ADL5201

ADL5201 (Rev. C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 26

Technical content

Wide Dynamic Range, High Speed, Digitally Controlled VGA Data Sheet ADL5201 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

−11.5 dB to +20 dB gain range 0.5 dB ± 0.1 dB step size 150 Ω differential input and output 7.5 dB noise figure at maximum gain OIP3 > 50 dBm at 200 MHz −3 dB upper frequency bandwidth of 700 MHz Multiple control interface options Parallel 6-bit control interface (with latch) Serial peripheral interface (SPI) (with fast attack) Gain up/down mode Wide input dynamic range Low power mode option Power-down control Single 5 V supply operation 24-lead, 4 mm × 4 mm LFCSP package

APPLICATIONS

High IF sampling receivers High output power IF amplification Instrumentation FUNCTIONAL BLOCK DIAGRAM +20dB ADL5201 SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN INTERFACE VPOS GND PWUP 0dB TO 31.5dBVIN+ MODE0, MODE1 VIN– PM VOUT+ VOUT– 09388-001 150Ω 150Ω LOGIC Figure 1. GENERAL DESCRIPTION The ADL5201 is a digitally controlled, variable gain, wide band- width amplifier that provides precise gain control, high IP3, and low noise figure. The excellent distortion performance and high signal bandwidth make the ADL5201 an excellent gain control device for a variety of receiver applications. The ADL5201 also incorporates a low power mode option that lowers the supply current. For wide input dynamic range applications, the ADL5201 provides a broad 31.5 dB gain range with 0.5 dB resolution. The gain is adjustable through multiple gain control interface options: parallel, serial peripheral interface, and up/down. Incorporating proprietary distortion cancellation techniques, the ADL5201 achieves an output IP3 of greater than 47 dBm at frequencies approaching 200 MHz for most gain settings. The ADL5201 is powered on by applying the appropriate logic level to the PWUP pin. The quiescent current of the ADL5201 is typically 80 mA in low power mode. When configured in high performance mode for more demanding applications, the quiescent current is 110 mA. When powered down, the ADL5201 consumes less than 7 mA and offers excellent input-to-output isolation. The gain setting is preserved during power-down. Fabricated on an Analog Devices, Inc., high speed SiGe process, the ADL5201 provides precise gain adjustment capabilities with good distortion performance and low phase error. The ADL5201 amplifier comes in a compact, thermally enhanced, 24-lead, 4 mm × 4 mm LFCSP package and operates over the temperature range of −40°C to +85°C.

Rev. C | Page 2 of 26 TABLE OF CONTENTS

REVISION HISTORY

1/15—Rev. B to Rev. C 9/13—Rev. A to Rev. B Changed Logic Pins Absolute Maximum Rating from 3.6 V to 12/12—Rev. 0 to Rev. A 10/11—Revision 0: Initial Version

Rev. C | Page 3 of 26 SPECIFICATIONS VS = 5 V , TA = 25°C, RS = RL = 150 Ω at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth VOUT < 2 V p-p (5.2 dBm) 700 MHz Slew Rate 5.5 V/ns Input Return Loss (S11) 100 MHz −18.73 dB Output Return Loss (S22) 100 MHz −18.8 dB INPUT STAGE VIN+ and VIN− pins Maximum Input Swing (Differential) Gain code = 111111 10.8 V p-p Differential Input Resistance 150 Ω Common-Mode Input Voltage 1.5 V CMRR Gain code = 000000 51.44 dB GAIN Maximum Voltage Gain Gain code = 000000 20 dB Minimum Voltage Gain Gain code = 111111 −11.5 dB Gain Step Size 0.5 dB Gain Flatness 30 MHz < fC < 200 MHz 0.285 dB Gain Temperature Sensitivity Gain code = 000000 0.0089 dB/°C Gain Step Response For VIN = 0.2 V, gain code = 111111 to 000000 15 ns Gain Conformance Error Over 10 dB gain range ±0.03 dB Phase Conformance Error Over 10 dB gain range 1.0 Degrees OUTPUT STAGE VOUT+ and VOUT− pins Output Voltage Swing At P1dB, gain code = 000000 10 V p-p Differential Output Resistance Differential 150 Ω NOISE/HARMONIC PERFORMANCE

46 MHz Gain code = 000000, high performance mode

Second Harmonic VOUT = 2 V p-p −86 dBc Third Harmonic VOUT = 2 V p-p −104 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 50 dBm

70 MHz Gain code = 000000, high performance mode

Second Harmonic VOUT = 2 V p-p −91 dBc Third Harmonic VOUT = 2 V p-p −103 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 51 dBm

140 MHz Gain code = 000000, high performance mode

Noise Figure 7.5 dB Second Harmonic VOUT = 2 V p-p −89 dBc Third Harmonic VOUT = 2 V p-p −97 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 51 dBm Output 1 dB Compression Point (OIP1dB) 19.8 dBm

300 MHz Gain code = 000000, high performance mode

Second Harmonic VOUT = 2 V p-p −85 dBc Third Harmonic VOUT = 2 V p-p −90 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 50 dBm

Rev. C | Page 5 of 26 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage, VPOS 5.5 V PWUP , A0 to A5, MODE0, MODE1, PM, LATCH −0.3 V to +3.6 V (not to exceed |VPOS − 0.5 V| at any time) Input Voltage, VIN+ and VIN− +3.6 V to −1.2 V Internal Power Dissipation 676.5 mW θJA (Exposed Paddle Soldered Down) 37.16°C/W θJC (at Exposed Paddle) 2.29°C/W Maximum Junction Temperature 140°C Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Lead Temperature (Soldering, 60 sec) 240°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO

Figure 5. Pin Configuration Table 3. Pin Function Descriptions 1, 4, EP GND Ground. The exposed paddle (EP) must be connected to a low impedance ground pad. 5 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode. 6 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode. 7 SDIO/A5 Serial Data Input/Output (SDIO). When CS is pulled low, SDIO is used for reading and writing to the SPI port. Bit 5 for Parallel Gain Control Interface (A5). 8 SCLK/A4 Serial Clock Input in SPI Mode (SCLK). Bit 4 for Parallel Gain Control Interface (A4). 9 GS1/CS/A3 MSB for Gain Step Size Control in Up/Down Mode (GS1). SPI Interface Select (CS). When serial mode is enabled, a logic low (0 V ≤ CS ≤ 0.8 V) enables the SPI interface. Bit 3 for Parallel Gain Control Interface (A3). 10 GS0/FA/A2 LSB for Gain Step Size Control in Up/Down Mode (GS0). word. Bit 2 for Parallel Gain Control Interface (A2). 11 UPDN_CLK/A1 Clock Interface for Up/Down Function (UPDN_CLK). Bit 1 for Parallel Gain Control Interface (A1). 12 UPDN_DAT/A0 Data Pin for Up/Down Function (UPDN_DAT). Bit 0 for Parallel Gain Control Interface (A0). 14, 16 VOUT+ Positive Output. 15, 17 VOUT− Negative Output. 19 PWUP Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part.

Table 7. Gain Code vs. Voltage Gain Lookup Table To write to the ADL5201, refer to the timing shown in Figure 51.

1. Set the R/W bit high using a 16-bit word and the timing
2. The SDIO is used as an output during the next sequence.

Figure 51. SPI Interface Read/Write Mode Timing Diagram

Figure 52. Simplified Schematic 1.6 V . The reference is not accessible and cannot be adjusted. 1.6 V , regardless of the state of the PWUP pin. used to determine the resulting gain and input/output resistances. RS is the source resistance that is connected to the input of the part. or power plane under this routing region and under the chokes. maximum gain setting, and it increases as the gain is reduced. The increase in noise figure is equal to the reduction in gain.

differential configuration for each channel. downloaded from the ADL5201 product page at www.analog.com. Figure 59. Evaluation Board Control Software

Figure 60. Evaluation Board Schematic

Table 9. Bill of Materials for Main Section a 0.1 μF capacitor to ground. removing R3 and installing a 0 Ω jumper at R4. a fully differential source. a 150 Ω balanced differential signal to a 50 Ω singled-end signal. L1 and L2 provide dc bias to the open-collector output. for single-ended applications. installing a shunt between Pin 1 and Pin 2 of the 3-pin header, PWUP . controlled via the USB microcontroller using the supplied software. capacitors allow for the generic placement of filter components.

Table 10. Bill of Materials for USB Section

COMPLIANT TOJEDEC STANDARDS MO-220-WGGD.

0.20 REF

0.25 MIN

0.05 MAX

0.02 NOM

Figure 64. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] registered trademarks are the prop erty of their respective owners.