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Preliminary Technical Data ADIS16220 Rev. PrE Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
Digital ±70 g accelerometer/vibration sensing 22 kHz sensor resonance 100.2 kSPS sample rate SPI-compatible serial interface Programmable data capture function: 3 channels, 1024 samples each 1 accelerometer/2 auxiliary ADCs (AIN1, AIN2) Manual trigger for user initiation Automatic trigger for periodic data capture Conditional trigger for condition-driven capture Digital temperature sensor output Digitally controlled sample rate Digitally controlled frequency response 2 auxiliary digital I/Os Digitally activated self-test Digitally activated low power mode Serial number and device ID Single-supply operation: 3.15 V to 3.6 V Operating temperature range: −40°C to +125°C 9.2 mm × 9.2 mm 16-terminal LGA
APPLICATIONS
Shock detection and event capture Condition monitoring Machine health Instrumentation, diagnostics Safety, shut-off sensing Security sensing, tamper detection GENERAL DESCRIPTION The ADIS16220 iSensor® is a digital vibration sensor that com- bines industry-leading iMEMS® sensing technology with a signal processor. It provides a buffer memory for high speed data capture, along with a convenient serial interface for data collection and configuration. The 22 kHz sensor resonance and 100.2 kSPS sample rate provide adequate response for most machine-health applications. The averaging/decimating filter provides optimization for lower bandwidth applications. An internal clock drives the data sampling system, which fills the buffer memory for user access. The data capture function has three different trigger modes. The automatic data collection allows for periodic wake-up and capture, based on a programma- ble duty cycle. The manual data capture mode allows the user to initiate a data capture, providing power and read-rate optimiza- tion. The event capture mode continuously updates the buffers and monitors them for a preset trigger condition. This mode captures pre-event data and post-event data and produces an alarm indicator for driving an interrupt. The serial peripheral interface (SPI) and data buffer structure provide convenient access to wide-bandwidth sensor data. The ADIS16220 also offers a digital temperature sensor, digital power supply measurements, and peak output capture. The ADIS16220 comes in a 9.2 mm × 9.2 mm × 3.9 mm LGA package that meets the Pb-free solder reflow profile require- ments per JEDEC J-STD-020 and has an extended operating temperature range of −40°C to +125°C. FUNCTION BLOCK DIAGRAM 07980-001 CAPTURE BUFFER ADIS16220 FILTER ALARMSI/OSELF-TEST USER CONTROL REGISTERS SPI PORT OUTPUT DATA REGISTERS CONTROLLER CLOCK MEMS SENSOR TEMP SENSOR POWER MANAGEMENT CS SCLK DIN DOUT GND VDDRSTDIO1 DIO2 AIN1 AIN2 VREF Figure 1.
ADIS16220 Preliminary Technical Data Rev. PrE | Page 2 of 16 TABLE OF CONTENTS
Preliminary Technical Data ADIS16220 Rev. PrE | Page 3 of 16 SPECIFICATIONS TA = −40°C to +125°C, VDD = 3.3 V , ±1 g, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit ACCELEROMETER Measurement range TA = 25°C −70 +70 g Sensitivity T A = 25°C 19.073 mg/LSB Sensitivity Error TA = 25°C ±5 % Sensitivity Temperature Coefficient ±310 ppm/°C Nonlinearity With respect to full scale ±0.2 ±2 % Cross-Axis Sensitivity ±2 % Alignment Error With respect to package ±1 Degree Offset Error TA = 25°C −19.1 +19.1 g Offset Temperature Coefficient ±5 mg/°C Output Noise TA = 25°C, AVG_CNT = 0x0000 507 mg rms Output Noise Density TA = 25°C, 10 Hz to 1 kHz 4 mg/√Hz Sensor Resonant Frequency 22 kHz Self-Test Response 917 1310 1703 LSB AUXILIARY INPUTS (AIN1, AIN2) Resolution1 12 Bits Sensitivity 305.18 μV/LSB Integral Nonlinearity 2.4 LSB Differential Nonlinearity 4 LSB Offset VDD/2 V Offset Error ±20.4 LSB Input Range 0 VDD V Input Capacitance 20 pF ON-CHIP VOLTAGE REFEERENCE Output Level 2.5 V Accuracy ±5 mV Temperature Coefficient ±40 ppm/°C Output Impedance 70 Ω LOGIC INPUTS2 Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V Logic 1 Input Current, IINH V IH = 3.3 V ±0.2 ±1 μA Logic 0 Input Current, IINL V IL = 0 V All Except RST −40 −60 μA RST −1 mA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS2 Output High Voltage, VOH I SOURCE = 1.6 mA 2.4 V Output Low Voltage, VOL I SINK = 1.6 mA 0.4 V FLASH MEMORY Endurance3 10,000 Cycles Data Retention4 T J = 85°C 10 Years START-UP TIME5 Initial Startup 160 ms Reset Recovery (RST) RST or software (GLOB_CMD) 23 ms Sleep Mode Recovery 2.3 ms
ADIS16220 Preliminary Technical Data Rev. PrE | Page 4 of 16 Parameter Conditions Min Typ Max Unit CONVERSION RATE AVG_CNT = 0x0000 100.2 kSPS Clock Accuracy 3 % POWER SUPPLY Operating voltage range, VDD 3.15 3.3 3.6 V Power Supply Current Capture mode, TA = 25°C 38 46 mA Sleep mode, TA = 25°C 230 μA Sleep mode, TA = 85°C 250 400 μA Sleep mode, TA = 125°C 600 1000 μA 1 A 12-bit analog-to-digital converter is used to create a 14-bit digital scale for the AIN1 and AIN2 inputs. 2 The digital I/O signals are 5 V tolerant. 3 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C. 3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. 5 The start-up times presented do not include the data capture time, which is dependent on the AVG_CNT register settings.
Table 4. Package Characteristics
Note that all registers in Table 8 consist of two bytes. All unused memory locations are reserved for future use. Table 8. User Register Memory Map 1 Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte, plus 1.
- DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
Figure 13. SPI Communication Bit Sequence
in the buffer memory to load into the CAPT_BUFx registers. Figure 14. Acceleration Capture Buffer Structure and Operation; Table 9. CAPT_PNTR Bits Descriptions Table 10. Capture Output Register Formats Table 11. Acceleration Data Format Table 12. Analog Input Data Format where CAPT_SUPPLY = 2703 LSB. For example, when CAPT_TEMP = 1331, the result is 0.1°C. Table 13. CAPT_CTRL Bit Descriptions set in ALM_CTRL, ALM_MAGA, ALM_MAG1, and ALM_MAG2.
waits for the data capture command. Table 14. CAPT_PRD Register Bit Descriptions Table 15. Example Event Mode Configuration Sequence meets the preset conditions in the alarm registers (ALM_xxxx). Table 16. ALM_CTRL Bit Descriptions Table 17. ALM_MAGA Bit Descriptions twos complement, 19.073 mg/LSB. Table 18. ALM_MAG1 and ALM_MAG2 Bit Descriptions twos complement, 305.18 μV/LSB. Table 19. ALM_MAGS Bit Descriptions [11:0] Data bits for temperature or supply threshold setting. format, depending on the ALM_CTRL[4] setting. Table 20. Example Event Mode Configuration Sequence alarms by setting ALM_CTRL[7:0] = 0x39. alarm indicator by setting DIO_CTRL[7:0] = 0x1F. setting CAPT_CTRL[7:0] = 0x5A. within normal limits for the execution times listed in Table 21.
Table 21. GLOB_CMD Bit Descriptions
1 This indicates the typical duration of time between the command write and
the device returning to normal operation. resolution using the 1024-sample capture buffer. Figure 15. Simplified Signal Processing Flowchart Table 22. AVG_CNT Bit Descriptions Table 23. ACCL_NULL Bit Descriptions sensitivity. See Figure 15 for impact on output. Table 24. AIN1_NULL, AIN2_NULL Bit Descriptions sensitivity. Signal path is similar to Figure 15. capture events and can help prevent undesirable interruptions. Table 25. DIO_CTRL Bit Descriptions
Table 26. GPIO_CTRL Bit Descriptions SCLK clocks is not a multiple of 16 during a SPI transfer. Table 27. DIAG_STAT Bit Descriptions which reflects the response associated with the self-test setting. Table 28. MSC_CTRL Bit Descriptions Table 29. ST_DELTA Bit Descriptions Table 30. FLASH_CNT Bit Descriptions number for each device within a given lot. Table 31. LOT_ID1 Bit Descriptions Table 32. LOT_ID2 Bit Descriptions Table 33. SERIAL_NUM Bit Descriptions
protect these devices from ESD during shipping and handling. levels of shock to these devices. simplifies the connection to an existing processor system. has a presolder reflow thickness of approximately 0.005 inches. Figure 5. J1 and J2 are dual-row, 2 mm (pitch) connectors that Number 3625/12 (ribbon cable).
1 SCLK
2 DOUT
3 DIN
13 VDD
9 RST
16 GND
Figure 16. Electrical Schematic Figure 17. PCB Assembly View and Dimensions
1.000 BSC
0.797 BSC
Figure 18. 16-Terminal Stacked Land Grid Array [LGA] registered trademarks are the prop erty of their respective owners.