ADIS16204 (Rev. B)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 24
Technical content
Programmable High-g Digital Impact Sensor and Recorder ADIS16204 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
FEATURES
Dual-axis sensing, ±70 g, ±37 g 14-bit resolution Impact peak-level sample-and-hold RSS output Programmable event recorder
400 Hz double-pole Bessel sensor response
Digitally controlled sensitivity and bias Digitally controlled sample rate, up to 4096 SPS Programmable condition monitoring alarms Auxiliary digital I/O Digitally activated self-test Embedded temperature sensor Programmable power management SPI-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: +3.0 V to +3.6 V 4000 g powered shock survivability
APPLICATIONS
Condition monitoring of valuable goods Safety, shut-off sensing Impact event recording Security sensing, tamper detection FUNCTIONAL BLOCK DIAGRAM SCLK DIN DOUT CS RST DIO1 DIO2 SPI PORT TEMPERATURE SENSOR SELF-TEST POWER MANAGEMENT AUXILIARY I/O EVENT CAPTURE BUFFER MEMORY ALARMS DIGITAL CONTROL SIGNAL CONDITIONING AND CONVERSION DIGITAL PROCESSING ADIS16204 VDD COM AUX ADC AUX DAC VREF INERTIAL MEMS SENSOR 06448-001 Figure 1. GENERAL DESCRIPTION The ADIS16204 is a fully-contained programmable impact sensor in a single compact package enabled by the Analog Devices, Inc. iSensor™ integration. By enhancing the Analog Devices iMEMS® sensor technology with an embedded signal processing solution, the ADIS16204 provides tunable digital sensor data in a convenient format that can be accessed using a serial peripheral interface (SPI). The SPI provides access to measurements for dual-axis linear acceleration, a root sum square (RSS) of both axes, temperature, power supply, an auxiliary analog input, and an event capture buffer memory. Easy access to digital sensor data provides users with a system-ready device, reducing development time, cost, and program risk. Unique characteristics of the end system are accommodated easily through several built-in features, such as a single command in-system bias null/offset calibration, along with convenient sample rate control. The ADIS16204 offers the following embedded features, which eliminate the need for external circuitry and provide a simplified system interface: Peak sample-and-hold Programmable event recording (dual, 1K × 16 bit) RSS output (total shock in the XY plane) Configurable alarms Auxiliary 12-bit ADC and DAC Configurable digital I/O port Digital self-test function The ADIS16204 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. The ADIS16204 is available in a 9.2 mm × 9.2 mm × 3.9 mm laminate-based land grid array (LGA) package with a tem- perature range of −40°C to +105°C. OBSOLETE
Rev. B | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
12/09—Rev. A to Rev. B 10/07—Rev. 0 to Rev. A 6/07—Revision 0: Initial Version OBSOLETE
Rev. B | Page 3 of 24 SPECIFICATIONS TA = −40oC to +105°C, VDD = 3.3 V , unless otherwise noted. Table 1. Parameter Conditions Axis Min Typ Max Unit ACCELEROMETER Output Full-Scale Range X ±70 g Y ±37 g Sensitivity X 17.125 mg/LSB Y 8.407 mg/LSB Nonlinearity 0.2 % Sensor-to-Sensor Alignment Error 0.1 Degrees Cross-Axis Sensitivity −5 +5 % Resonant Frequency 24 kHz OFFSET Zero-g Output1 X 0.2 g Y 0.2 g NOISE Noise Density 10 Hz − 400 Hz, no postfiltering 1.8 m g/√Hz FREQUENCY RESPONSE Sensor Bandwidth (−3 dB) 2-pole Bessel 360 400 440 Hz Temperature Drift |25°C − TMIN| or |TMAX − 25°C| 2 Hz ACCELEROMETER SELF-TEST STATE2 Output Change When Active At 25°C X 254 LSB Output Change When Active Y 518 LSB TEMPERATURE SENSOR Output at 25°C 1278 LSB Scale Factor −2.13 LSB/°C ADC INPUT Resolution 12 Bits Integral Nonlinearity (INL) ±2 LSB Differential Nonlinearity (DNL) ±1 LSB Offset Error ±4 LSB Gain Error ±2 LSB Input Range 0 2.5 V Input Capacitance During acquisition 20 pF ON-CHIP VOLTAGE REFERENCE 2.5 V Accuracy At 25°C −10 +10 mV Reference Temperature Coefficient ±40 ppm/ oC Output Impedance 70 Ω DAC OUTPUT 5 kΩ/100 pF to GND Resolution 12 Bits Relative Accuracy For Code 101 to Code 4095 4 LSB Differential Nonlinearity (DNL) 1 LSB Offset Error ±5 mV Gain Error ±0.5 % Output Range 0 to 2.5 V Output Impedance 2 Ω Output Settling Time 10 μs OBSOLETE
Rev. B | Page 4 of 24 Parameter Conditions Axis Min Typ Max Unit LOGIC INPUTS3 Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V Logic 1 Input Current, IINH VIH = VDD ±0.2 ±1 μA Logic 0 Input Current, IINL V IL = 0 V −40 −60 μA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output High Voltage, VOH I SOURCE = 1.6 mA 2.4 V Output Low Voltage, VOL I SINK = 1.6 mA 0.4 V SLEEP TIMER Timeout Period4 0.5 128 Seconds START-UP TIME Initial 130 ms Reset recovery 2.5 ms FLASH MEMORY Endurance5 20,000 Cycles Data Retention6 T J = 85°C 20 Years CONVERSION RATE Maximum Throughput Rate 4096 SPS Minimum Throughput Rate 2.066 SPS POWER SUPPLY Operating Voltage Range, VDD 3.0 3.3 3.6 V Power Supply Current Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 910 Hz), at 25°C 12 15 mA Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 1024 Hz), at 25°C 37 43 mA Sleep mode, at 25°C 150 μA 1 Note that gravity can impact this number; zero-g condition assumes both axes oriented normal to the earth’s gravity. 2 Self-test response changes as the square of VDD. 3 Note that the inputs are +5 V tolerant. 4 Guaranteed by design. 5 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +105°C. 6 Retention lifetime equivalent at junction temperature (TJ), 55°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. OBSOLETE
Rev. B | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Acceleration (Any Axis, Unpowered, 0.5 ms) 4000 g Acceleration (Any Axis, Powered, 0.5 ms) 4000 g VCC to COM −0.3 V to +6.0 V Digital Input/Output Voltage to COM −0.3 V to +5.5 V Analog Inputs to COM −0.3 V to +3.5 V Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION OBSOLETE
ADC channel, and the event-capture buffer memory. always first in register read sequences. Table 5. Output Bit Assignments registers are updated with new data, the ND bit goes to a 1 state. output data, Bit D13 and Bit D12 are assigned don’t care status. provides an example of the SPI sequence. Table 6. Data Output Register Information 1 25°C, nominal output is equal to 1278 LSB. 3 This is a measure of the total shock absorbed by the package in the XY plane, and is the result of a root sum square of X and Y acceleration measurements. 4 See the Alarm Detection and Event Capture section for more details. Figure 23. Example of an Output Timing/Coding Diagram
memory location for storing the latest configuration contents. of each nonvolatile register must be stored to flash manually. made available in the COMMAND register, provides this function. Table 7. Control Register Mapping 1 In order to establish nonvolatile status, the flash memory must be updated after updating the control registers. 2 Bit 8 clears after the internal self-test sequence completes, effectively making this bit volatile.
the error flag, which is required for flash memory access. ensures a stable DAC output voltage during updates. ADIS16204 calibration, see the Calibration section. Event Capture section for more information. Table 8. COMMAND Register Definition Table 9. COMMAND Bit Descriptions
10 Reset-capture pointer (set CAPT_PNTR to 0x0001)
9 Clear capture flash (nonvolatile back-up)
8 Clear capture buffer (SRAM)
7 Software reset
6 Copy capture buffer to nonvolatile flash
5 Clear peak output register s, (reset them to 0x0000)
4 Clear status register (reset all bits to 0)
3 Flash update—saves nonvolatile register settings
2 DAC data latch
1 Factory calibration restore
0 Autonull
resolution to separate a minor bump from a hard brake event. y is the calibrated output data. m is the scale factor multiplier [XACCL_SCALE/YACCL_SCALE]. x is the precalibration data. b is the offset adder [XACCL_NULL/YACCL_NULL]. Table 10. XACCL_NULL Register Definition 1 Scale is the weight of each LSB. Table 11. YACCL_NULL Register Definition 1 Scale is the weight of each LSB. Table 12. XACCL_SCALE Register Definition 1 Scale is the weight of each LSB. 2 Equates to a scale factor of one.
Table 13. YACCL_SCALE Register Definition 1 Scale is the weight of each LSB. 2 Equates to a scale factor of one. Table 14. Calibration Register Bit Descriptions NS is the increment setting. this register are nonvolatile. Table 15. SMPL_PRD Register Definition Table 16. SMPL_PRD Bit Descriptions
7 Time base
SCLK can run at a rate up to 1 MHz. The sample rate setting also affects the power dissipation. Table 17. SLP_CNT Register Definition 1 Scale is the weight of each LSB. Table 18. SLP_CNT Bit Descriptions The auxiliary DAC provides a 12-bit level adjustment function. The AUX_DAC register controls the operation of this feature. set after every reset and power cycle event. Table 19. AUX_DAC Register Definition the 2.5 V range out of output voltage. Table 20. AUX_DAC Bit Descriptions
flexibility of both input (read) and output (write) operations. Table 21. GPIO_CTRL Register Definition Table 22. GPIO_CTRL Bit Descriptions
9 General-purpose I/O Line 2 polarity
8 General-purpose I/O Line 1 polarity
1 General-purpose I/O Line 2, data direction control
0 General-purpose I/O Line 1, data direction control
along with their appropriate control registers. Table 23. Status and Diagnostic Functions indicator, the duty cycle is 20% (±10% tolerance). by reading Bit 5 of the STATUS register. The device is configured to perform a self-test at power on. the new data bit is not active while in this mode. Table 24. MSC_CTRL Register Definition Table 25. MSC_CTRL Bit Descriptions
11 Store capture to flash after capture buffer fills up
10 Self-test at power-on
9 Not used
8 Self-test enable (temporary, bit is volatile)
2 Data-ready enable
1 Data-ready polarity
0 Data-ready line select
mum value of 32,767, it wraps around to zero and starts over. Table 26. ENDURANCE Register Definition
appropriate register access and bit assignment for each flag. cally reset to zero when the error condition no longer exists. command to the COMMAND register (write a 1 to Bit 4). priate error flag bit returns to 1 during the next sampling cycle. All bits in the STATUS register are volatile. Table 27. STATUS Register Definition Table 28. STATUS Bit Descriptions
12 Capture buffers full
9 Alarm 2 status
8 Alarm 1 status
5 Self-test diagnostic error flag
4 Not used
3 SPI communications failure
2 Flash update failed
which reduces the external processing burden for this function. available for configuring the alarms.
- Program the Output Data to Monitor.
Write 0x23 to Address 0x29 [ALM_CTRL].
- Program the Trigger Levels and Polarity.
Write 0x81 to Address 0x21 [ALM_MAG1]. Write 0xB0 to Address 0x20 [ALM_MAG1]. Write 0x83 to Address 0x23 [ALM_MAG2]. Write 0x70 to Address 0x22 [ALM_MAG2].
- Set Up a Digital I/O Line as an Alarm Indicator.
Write 0x07 to Address 0x28 [ALM_CTRL]. as a data-ready or general-purpose I/O pin.
Table 29. Alarm and Event Capture Configuration Registers Table 30. ALM_CTRL Register Definition Table 31. ALM_CTRL Bit Descriptions
0000 Disable
0001 Power supply
0010 X-acceleration
0011 Y-acceleration
0100 Auxiliary ADC
0101 Temperature sensor
1000 XY RSS acceleration
7 Not used
6 Capture trigger activation, Alarm 2
5 Not used
4 Capture trigger activation, Alarm 1
3 Not used
2 Alarm indicator, using DIO1/2
1 Alarm indicator polarity
0 Alarm indicator line selection
Table 32. ALM_MAG1 Register Definition Table 33. ALM_MAG2 Register Definition Table 34. ALM_MAG1/ALM_MAG 2 Bit Designations
15 Comparison polarity
14 Not used
The ADIS16204 also provides a dual-channel, capture function. Figure 24. Event Capture Example The event capture buffers use the alarms as their trigger source. through Step 5 to complete the event capture setup.
- Program the Data Source to Capture.
Write 0x23 to Address 0x39 [CAPT_CFG].
- Configure the Capture Backup Memory.
event capture back-up function, effectively making it nonvolatile. Write 0x08 to Address 0x35 [MSC_CTRL].
- Clear the Capture Memory Locations.
Write 0x03 to Address 0x3F [COMMAND].
- Set Up a Digital I/O Line as an Alarm Indicator.
- Set Each Alarm as a Trigger Source for the Buffer.
necessary. It also arms both triggers for the event recorder. Write 0x57 to Address 0x28 [ALM_CTRL]. Write 0x50 to Address 0x28 [ALM_CTRL]. Table 35. CAPT_CFG Register Definition Table 36. CAPT_CFG Bit Descriptions Power of two setting determines length. Power of two setting determine length. 1010b = 10d, which corresponds to 210 = 1024 samples. ADIS16204’s capture buffers: CAPT_BUF_1 and CAPT_BUF_2. Figure 25. Event Capture Buffer Memory Structure Table 37. Capture Register Definitions Table 38. CAPT_BUF_1 and CAPT_BUF_2 Bit Descriptions
15 Not used
14 Error/alarm condition (use to identify transition between
Table 39. CAPT_PNTR Register Definition Table 40. CAPT_PNTR Bit Descriptions
profile based upon the specific application. in a more reliable assembly. Figure 26. Acceptable Solder Reflow Profiles Table 41. Acceptable Solder Reflow Profiles1
1.000 BSC
0.797 BSC
Figure 27. 20-Terminal Land Grid Array [LGA]
Rev. B | Page 23 of 24 NOTES OBSOLETE
Rev. B | Page 24 of 24 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06448-0-12/09(B) OBSOLETE