ADIS16201

ADIS16201 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 31

Technical content

Inclinometer/Accelerometer Data Sheet ADIS16201 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2006–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Dual-axis inclinometer/accelerometer measurements 12-, 14-bit digital inclination/acceleration sensor outputs ±1.7 g accelerometer measurement range ±90° inclinometer measurement range, linear output 12-bit digital temperature sensor output Digitally controlled sensitivity and bias calibration Digitally controlled sample rate Digitally controlled frequency response Dual alarm settings with rate/threshold limits Auxiliary digital I/O Digitally activated self test Digitally activated low power mode SPI®-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: 3.0 V to +3.6 V 3500 g powered shock survivability

APPLICATIONS

Platform control, stabilization, and leveling Tilt sensing, inclinometers Motion/position measurement Monitor/alarm devices (security, medical, safety) FUNCTIONAL BLOCK DIAGRAM SCLK DIN DOUT CS RST DIO0 DIO1 SPI PORT TEMPERATURE SENSOR SELF-TEST POWER MANAGEMENT AUXILIARY I/OALARMS DIGITAL CONTROL SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING ADIS16201 VDD COM AUX ADC AUX DAC VREF DUAL-AXIS ACCELEROMETER 05462-001 Figure 1. GENERAL DESCRIPTION The ADIS16201 is a complete, dual-axis acceleration and inclination angle measurement system available in a single compact package enabled by the Analog Devices iSensor™ integration. By enhancing the Analog Devices iMEMS® sensor technology with an embedded signal processing solution, the ADIS16201 provides factory calibrated and tunable digital sensor data in a convenient format that can be accessed using a serial peripheral interface (SPI). The SPI interface provides access to measurements for dual-axis linear acceleration, dual- axis linear inclination angle, temperature, power supply, and one auxiliary analog input. Easy access to calibrated digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. Unique characteristics of the end system are accommodated easily through several built-in features, such as a single command in-system offset calibration, along with convenient sample rate and bandwidth control. The ADIS16201 offers the following embedded features, which eliminate the need for external circuitry and provide a simplified system interface:

• Configurable alarm function
• Auxiliary 12-bit ADC
• Auxiliary 12-bit DAC
• Configurable digital I/O port
• Digital self-test function The ADIS16201 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. The ADIS16201 is available in a 9.2 mm × 9.2 mm × 3.9 mm laminate-based land grid array (LGA) package with a temperature range of −40°C to +125°C.

Rev. E | Page 2 of 31 TABLE OF CONTENTS

REVISION HISTORY

3/2019—Rev. D to Rev. E 7/2018—Rev. C to Rev. D Deleted Figure 31 and Figure 32; Renumbered Sequentially ... 13 Changed Applications Section to Applications Information Added Power Supply Considerations Section, Power-On-Reset Function Section, Transient Current from VDD Ramp Rate Deleted Power-On Reset Operation Section, Figure 40, Second- Level Assembly Section, Figure 41, and Table 32; Renumbered 8/2013—Rev. B to Rev. C Changed Digital Input/Output Voltage to COM Parameter from Changes to SMPL_PRD Register Definition Section, Table 24, 4/2013—Rev. A to Rev. B 5/2006—Rev. 0 to Rev. A 3/2006—Revision 0: Initial Version

Rev. E | Page 3 of 31 SPECIFICATIONS TA = −40oC to +125°C, VDD = 3.3 V , tilt = 0°, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INCLINOMETER Each axis Input Range Operable to ~±90 degrees ±70 Degrees Relative Accuracy1 ±15 degrees, 25°C, max filter ±0.25 Degrees ±30 degrees, 25°C, max filter ±0.5 Degrees ±60 degrees, 25°C, max filter ±1.5 Degrees Sensitivity ±60 degrees, 25°C 9.9 10 10.1 LSB/degrees Sensitivity over Temperature ±30 degrees ±50 ppm/°C Offset1 At 25°C 2037 2048 2059 LSB Offset over Temperature ±0.082 LSB/°C ACCELEROMETER Each axis Input Range2 At 25°C ±1.7 g Nonlinearity2 % of full scale ±0.5 ±2.5 % Alignment Error X sensor to Y sensor ±0.1 Degrees Cross Axis Sensitivity ±2 % Sensitivity At 25°C 2.140 2.162 2.184 LSB/m g Sensitivity over Temperature ±50 ppm/°C Offset At 25°C, 0 g 8151 8192 8233 LSB Offset over Temperature ±0.33 LSB/°C ACCELEROMETER NOISE PERFORMANCE Output Noise At 25°C, no averaging 22 LSB rms Noise Density At 25°C, no averaging 0.37 LSB/√Hz rms ACCELEROMETER FREQUENCY RESPONSE Sensor Bandwidth 2250 Hz Sensor Resonant Frequency 5.5 kHz ACCELEROMETER SELF-TEST STATE3 Output Change When Active At 25°C 372 708 1040 LSB TEMPERATURE SENSOR Output at 25°C 1278 LSB Scale Factor −2.13 LSB/°C ADC INPUT Resolution 12 Bits Integral Nonlinearity ±2 LSB Differential Nonlinearity ±1 LSB Offset Error ±4 LSB Gain Error ±2 LSB Input Range 0 2.5 V Input Capacitance During acquisition 20 pF ON-CHIP VOLTAGE REFERENCE 2.5 V Accuracy At 25°C −10 +10 mV Reference Temperature Coefficient ±40 ppm/°C Output Impedance 70 Ω DAC OUTPUT 5 kΩ/100 pF to GND Resolution 12 Bits Relative Accuracy For Code 101 to Code 4095 4 LSB Differential Nonlinearity 1 LSB Offset Error ±5 mV Gain Error ±0.5 % Output Range 0 to 2.5 V

Rev. E | Page 4 of 31 Parameter Conditions Min Typ Max Unit Output Impedance 2 Ω Output Settling Time 10 μs LOGIC INPUTS Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V Logic 1 Input Current, IINH V IH = VDD ±0.2 ±1 μA Logic 0 Input Current, IINL V IL = 0 V −40 −60 μA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output High Voltage, VOH I SOURCE = 1.6 mA 2.4 V Output Low Voltage, VOL I SINK = 1.6 mA 0.4 V SLEEP TIMER Timeout Period4 0.5 128 Seconds FLASH MEMORY Endurance5 20,000 Cycles Data Retention6 T J = 85°C 20 Years CONVERSION RATE Minimum Conversion Time 244 μs Maximum Conversion Time 484 ms Maximum Throughput Rate 4096 SPS Minimum Throughput Rate 2.066 SPS POWER SUPPLY Operating Voltage Range VDD 3.0 3.3 3.6 V Power Supply Current Normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz), at 25°C 11 14 mA Fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz), at 25°C 36 42 mA Sleep mode, at 25°C 500 750 μA Turn-On Time7 130 ms 1 X-ray exposure may degrade this performance metric. 2 Guaranteed by iMEMs packaged part testing, design, and/or characterization. 3 Self-test response changes as the square of VDD. 4 Guaranteed by design. 5 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 6 Retention lifetime equivalent at junction temperature (TJ) 85°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature. 7 The start-up time defines the time from VDD > 3.0 V to the first output register update. This parameter does not account for filter settling, which depends on the SMPL_PRD and AVG_CNT settings.

Table 4. Package Characteristics

Figure 4. Pin Configuration Table 5. Pin Function Descriptions out on the falling edge of the SCLK. 4 CS I Chip Select, Active Low. This input frames the serial data transfer. 5, 6 DIO0, DIO1 I/O Multifunction Digital I/O Pins. 8, 10 AUX COM S Auxiliary Grounds. Connect to GND for proper operation. 9 RST I Reset, Active Low. This input resets the embedded microcontroller to a known state. 12 AUX DAC O Auxiliary DAC Analog Voltage Output. 13 VDD S +3.3 V Power Supply. 14 AUX ADC I Auxiliary ADC Analog Input Voltage. 15 VREF O Precision Reference Output. 16 COM S Common. Reference point for all circuitry in the ADIS16201. 1 S = Supply; O = Output; I = Input.

Rev. E | Page 13 of 31 THEORY OF OPERATION The ADIS16201 is a complete dual-axis digital inclinometer/ accelerometer that uses Analog Devices’ surface-micromachining process and embedded signal processing to make a functionally complete, low cost dual-axis sensor. The ADIS16201 offers a fully calibrated, dual–axis micromachined sensor element that develops independent analog signals representative of the acceleration levels applied to the part. An on-board precision ADC samples the acceleration signals, along with the power supply voltage, an internal temperature signal, and the auxiliary analog input signal. These signals are then processed and latched into addressable output registers. The serial peripheral interface (SPI) provides convenient, digital access to these registers. In addition, the acceleration signals are further processed to produce inclination angle data for both axes. The inclination angle data represents the tilt away from the ideal plane, which in this case, is normal to the earth’s gravitational force. This calculation assumes that no force outside of the earth’s gravitational force is acting on the device. ACCELEROMETER OPERATION The acceleration sensor used in the ADIS16201 is a surface- machined, polysilicon structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Acceleration causes a deflection in the differential capacitor structure that includes both fixed plates and plates that are attached to the moving mass. The fixed plates are driven by a set of square waves that are 180 o out-of-phase from one another. Acceleration deflects the beam and unbalances the differential capacitor, resulting in an output square wave whose amplitude is proportional to acceleration. Phase sensitive demodulation techniques rectify the signal and determine the direction of the acceleration. The output of the demodulator is amplified, digitized, and processed to remove any process variations and sensitivities to supply variations. INCLINOMETER OPERATION The ADIS16201 computes incline angles, with respect to the horizontal plane (normal to the gravity vector), using the following formulas: arcsin 1 X X a g arcsin 1 Y Y a g Incline angle results have the least sensitivity to noise and quantization when the accelerometer orientation is perpendicular to the gravity vector (incline angle = 0°) and have the most sensitivity to noise when the accelerometer orientation is parallel with the gravity vector (incline angle = 90°). Any linear acceleration, including vibration, causes error in the angle measurements. TEMPERATURE SENSOR The TEMP_OUT control register allows the end user to monitor the internal temperature of the ADIS16201 to an accuracy of ±5°C. The output data is presented in a straight binary format with a nominal 25°C die temperature correlating to a 1278 LSB read through the TEMP_OUT output data register. The temperature scale factor of −2.129 LSB/°C allows for a resolution of less than 0.5°C in the temperature reading within the output data register.

4-wire, industry standard, serial peripheral interface (SPI). Applications Information section. the register address, and the second cycle is for reading the data. Table 6 displays the appropriate bit map for the read command. available. When a register is read, this bit is set to a 0 logic level. be used to simplify system-level processing requirements. registers, along with their addresses, can be found in Table 7. defined in Table 6 during the next SPI cycle. Table 6. Register Read Command Bit Map 1 The W/R bit is always 0 for read commands.

Table 7. Data Output Register Information Table 8. Output Coding Example, XACCL_OUT1, 2 1 Two MSBs have been masked off and are not considered in the coding. 2 Nominal sensitivity (2.162 LSB/mg) and zero offset null performance are assumed.

Rev. E | Page 16 of 31 PROGRAMMING AND CONTROL CONTROL REGISTER OVERVIEW The ADIS16201 offers many programmable features that are controlled by writing commands to the appropriate control registers using the SPI. For added system flexibility and programmability, the following sections describe these controls and specify the 28 digital control registers that are available using the SPI interface. A high level listing of these registers is given within Table 9. The following sections expand upon the functionality of each of these control registers, providing for the full clarification of the behavior of each of the control registers. Available control modes for the device include selectable sample rates for reading the seven output vectors, configurable output data, alarm settings, control of the on-board 12-bit auxiliary DAC, handling of the two general-purpose I/O lines, facilitation of the sleep mode, enabling the self-test mode, and other miscellaneous control functions. The conversion process is repeated continually, providing for continuous update of the seven output registers. The new data ready bit (ND) flags bits common to all seven output registers, allowing the completion of the conversion process to be tracked via the SPI. As an alternative, the digital I/O lines can be configured through software control to create a data-ready hardware function that can signal the completion of the conversion process. Two independent alarms provide the ability to monitor any one of the seven output registers. They can be configured to report an alarm condition on either fixed thresholds or rates of change. The alarm conditions are monitored through the SPI. In addition, the user can configure the digital I/O lines through software control to create an alarm function that allows for monitoring of the alarm conditions through hardware. The seven output signals noted above are calibrated independ- ently at the factory, delivering a high degree of accuracy. In addition, the user has access to independent offset and scale factors for each of the two acceleration and inclination output vectors. This allows independent scaling and level adjustment control of any one these four registers prior to the values being read via the SPI. In turn, field level calibrations can be implemented within the sensor itself using these offset and scale variables. System level commands provided within the sensor include automatic zeroing of the four outputs using a single null command via the SPI. In addition, the original factory calibration settings can be recovered at any point, using a simple factory reset command. CONTROL REGISTER ACCESS The control registers within the ADIS16201 are based upon a 16-bit/2-byte format, and they are accessed via the SPI. The SPI operates in full duplex mode with the data clocked out of the DOUT pin at the same time data is clocked in through the DIN pin. All commands written to the ASIS16201 are categorized as write commands or read commands. All write commands are self-contained and take place within a single cycle. Each read command requires two cycles to complete; the first cycle is for transmitting the register address, and the second cycle is for reading the data. During the second cycle, when the data out line is active, the data in line is used to receive the next sequential command. This allows for overlapping the commands. For more information on basic SPI port operation, see the Applications Information section. The read and write commands are identified through the most significant bit (MSB), B15, of the received data. Write a 1 to B15 to indicate a write command. Write a 0 to B15 to indicate a read command. Bit B13 through Bit B8 contain the address of the control register that is being accessed. The remaining eight bits of the write command contain the data that is being written into the part, whereas the remaining eight bits of the read command contain don’t care levels. Given that the data within the write command is eight bits in length, the 8-bit data format is the default byte size. A write command operates on a single chip select cycle, as shown in Figure 32. The read command operates on a 2-chip select cycle basis, as seen in Figure 31. All 64 bytes of register space are accessed using the 6-bit address. Data written into the device is one byte at a time with the address of each byte being explicitly called out in the write command. Conversely, data being read from the device consists of two, back-to-back, 8-bit variables being sent out, with the first byte out corresponding to the upper address (odd number address) and the second byte relating to the next lower address space (even number address). For example, a data read of Address 03h results in the data from Address 03h being fed out followed by data from Address 02h. Likewise, a data read of Address 02h results in the same data stream being output from the device. The ADIS16201 is a flash-based device with the nonvolatile functional registers implemented as flash registers. Take into account the endurance limitation of 20,000 writes when considering the system-level integration of these devices. The nonvolatile column in Table 9 indicates which registers are recovered upon power-up. The user must instigate a manual flash update command (using the command register) in order to store the nonvolatile data registers, once they are configured properly. When performing a manual flash update command, the user needs to ensure that the power supply remains within limits for a minimum of 50 μs after the write is initiated. This ensures a successful write of the nonvolatile data.

Table 9. Control Register Mapping Table 10. Register Write Command Bit Map Figure 32. Control Register Write Command Sequence of SPI Signals

The control registers in the ADIS16201 are 16 bits in length. numerical assignments that are displayed in the following table. scaling information, bit maps, addresses, and default values. a high degree of accuracy and simpler system implementation. utilize the straight binary format. x represents the raw data prior to calibration. errors in the inclination and acceleration data output registers. stimulus to excite the ADIS16201. 1 Scale is the weight of each LSB. contents of this register are nonvolatile. Table 11. XACCL_OFF Bit Designations

1 Scale is the weight of each LSB. contents of this register are nonvolatile. Table 12. XACCL_SCALE Bit Designations 1 Scale is the weight of each LSB. contents of this register are nonvolatile. Table 13. YACCL_OFF Bit Designations 1 Scale is the weight of each LSB. contents of this register are nonvolatile. Table 14. YACCL_SCALE Bit Designations 1 Scale is the weight of each LSB. contents of this register are nonvolatile. Table 15. XINCL_OFF Bit Designations 1 Scale is the weight of each LSB. Table 16. XINCL_SCALE Bit Designations 1 Scale is the weight of each LSB. of this register are nonvolatile. Table 17. YINCL_OFF Bit Designations

1 Scale is the weight of each LSB. Table 18. YINCL_SCALE Bit Designations managed by the ALM_MAG1 and ALM_SMPL1 control registers. following text references the Alarm 1 functionality only. accomplished using this register. alarm condition (see the STATUS Register Definition section). has precedence over GPIO_CTRL. ALM_MAG1 control register is located within the lower 14 bits. of the output data variable against a predefined slope.

output variable remains within a predefined window. one of the seven data output registers. not latched but tracks the actual alarm conditions in real time. 1 Default is valid only until the first register write cycle. Alarm 1. The contents of this register are nonvolatile. Table 19. ALM_MAG1 Bit Designations 15 Greater than active alarm bit. Magnitude 1 register setting. Magnitude 1 register setting. the value being monitored by this function. 1 Default is valid only until the first register write cycle. Table 20. ALM_SMPL1 Bit Designations 1 Default is valid only until the first register write cycle. Alarm 2. The contents of this register are nonvolatile. Table 21. ALM_MAG2 Bit Designations 15 Greater than active alarm bit. Magnitude 2 register setting. Magnitude 2 register setting. the value being monitored by this function. 1 Default is valid only until the first register write cycle. Table 22. ALM_SMPL2 Bit Designations

1 Default is valid only until the first register write cycle. The ALM_CTRL register contains the alarm control variables. Table 23. ALM_CTRL Bit Designations 15 Rate of change (ROC) enable for Alarm 2. 14:12 Alarm 2 source selection. 001 Alarm source: power supply output. 010 Alarm source: X-acceleration output. 011 Alarm source: Y-acceleration output. 100 Alarm source: auxiliary ADC output. 101 Alarm source: temperature sensor output. 110 Alarm source: X-inclination output. 111 Alarm source: Y-inclination output. 11 Rate of change (ROC) enable for Alarm 1. 10:8 Alarm 1 source selection. 001 Alarm source: power supply output. 010 Alarm source: X-acceleration output. 011 Alarm source: Y-acceleration output. 100 Alarm source: auxiliary ADC output. 101 Alarm source: temperature sensor output. 110 Alarm source: X-inclination output. 111 Alarm source: Y-inclination output. logarithmic frequency scale. at the same rate whether they are monitored via the SPI or not. Figure 33. SMPL_PRD Values vs. Sample Frequency

1 Default is valid only until the first register write cycle. up, allowing for a sample period of ~744 μs. Table 24. SMPL_PRD Bit Descriptions 6:0 ADC sample period control (N S). various numbers of taps, are detailed in Figure 34. Figure 34. Number of Taps vs. Sample Frequency Response 1 Default is valid only until the first register write cycle. Table 25. AVG_CNT Bit Description

control register, which is reset to 0 prior to power-down. 1 Default is valid only until the first register write cycle. recovery from the power-down mode. Table 26. PWR_MDE Bit Descriptions indicating which alarm condition exists. 1 Default is valid only until the first register write cycle. the error or alarm conditions persist. Table 27. STATUS Bit Descriptions 3 SPI communications failure. 2 Control register update failed. 1 Power supply above 3.625 V. 0 Power supply below 2.975 V. be implemented by writing 1 to its corresponding bit location. volatile. Table 28 describes each of these global commands. 1 Default is valid only until the first register write cycle.

Table 28. COMMAND Bit Descriptions is initiated to move the data into the auxiliary DAC itself. within the moving average filters will likewise be reset. command stores all of the nonvolatile registers to flash. proper update of the nonvolatile registers to flash. zero out the inclination and acceleration outputs. proper update of the nonvolatile registers to flash. control these two functions are shown in Table 29. data ready hardware I/O line is reasserted. bit is returned to a low state, normal operation is resumed. 1 Default is valid only until the first register write cycle. controlling of the self-test and data-ready hardware functions. to 0s upon reset. This register has read/write capability. Table 29. MSC_CTRL Bit Descriptions

user for control of auxiliary circuits within the target application. control register, as defined in Table 31. 1 Default is valid only until the first register write cycle. register is volatile and is set to 0s upon reset. Table 31. GPIO_CTRL Bit Descriptions 9 General-Purpose I/O Line 1 polarity. 8 General-Purpose I/O Line 0 polarity. 1 General-Purpose I/O Line 1, data direction control. 0 General-Purpose I/O Line 0, data direction control.

voltage on the VDD pin to reach 3 V as quickly as possible. a linear regulator that can support the recommended ramp profile. between 2.35 V and 2.7 V within 128 ms. current for this ramp rate is 200 mA during the 33 µs ramp time. to the standard is that the peak temperature exposure is 240°C. example pattern of the location of the ADIS16201 on a PCB.

1.178 BSC

0.500 BSC

1.127 BSC

0.670 BSC

7.873 BSC

Figure 37. Example Pad Layout exposing the ADIS16201 to this type of inspection.

1.000 BSC

0.797 BSC

0.373 BSC

Figure 38. 16-Terminal Stacked Land Grid Array [LGA]

Rev. E | Page 31 of 31 NOTES ©2006–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05462-0-3/19(E)