ADIS16130

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Digital Output, High-Precision Angular Rate Sensor ADIS16130 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Low noise density, 0.0125o/sec/√Hz Industry-standard serial peripheral interface (SPI) 24-bit digital resolution ±250o/sec dynamic range Z-axis, yaw rate response

300 Hz bandwidth, adjustable

Embedded temperature sensor output Precision voltage reference output

5 V single-supply operation

−40°C to +85°C

APPLICATIONS

Inertial measurement units (IMU) Platform stabilization Navigation GENERAL DESCRIPTION The ADIS16130 is a low noise, digital output angular rate sensor (gyroscope) that provides an output response over the complete dynamic range of ±250o/sec. Its industry-standard serial interface and register structure provide a simple interface that is supported by most MCU, DSP , and FPGA platforms. By implementing a unique design, the device provides superior stability over variations in temperature, voltage, linear acceleration, vibration, and next-level assembly. In addition, the surface-micro- machining technology used to manufacture the device is the same high volume BiMOS process used by Analog Devices, Inc., for its high reliability automotive sensor products. Features include a temperature output that provides critical information for system-level calibrations, and a digital self-test feature, which exercises the mechanical structure of the sensor and enables system-level diagnostics. The package configuration is a 36 mm × 44 mm × 16 mm module with a standard 24-lead connector interface. FUNCTIONAL BLOCK DIAGRAM TEMPERATURE SENSOR REFERENCE SYNC SYNC 24-BIT Σ-Δ ADC SERIAL INTERFACEMEMS ANGULAR RATE SENSOR 2:1 MUX SELF-TEST CS SCLK SDI SDO RDY ST ROA1 ROA2 VCC GND 07238-001 ADIS16130 Figure 1.

Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

1/08—Revision 0: Initial Version

Rev. 0 | Page 3 of 16 SPECIFICATIONS TA = 25°C, VCC = 5 V , angular rate = 0°/sec, COUT = 0 μF, ±1 g, unless otherwise noted. Table 1. Parameter Conditions Min1 Typ Max Unit SENSITIVITY Clockwise rotation is positive output (See Figure 5) Dynamic Range2 Full-scale range over specified operating conditions ±250 °/sec Initial 22,548 23,488 24,428 LSB/°/sec Nonlinearity Best fit straight line 0.04 % of FS NULL Initial Null ±1σ ±3 °/sec In-Run Bias Stability 1σ 0.0016 °/sec Angle Random Walk 1σ 0.56 °/√hr Turn-On Time Power on to ±0.5°/sec of final value, 80 Hz bandwidth 35 ms Linear Acceleration Effect Any axis 0.05 °/sec/g Voltage Sensitivity VCC = 4.75 V to 5.25 V 0.2 °/sec /V NOISE PERFORMANCE Rate Noise Density3 0.0125 °/sec/√Hz FREQUENCY RESPONSE Bandwidth −3 dB frequency with no external capacitance 300 Hz Sensor Resonant Frequency 14 kHz SELF-TEST INPUTS ST RATEOUT Response4 ST pins from Logic 0 to Logic 1 65 75 85 °/sec Logic 1 Input Voltage Standard high logic level definition 3.3 V Logic 0 Input Voltage Standard low logic level definition 1.7 V Input Impedance To GND 3.13 kΩ TEMPERATURE SENSOR Output at 298 K (25°C) 8,388,608 LSB Scale Factor 14,093 LSB/°C DIGITAL OUTPUTS Output Low Voltage (VOL) 0.4 V Output High Voltage (VOH) 4 V DIGITAL INPUTS Input Current CS 10 μA All others 1 μA Input Capacitance 5 pF VT+ 1.4 2 V VT− 0.8 1.4 V POWER SUPPLY Operating Voltage Range 4.75 5.00 5.25 V Quiescent Supply Current IOUT = 0 mA, 5 V 73 85 mA TEMPERATURE RANGE Operating Range –40 +85 °C 1 All minimum and maximum specifications are guaranteed. Typical specifications are not tested or guaranteed. 2 Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 4.75 V to 5.25 V supplies. 3 Resulting bias stability is <0.01°/sec. 4 Self-test response varies with temperature, see Figure 12.

Rev. 0 | Page 4 of 16 TIMING SPECIFICATIONS All input signals are specified with 10% to 90% rise and fall times of less than 5 ns. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments t1 50 ns SYNC pulse width Read Operation t4 0 ns CS falling edge to SCLK falling edge setup time t51 SCLK falling edge to data valid delay 0 60 ns DVDD of 4.75 V to 5.25 V t5A1, 2 CS falling edge to data valid delay 0 60 ns DVDD of 4.75 V to 5.25 V t6 50 ns SCLK high pulse width t7 50 ns SCLK low pulse width t8 0 ns CS rising edge after SCLK rising edge hold time t93 10 80 ns Bus relinquish time after SCLK rising edge Write Operation t11 0 ns CS falling edge to SCLK falling edge setup t12 30 ns Data valid to SCLK rising edge setup time t13 25 ns Data valid after SCLK rising edge hold time t14 50 ns SCLK high pulse width t15 50 ns SCLK low pulse width t16 0 ns CS rising edge after SCLK rising edge hold time 1 These numbers are measured with the load circuit shown in Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 2 This specification is relevant only if CS goes low while SCLK is low. 3 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. Therefore, the times quoted are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

Table 4. Thermal Characteristics Figure 5. Rotational Measurement Orientation

Figure 6. Pin Configuration, Top View Table 5. Pin Function Descriptions

8 CS Chip Select of the SPI

10 RDY Data Ready

12 SDO Data Output of the SPI

14 SDI Data Input of the SPI

16 SCLK Serial Clock of the SPI

18 SYNC Synchronization Input

23 ROA1 Analog Filter Node 1

24 ROA2 Analog Filter Node 2

configuration registers govern the operation in the ADIS16130. Table 8 for a summary of these registers. next one to three bytes contain the contents of the register selected. for each segment of this configuration sequence. Table 6. Configuration Sequence 1 0x01 COM Start a write sequence for IOP . 6 0x05 RATECONV Initialize the RATE conversion. 10 0x05 TEMPCONV Initialize the TEMP conversion.

1 The SDI column lists the hexadecimal code representation of the SDI bit

Figure 3 provide critical timing details for the output signal. Figure 13. Read Sequence Example Figure 13. The RATE and TEMP channels update this case, the old data remains and the new data is lost. interrupt routine at a reduced sample rate. to Step 10 of the configuration sequence are not required.

the rising edge of the SYNC pin). the pass/fail criteria for system-level diagnostic routines.

300 Hz, which is the combined response of two single-pole

Figure 14. Pin ROA1 and Pin ROA2 provide Cext is as defined in Figure 15 and Table 7. Figure 14. Frequency Response Block Diagram Figure 15. Frequency Response: Cext = 0 μF vs. Cext = 0.15 μF Table 7. Nominal Bandwidth for Standard Capacitor Values

Table 8. Register Descriptions Table 9. COM Register Bit Assignments Table 10. IOP Register Bit Assignments Table 11. RATECS Register Bit Assignments Table 12. TEMPCS Register Bit Assignments Table 13. RATECONV/TEMPCONV Bit Assignments Table 14. MODE Register Bit Assignments

potential noise threats on the power supply lines. mechanical and electrical connections on the same surface. of the mating socket layout, which is illustrated in Figure 17. maintaining reliability and optimal bias stability performance.

5.00 BSC

39.60 BSC

19.800 BSC

31.200 BSC

15.600 BSC

Figure 16. Suggested Hole Pattern for Mounting

0.022 DIA THRU HOLE (TYP)

Figure 17. Mating Socket Recommended Pad Layout, with

1.00 BSC

0.30 BSC SQ

2.200 TYP

2.400 THRU HOLE

5.50 BSC

Figure 18. PCB Module with Connector Interface

Rev. 0 | Page 14 of 16 NOTES

Rev. 0 | Page 15 of 16 NOTES

Rev. 0 | Page 16 of 16 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07238-0-1/08(0)