ADIN6310BBCZ-RL

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Industrial Ethernet Time Sensitive Networking Switch Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Ethernet MAC interfaces: 10 Mb, 100 Mb or 1 Gb per port ►6-port: 4x RMII/RGMII/SGMII and 2x RMII/RGMII ►3-port: 2x RMII/RGMII/SGMII and 1x RMII/RGMII ►SGMII, 1000BASE-SX/1000BASE-LX/1000BASE-KX, and 100BASE-FX ►Low Latency, Layer 2 Ethernet switch ►Deterministic latency from port to port ►Cut-through or store and forward operation ►Traffic types and bridge delay per IEEE/IEC 60802 ►Standard bridging per IEEE 802.1Q-2018 (tailored) ►Each port is nonblocking and independent ►32 kB frame buffer per transmit port ►4096 VLANs ►Time synchronization ►IEEE 802.1AS-2020 ►IEEE 1588-2019 default profile ►IEEE C37.238-2017 energy profile2 ►8 ns timestamp resolution ►Frames timestamped on ingress or egress ►IEEE 802.1Q time sensitive networking bridging ►Qbv: enhancements for scheduled traffic ►Qci: per stream filtering and policing ►Qbu: frame preemption ►Qch: cyclic queuing and forwarding ►Qav: forwarding and queuing enhancement2 ►Qcc: stream reservation protocol enhancements2 ►Number of streams ►16000 TSN Layer 2 streams ►256 extended lookup streams (IPV4, IPV6, PCP, and so on) ►PROFINET SendList control ►High availability and redundancy ►IEEE 802.1CB Frame Replication and Elimination for Reliability ►IEC62439-3:2016-03 HSR-/PRP-Compliant Protocol for Seamless Failover ►IEC62439-3-2021-12 Media Redundancy Protocol ►Custom Layer 2 on two ports for PROFINET IRT, EtherNet/IP beacon-based DLR, POWERLINK (100 Mbps)2 ►Packet assist engine offloads host and manages TSN and switch ►Portable C drivers for TSN and industrial Ethernet protocols ►NETCONF support (driver to Sysrepo translation layer) ►Hardware root of trust based security features ►Secure boot, secure update with anti-rollback ►Hardware-based cryptography ►Secure host pairing Protocol ►Cryptographic authenticity checking ►Interfaces to external host processor ►RMII, RGMII, SGMII, SPI, dual SPI, or Quad SPI ►Power ►3 external power supplies: 1.1 V, 3.3 V, and VDDIO_x (1.8 V, 2.5 V, or 3.3 V) ►Total chip power 60 mW per port at 1 Gbps, full utilization with VDDIO_B = 1.8 V ►Package and temperature range ►256-ball CSP_BGA, 14 mm × 14 mm, 0.8 mm pitch ►196-ball CSP_BGA, 12 mm × 12 mm, 0.8 mm pitch ►Temperature range −40°C to +85 or −40°C to 105°C

APPLICATIONS

►Factory and process automation ►Motion control, robots, and cobots ►Energy automation ►Transportation ►Instrumentation ►Building automation GENERAL DESCRIPTION The ADIN3310 and ADIN6310 are 3-port and 6-port Gigabit Ether- net time sensitive networking (TSN) switches with integrated securi- ty primarily designed for industrial Ethernet applications. Each port can be configured to operate at different speeds. These switches have uncommitted media access controller (MAC) interfaces and can be paired with Analog Devices, Inc., physical (PHY) layer devices such as ADIN1100, ADIN1200, and ADIN1300, to form a low power, low latency system. Four serial gigabit media independ- ent interface (SGMII) and serializer/deserializer (serdes) interfaces allow backplane connections, connectivity to SFP modules and cascade switches. The switch supports the suite of IEEE 802.1Q time sensitive networking bridging features required by IEEE 60802 standard providing quality of service (QoS) for latency sensitive streams. The device also includes hardware capability to support parallel redundancy protocol (PRP) or high availability seamless redundancy (HSR) redundancy protocols, thereby offloading the host processor. 1 Standard not finalized. 2 Future software capability.

Data Sheet ADIN3310/ADIN6310 TABLE OF CONTENTS analog.com Rev. A | 2 of 86 SGMII Serial Interface Transmit and Electromagnetic Compatibility (EMC) Power Consumption and Thermal Per Stream Filtering and Policing (IEEE Cyclic Queuing and Forwarding (IEEE Forwarding and Queuing Enhancements High-Availability Seamless Redundancy Frame Replication and Elimination for

Data Sheet ADIN3310/ADIN6310 TABLE OF CONTENTS analog.com Rev. A | 3 of 86

REVISION HISTORY

1/2025—Rev. 0 to Rev. A

Data Sheet ADIN3310/ADIN6310 TABLE OF CONTENTS analog.com Rev. A | 4 of 86 Changed Per Stream Filtering and Policing (Qci) Section to Per Stream Filtering and Policing (IEEE Changed Cyclic Queuing and Forwarding (Qch) Section to Cyclic Queuing and Forwarding (IEEE Changed Forwarding and Queuing Enhancements (Qav) Section to Forwarding and Queuing Changes to PRP Traffic With the Wrong LSDU Size in the PRP Tag Section and Hybrid HSR and PRP Changed Frame Replication and Elimination for Reliability, 802.1CB Section to Frame Replication and

Data Sheet ADIN3310/ADIN6310 TABLE OF CONTENTS analog.com Rev. A | 5 of 86 10/2024—Revision 0: Initial Version

temperature range, TA = −40°C to +105°C, unless otherwise noted. Table 1. Electrical Characteristics1

Table 1. Electrical Characteristics1 (Continued)

1000 Mbps 500 ns Bridge latency

10 Mbps 22 μs

100 Mbps 6 μs

10 Mbps 58 μs

1000 Mbps

1000 Mbps 112 μs

100 Mbps 118 μs

10 Mbps 170 μs

1.7 V IOH (minimum) = 4 mA

20 Years TJ = 85°C

1 Specifications may be subject to change. 2 When all six ports operate at 1 Gbps, use a VDDIO_B supply voltage of 1.8 V or 2.5 V to minimize power consumption. 3 Enabling SendList on the ADIN3310 adds 15 mA to the VDDCORE current consumption. table provides the routing information, the frame is immediately queued for transmission. Using lower numbers can decrease latency and increase jitter. 6 Latency from the SGMII to SGMII port = SGMII Receive + Bridge Latency + SGMII Transmit. Latency from the SGMII to RGMII port = SGMII Receive + Bridge Latency. Latency from the RGMII to SGMII port = Bridge Latency + SGMII Transmit. 7 Where load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

Table 2. Power-Up Timing1, 2 1 Specifications may be subject to change. VDDIO_A → VDDCORE and this order is reversed when powering down. 3 Applies to all supply rails. 4 Includes bootloader and software configuration time. Figure 3. Power-Up, Power-Down, and Reset Timing

Table 3. Management Interface Timing1, 2 1 Specifications may be subject to change. 2 Measured with a CL of 100 pF (routing to up to six Ethernet PHYs, includes pin capacitance and trace capacitance). Timing parameters measured from 10% to 90%. 3 The typical parameters correspond to the maximum MDC frequency of 2.5 MHz as specified in the IEEE 802.3 standard. Figure 4. Management Interface Timing

Table 4. 1000M RGMII Timing1, 2, 3 1 Specifications may be subject to change. 3 When operating at 1 Gbps, transmit and receive data is clocked on the rising and falling edge of the clocks; therefore, setup and hold times apply for both clock edges. ns and less than 2.0 ns is added to the associated clock signal. For 10 Mbps and 100 Mbps, the maximum value is unspecified. 5 Hardware and software programmable internal delay can be enabled or disabled. 6 For 10 Mbps and 100 Mbps, tCYC scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. Table 5. 10M/100M RGMII Timing1 1 For 10 Mbps and 100 Mbps, tCYC scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. Figure 5. RGMII Transmit Timing

Table 9. Absolute Maximum Ratings 1 All Port 0 pins, including P0_LINK and P0_RSTN. 2 All Port 1 to Port 5 pins including Px_LINK and Px_RSTN. ing conditions for extended periods may affect product reliability. environment. Close attention to PCB thermal design is required. measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 10. Thermal Resistance

202 Not applicable °C/W

1 Based on simulated data using a JEDEC 2s2p thermal test board (with

specification JESD-51 for details.

sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 11. ADIN6310, 256-Ball CSP_BGA Table 12. ADIN3310, 196-Ball CSP_BGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 12. ADIN3310 Pin Configuration (Top View, Looking Through the Device) Table 13. Pin Function Descriptions E4 XTAL_IN/CLK_INA High-Z VDD3P3 Input for Crystal (XTAL_IN). Single-Ended 25 MHz Reference Clock (CLK_IN). clock on XTAL_IN/CLK_IN, leave XTAL_OUT open circuit. define the host interface origin and operation.

Table 13. Pin Function Descriptions (Continued) H13 GPIO0 I/O Power-down VDDIO_A GPIO. G12 GPIO1 I/O Power-down VDDIO_A GPIO. G14 GPIO2 I/O Power-down VDDIO_A GPIO and Activity on Industrial Ethernet Engine Port 1. G13 GPIO3 I/O Power-down VDDIO_A GPIO and Activity on Industrial Ethernet Engine Port 2. B13 MDC O High-Z VDDIO_B Management Data Clock Output up to 5.5 MHz. MDIO pin requires a 1.5 kΩ power-up resistor to VDDIO_B. Serial Interface This interface supports SPI, dual SPI, and quad SPI communication. host interface origin and operation. H14 SPI_SCLK I Power-down VDDIO_A Clock Input. Output 0 for the dual SPI), and the serial data input (SDI) for the SPI. Output 1 for the dual SPI, and the serial data output (SDO) for the SPI. define the host interface origin and operation. J12 SPI_SIO3 I/O Power-down VDDIO_A Serial Input and Output 3 for the Quad SPI. L10 P0_RSTN O Power-down VDDIO_A Port 0 PHY Reset. Active low output. through strapping or software. N13 P0_TXD0 O Power-down VDDIO_A Port 0 RGMII and RMII Transmit Data 0 Output. P13 P0_TXD1 O Power-down VDDIO_A Port 0 RGMII and RMII Transmit Data 1 Output. N12 P0_TXD2 O Power-down VDDIO_A Port 0 RGMII Transmit Data 2 Output. P12 P0_TXD3 O Power-down VDDIO_A Port 0 RGMII Transmit Data 3 Output. combination of the TX_EN and TX_ER signals using both edges of TXC. (TX_EN), which indicates that transmission data is available on the data lines. 125 MHz for 1 Gbps, of 25 MHz for 100 Mbps, and of 2.5 MHz for 10 Mbps. L14 P0_RXD0 I Power-down VDDIO_A Port 0 RGMII and RMII Receive Data 0 Input. K13 P0_RXD1 I Power-down VDDIO_A Port 0 RGMII and RMII Receive Data 1 Input. K14 P0_RXD2 I Power-down VDDIO_A Port 0 RGMII Receive Data 2 Input. asserted high, it indicates that the PHY has detected a receive error. asserted while the receive medium is not idle.

connected to the PHY output link status pin or SFP LOS. K1 P1_SRXP I High-Z VDDCORE SGMII Receive Differential Pair Positive. K2 P1_SRXN I High-Z VDDCORE SGMII Receive Differential Pair Negative. J2 P1_STXP O High-Z VDDCORE SGMII Transmit Differential pair Positive. J1 P1_STXN O High-Z VDDCORE SGMII Transmit Differential pair Negative. M6 P1_RSTN O Power-down VDDIO_B See Port 0. N8 P1_TXC O Power-down VDDIO_B See Port 0. P7 P1_TXD0 O Power-down VDDIO_B See Port 0. N7 P1_TXD1 O Power-down VDDIO_B See Port 0. P6 P1_TXD2 O Power-down VDDIO_B See Port 0. N6 P1_TXD3 O Power-down VDDIO_B See Port 0. P8 P1_TXCTL O Power-down VDDIO_B See Port 0. P9 P1_RXC I Power-down VDDIO_B See Port 0. N10 P1_RXD0 I Power-up VDDIO_B See Port 0. P10 P1_RXD1 I Power-down VDDIO_B See Port 0. P11 P1_RXD2 I Power-down VDDIO_B See Port 0. N11 P1_RXD3 I Power-down VDDIO_B See Port 0. N9 P1_RXCTL I Power-down VDDIO_B See Port 0. M8 P1_LINK I Power-down VDDIO_B See Port 0. G1 P2_SRXP I High-Z VDDCORE See Port 1. G2 P2_SRXN I High-Z VDDCORE See Port 1. F2 P2_STXP O High-Z VDDCORE See Port 1. F1 P2_STXN O High-Z VDDCORE See Port 1. L3 P2_RSTN O Power-down VDDIO_B See Port 0. N2 P2_TXC O Power-down VDDIO_B See Port 0. N1 P2_TXD0 O Power-down VDDIO_B See Port 0. M3 P2_TXD1 O Power-down VDDIO_B See Port 0. M1 P2_TXD2 O Power-down VDDIO_B See Port 0. M2 P2_TXD3 O Power-down VDDIO_B See Port 0. P2 P2_TXCTL O Power-down VDDIO_B See Port 0. P3 P2_RXC I Power-down VDDIO_B See Port 0. N4 P2_RXD0 I Power-down VDDIO_B See Port 0. P4 P2_RXD1 I Power-up VDDIO_B See Port 0. N5 P2_RXD2 I Power-down VDDIO_B See Port 0. P5 P2_RXD3 I Power-down VDDIO_B See Port 0. N3 P2_RXCTL I Power-down VDDIO_B See Port 0. L5 P2_LINK I Power-down VDDIO_B See Port 0. Other Joint Test Action Group (JTAG) Access. A11 TDO O N/A VDDIO_A JTAG Test Data Output. C14 TDI I N/A VDDIO_A JTAG Test Data Input. D13 TCK I N/A VDDIO_A JTAG Test Clock. D12 TMS I N/A VDDIO_A JTAG Test Mode Select. operation, pull TEST_EN low or connect directly to ground if JTAG not used.

VDDIO_A S N/A N/A Supply for Host Port (RGMII and RMII Port 0, SPI, JTAG). VDDIO_B S N/A N/A Supply for RGMII and RMII Port 1 to Port 5, MDIO Interface. decoupling capacitors with respect to VSS3P3. D2, E3, G3, C1VSS3P3 S N/A N/A Ground for the Analog, Crystal, and Clock Circuit. L8 VSSCORE_DLL S N/A N/A Ground for the Analog Core. D3 VSSCORE_PLL S N/A N/A Ground for the Analog Core. VSS_SGMII S N/A N/A Ground for the SGMII on Port 1 to Port 4. DGND S N/A N/A Digital Ground. DNC N/A N/A Do Not Connect. Leave these balls open circuit. 1 A = analog, I = input, O = output, I/O = input and output, and S = supply. 3 There are multiple balls for some of the supply rails. It is critical for proper operation of the device to ensure that each ball is directly connected to the appropriate power rail.

Figure 13. ADIN6310 Pin Configuration (Top View, Looking Through the Device) Table 14. Pin Function Descriptions H4 XTAL_IN/CLK_INA High-Z VDD3P3 Input for Crystal (XTAL_IN). Single-Ended 25 MHz Reference Clock (CLK_IN). clock on XTAL_IN/CLK_IN, leave XTAL_OUT open circuit. is used to define the host interface origin and operation.

Table 14. Pin Function Descriptions (Continued) K16 GPIO0 I/O Pull-down VDDIO_A GPIO. K14 GPIO1 I/O Pull-down VDDIO_A GPIO. K15 GPIO2 I/O Pull-down VDDIO_A GPIO and Activity on Industrial Ethernet Engine Port 1. J16 GPIO3 I/O Pull-down VDDIO_A GPIO and Activity on Industrial Ethernet Engine Port 2. D15 MDC O High-Z VDDIO_B Management Data Clock Output up to 5.5 MHz. MDIO pin requires a 1.5 kΩ pull-up resistor to VDDIO_B. host interface origin and operation. L16 SPI_SCLK I/O Pull-down VDDIO_A Clock Input. and Output 0 for the dual SPI, and the serial data input (SDI) for the SPI. and Output 1 for the dual SPI, and the serial data output (SDO) for the SPI. to define the host interface origin and operation. M14 SPI_SIO3 I/O Pull-down VDDIO_A Serial Input and Output 3 for the Quad SPI. P10 P0_RSTN O Pull-down VDDIO_A Port 0 PHY Reset. Active low output. configured through strapping or software. R14 P0_TXD0 O Pull-down VDDIO_A Port 0 RGMII and RMII Transmit Data 0 Output. T14 P0_TXD1 O Pull-down VDDIO_A Port 0 RGMII and RMII Transmit Data 1 Output. R13 P0_TXD2 O Pull-down VDDIO_A Port 0 RGMII Transmit Data 2 Output. T13 P0_TXD3 O Pull-down VDDIO_A Port 0 RGMII Transmit Data 3 Output. combination of the TX_EN and TX_ER signals using both edges of TXC. MHz for 1 Gbps, of 25 MHz for 100 Mbps, and of 2.5 MHz for 10 Mbps. P15 P0_RXD0 I Pull-down VDDIO_A Port 0 RGMII and RMII Receive Data 0 Input. P16 P0_RXD1 I Pull-down VDDIO_A Port 0 RGMII and RMII Receive Data 1 Input. N15 P0_RXD2 I Pull-down VDDIO_A Port 0 RGMII Receive Data 2 Input. asserted high, it indicates that the PHY has detected a receive error.

and is asserted while the receive medium is not idle. connected to the PHY output link status pin or SFP LOS. P1 P1_SRXP I High-Z VDDCORE SGMII Receive Differential Pair Positive. P2 P1_SRXN I High-Z VDDCORE SGMII Receive Differential Pair Negative. N2 P1_STXP O High-Z VDDCORE SGMII Transmit Differential Pair Positive. N1 P1_STXN O High-Z VDDCORE SGMII Transmit Differential Pair Negative. P8 P1_RSTN O Pull-down VDDIO_B See Port 0. T9 P1_TXC O Pull-down VDDIO_B See Port 0. R8 P1_TXD0 O Pull-down VDDIO_B See Port 0. T8 P1_TXD1 O Pull-down VDDIO_B See Port 0. R7 P1_TXD2 O Pull-down VDDIO_B See Port 0. T7 P1_TXD3 O Pull-down VDDIO_B See Port 0. R9 P1_TXCTL O Pull-down VDDIO_B See Port 0. R10 P1_RXC I Pull-down VDDIO_B See Port 0. T11 P1_RXD0 I Pull-up VDDIO_B See Port 0. R11 P1_RXD1 I Pull-down VDDIO_B See Port 0. T12 P1_RXD2 I Pull-down VDDIO_B See Port 0. R12 P1_RXD3 I Pull-down VDDIO_B See Port 0. T10 P1_RXCTL I Pull-down VDDIO_B See Port 0. P9 P1_LINK I Pull-down VDDIO_B See Port 0. L1 P2_SRXP I High-Z VDDCORE See Port 1. L2 P2_SRXN I High-Z VDDCORE See Port 1. K2 P2_STXP O High-Z VDDCORE See Port 1. K1 P2_STXN O High-Z VDDCORE See Port 1. P4 P2_RSTN O Pull-down VDDIO_B See Port 0. T3 P2_TXC O Pull-down VDDIO_B See Port 0. R4 P2_TXD0 O Pull-down VDDIO_B See Port 0. T2 P2_TXD1 O Pull-down VDDIO_B See Port 0. R3 P2_TXD2 O Pull-down VDDIO_B See Port 0. R2 P2_TXD3 O Pull-down VDDIO_B See Port 0. P5 P2_TXCTL O Pull-down VDDIO_B See Port 0. R5 P2_RXC I Pull-down VDDIO_B See Port 0. T5 P2_RXD0 I Pull-down VDDIO_B See Port 0. P6 P2_RXD1 I Pull-up VDDIO_B See Port 0. T6 P2_RXD2 I Pull-down VDDIO_B See Port 0. R6 P2_RXD3 I Pull-down VDDIO_B See Port 0. T4 P2_RXCTL I Pull-down VDDIO_B See Port 0. P7 P2_LINK I Pull-down VDDIO_B See Port 0.

H1 P3_SRXP I High-Z VDDCORE See Port 1. H2 P3_SRXN I High-Z VDDCORE See Port 1. G2 P3_STXP O High-Z VDDCORE See Port 1. G1 P3_STXN O High-Z VDDCORE See Port 1. C6 P3_RSTN O Pull-down VDDIO_B See Port 0. B5 P3_TXC O Pull-down VDDIO_B See Port 0. A4 P3_TXD0 O Pull-down VDDIO_B See Port 0. C5 P3_TXD1 O Pull-down VDDIO_B See Port 0. A5 P3_TXD2 O Pull-down VDDIO_B See Port 0. B6 P3_TXD3 O Pull-down VDDIO_B See Port 0. A3 P3_TXCTL O Pull-down VDDIO_B See Port 0. A2 P3_RXC I Pull-down VDDIO_B See Port 0. B3 P3_RXD0 I Pull-down VDDIO_B See Port 0. B2 P3_RXD1 I Pull-down VDDIO_B See Port 0. B1 P3_RXD2 I Pull-up VDDIO_B See Port 0. C2 P3_RXD3 I Pull-down VDDIO_B See Port 0. B4 P3_RXCTL I Pull-down VDDIO_B See Port 0. C3 P3_LINK I Pull-down VDDIO_B See Port 0. E1 P4_SRXP I High-Z VDDCORE See Port 1. E2 P4_SRXN I High-Z VDDCORE See Port 1. D2 P4_STXP O High-Z VDDCORE See Port 1. D1 P4_STXN O High-Z VDDCORE See Port 1. C9 P4_RSTN O Pull-down VDDIO_B See Port 0. B9 P4_TXC O Pull-down VDDIO_B See Port 0. A10 P4_TXD0 O Pull-down VDDIO_B See Port 0. B10 P4_TXD1 O Pull-down VDDIO_B See Port 0. A11 P4_TXD2 O Pull-down VDDIO_B See Port 0. B11 P4_TXD3 O Pull-down VDDIO_B See Port 0. A9 P4_TXCTL O Pull-down VDDIO_B See Port 0. A8 P4_RXC I Pull-down VDDIO_B See Port 0. C8 P4_RXD0 I Pull-down VDDIO_B See Port 0. A7 P4_RXD1 I Pull-down VDDIO_B See Port 0. B7 P4_RXD2 I Pull-down VDDIO_B See Port 0. A6 P4_RXD3 I Pull-up VDDIO_B See Port 0. B8 P4_RXCTL I Pull-down VDDIO_B See Port 0. C7 P4_LINK I Pull-down VDDIO_B See Port 0. C13 P5_RSTN O Pull-down VDDIO_B See Port 0. B14 P5_TXC O Pull-down VDDIO_B See Port 0. B15 P5_TXD0 O Pull-down VDDIO_B See Port 0. B16 P5_TXD1 O Pull-down VDDIO_B See Port 0. C16 P5_TXD2 O Pull-down VDDIO_B See Port 0. C15 P5_TXD3 O Pull-down VDDIO_B See Port 0. A15 P5_TXCTL O Pull-down VDDIO_B See Port 0. A14 P5_RXC I Pull-down VDDIO_B See Port 0.

C12 P5_RXD0 I Pull-up VDDIO_B See Port 0. A13 P5_RXD1 I Pull-down VDDIO_B See Port 0. B12 P5_RXD2 I Pull-down VDDIO_B See Port 0. A12 P5_RXD3 I Pull-up VDDIO_B See Port 0. B13 P5_RXCTL I Pull-down VDDIO_B See Port 0. C11 P5_LINK I Pull-down VDDIO_B See Port 0. Other Joint Test Action Group (JTAG) Access. D16 TDO O N/A VDDIO_A JTAG Test Data Output. F15 TCK I N/A VDDIO_A JTAG Test Clock. F16 TMS I N/A VDDIO_A JTAG Test Mode Select. capacitors with respect to DGND. VDDIO_A S N/A N/A Supply for the Host Port (RGMII and RMII Port 0, SPI, JTAG). VDDIO_B S N/A N/A Supply for the RGMII and RMII Port 1 to Port 5, MDIO Interface. decoupling capacitors with respect to VSS3P3. F2, H3, J3, K3 VSS3P3 S N/A N/A Ground for the Analog, Crystal, and Clock Circuit. M10, E10 VSSCORE_DLL S N/A N/A Ground for the Analog Core. G3 VSSCORE_PLL S N/A N/A Ground for the Analog Core. VSS_SGMII S N/A N/A Ground for the SGMII on Port 1 to Port 4. DGND S N/A N/A Digital Ground.

DNC N/A N/A Do Not Connect. Leave these balls open circuit. 1 A = analog, I = input, O = output, I/O = input and output, and S = supply. 3 There are multiple balls for some of the supply rails. It is critical for proper operation of the device to ensure that each ball is directly connected to the appropriate power rail.

Data Sheet ADIN3310/ADIN6310 THEORY OF OPERATION analog.com Rev. A | 34 of 86 errors specific to preemption. The MAC front ends format the data to be driven onto the wire, maintain various statistics, such as transmit and receive port statistics, and generates mCRC and CRC for transmitted packets. Port statistics can be read on a per port basis using the SES_GetStatistics() API or cleared us- ing the SES_ClearStatistics API (both included in SES_switch.h file, which is available as part of the software drivers from the ADIN6310 product page). When transmitting, the switch ensures a minimum IFG of 11 byte- times. STORM PROTECTION The switch has the capability to protect the port against broadcast storms. This capability is provided as part of the per stream filtering and policing (Qci) feature (see the Per Stream Filtering and Policing (IEEE 802.1Qci) section). SWITCH FABRIC The switch fabric is a high-performance engine that manages and moves data between ports and packet buffers. The switch fabric supports two modes of operation, store and forward and cut-through, with the latter providing the lowest latency. The switch has a packet storage capacity of 32 kBytes per port, which cannot be shared across ports. Cut-Through Operation Cut-through operation means that a frame has not been completely received before it starts to egress. In this case, not all information about the frame is known before transmission begins, such as length or if there are errors. Queuing of the frame for transmission may take place after the necessary forwarding data of the received frame has been received and processed through the forwarding database. Once transmission of a cut-through frame has begun, it always finishes. Frames received with errors can only be discarded if they are store and forward. For a frame that has been cut-through with errors detected, the switch corrupts the CRC on egress. Cut-through operation is the default mode of the device. Cut- through operation can be configured per egress port, per queue, see the SES_SetStoreAndForwardMask () API and SES_Get- StoreAndForwardMask API included in the SES_switch.h file, which is available as part of the software drivers from the ADIN6310 product page. It is possible to add a static table entry that defines whether a particular frame should egress in cut-through or store and forward mode. Cut-through operation is only possible if the egress port is not currently transmitting, and the speed of the egress port must be equal to or less than the speed of the ingress port; otherwise, the frame is forwarded in store and forward mode. Only express frames can be designated for cut-through operation. Note that preemptable frames are always store and forward. A per-traffic class queue, QueueMaxSDU, setting defines the maxi- mum data unit size for each queue, with the frames that exceeds the programmed value being discarded. These QueueMaxSDU settings do not apply to cut-through frames because the switch has already started forwarding before it knows the size of the frame. Store and Forward The switch acts as store and forward when it is not possible to cut-through a frame. The user can configure the device to operate in store and forward mode using the SES_SetStoreAndForward- Mask () API and SES_GetStoreAndForwardMask API included in SES_switch.h file, which is available as part of the software drivers from the ADIN6310 product page. In this mode, the entire frame is stored in memory to be sent at a later time to its destination. The entire frame can be checked; therefore, errored frames are identified and discarded. QueueMaxSDU settings apply to store and forward frames, and frames in excess of the programmed setting are dropped. QueueMaxSDU settings are programmable on a per port and per queue basis. LOOKUP TABLES Dynamic and Static Forwarding Table The forwarding table stores MAC addresses and associated infor- mation for dynamic and static entries. The table size is 2048 entries, the current use of the dynamic table can be read using the SES_GetDynTblEntryUsage() API (see SES_switch.h file, which is available as part of the software drivers from the ADIN6310 product page). Dynamic entries get created automatically in the hardware in response to port learning from incoming frames, while static entries are typically created by management software. Each received frame generates a lookup request to the forwarding ta- ble. If an entry already exists (returns a hit), the table returns information about where to send that frame and any transforms or filters to apply. If no entry exists (for example, it returns a miss), the frame is forwarded with the default behavior. Users can configure the default miss behavior via the SES_SetUnicastMiss- Return() API and SES_SetMulticastMissReturn() API included in SES_switch.h file. For VLAN tagged traffic, the ports must be configured to forward the VLAN IDs of interest for traffic to egress. Learning The learning process is a function executed for all frames received on a port unless learning is disabled. Learning is an automated mechanism for populating the dynamic forwarding table. The ta- ble is updated with a new dynamic entry if an entry does not already exist, if the received packet has no errors, if the received packet has a unicast source address, and if the packet size is valid. Assuming the frame is valid, a new entry is created in the forwarding table with the MAC address, VLAN ID, ingress port, and the age is initialized. As further frames are received and lookups performed, if an entry is matched, the age field on the entry is reset. The SES_GetLearnMode() API (see SES_switch.h file, which is

can also interrogate and read back the entries in the dynamic table. entry from the forwarding table. SES_RmStaticTableEntry() API can be used to remove an entry. drivers from the ADIN6310 product page. Each dynamic table entry has an age value associated with it. the corresponding source address and VLAN combination appears. of programmability extends from 2 seconds to 4 hours. of the software drivers from the ADIN6310 product page. different types of traffic to perform filtering and transformations. Figure 25. Destination Address to Stream Index

Data Sheet ADIN3310/ADIN6310 THEORY OF OPERATION analog.com Rev. A | 37 of 86 Standard Lookup The standard lookup is the default type of lookup. A standard desti- nation address and VLAN lookup is performed on each ingressing frame. The frame information is searched against all entries in the static and dynamic table, returning the mapping and transform fields associated with a hit, or otherwise, it returns a miss. The return information provided by a hit can prompt further lookups, as required, how to handle the traffic, what types of receive filtering must be applied (such as a stream gate or flow meter), and what types of transforms must be applied to the frame, such as the following: ►Inserting or removing PRP, IEEE 802.1CB, or HSR tags ►Timestamp-related changes (correction fields, source addresses, and source port identity) ►Destination address changes ►Inserting, removing, or modifying VLAN tags A miss indicates there was no entry in the table, and the default processing is applied. The default behavior is configurable for unicast and multicast and broadcast frames. Once the destination and VLAN lookup is complete, if additional lookups are required, these lookups can be performed in parallel. Source Lookup If the destination address and VLAN ID lookup prompts a source lookup, this is a lookup of the source address and VLAN ID. The return information from the lookup directs how to route the frame and any filtering or transforms to apply. A source lookup can be prompted based on how a static entry was installed. Alternatively, a port can be configured to perform source lookups on all traffic. Extended Table Lookup When enabled, the extended table lookup mode is performed in addition to the standard lookup or the source stream lookup. The additional analysis performed by the extended lookup results in lon- ger processing of the frame. This mode identifies the EtherType in the frame, which is then looked up in an EtherType transform table. The EtherType transform table is a 16 entry table that indicates the search pattern for each supported EtherType. The return values are eight pairs of offset and count. The offset value indicates the data bytes past the EtherType to start populating the extended search with, while the count indicates the number of bytes starting from this offset to populate the extended search with. The data extracted from the packet represents the total data pattern to be matched for that EtherType. An extended lookup can be prompted based on how a static entry was installed. Alternatively, a port can be configured to perform extended lookups on all traffic. Stream ID Lookup The Stream ID lookup mode can be performed in addition to the standard lookup or the source stream lookup. Stream configuration APIs are part of SES_stream.h file, which is available as part of the software drivers from the ADIN6310 product page. VLAN Table and Management A VLAN is used to partition the network into multiple virtual net- works where traffic is directed to specific subsets of the larger network. The VLAN protocol uses a 4 byte tag included in the header of the Ethernet frame. The switch supports a VLAN table with 4096 entries, each entry in the table sets the state per port in that VLAN, such as disabled, learning, or forwarding. The VLAN management block controls the functions applied at the receive port, remapping VLAN IDs or priorities on ingress, replacing VLAN IDs, adding VLAN tags if there is not any assigned and restricting traffic ingressing a port to particular sets of VLANs. The default VLAN behavior is no learn and no forward on all VLAN IDs, with the exception of untagged and priority (VID 0) for all ports. Therefore, the user must configure the VLAN table directly or configure the ports as trunk or access type during the initial configuration of the device. Trunk ports can support multiple VLAN IDs or ranges of VLAN IDs, whereas access ports support only one VLAN ID. When using a VLAN trunk or access port configuration, the switch handles the insertion and removal of VLAN tags, where required, when traffic is crossing between ports. The VLAN configuration APIs are part of SES_vlan.h header file, which is available as part of the software drivers from the ADIN6310 product page. The switch does not support double tagging. While the VLAN table supports 4096 entries, in practice, systems only use a small number of VLANs. When configuring the switch VLAN table, a maximum of 64 active VLANs is supported. BUFFER MANAGEMENT Each transmit port has a dedicated frame buffer of 32 Kbytes. In the event this buffer fills, then the oldest, lowest priority traffic gets discarded. Each traffic class queue can hold 32 entries. In the event a queue is full, the oldest entry in that queue gets removed (irrespective of traffic class). Incoming frames are stored in buffer memory as the packet is ingressed. If the egress port is available to transmit, the frame can cut-through once sufficient information is available to make a forwarding decision. If the port is busy, or the return information indicates that the frame must be treated as store and forward, the full frame is buffered and added to the egress ports transmit queue. Buffers are dedicated to each port and cannot be shared across ports. Extended port statistics provide status information on the current buffer utilization and the highest buffer used. The user can set the buffer usage notification limit and subscribe to an event to be

Data Sheet ADIN3310/ADIN6310 THEORY OF OPERATION analog.com Rev. A | 38 of 86 notified that the current transmit buffer usage is at or above the specified limit. QUALITY OF SERVICE (QOS) The switch QoS provides eight internal queues per port that support eight traffic priorities. Incoming frames are assigned to egress transmit queues depending on the priority in the VLAN tag or, if they are untagged, they are assigned to Queue 0. By default, traffic with VLAN priority of 0 goes into the lowest priority queue of 0, Priority 1 goes into Queue 1 and so on. Traffic with a VLAN priority of 7 is routed to the highest priority queue of 7. Some applications use different mapping of VLAN priority to queues, and the switch supports ability to modify the priority to queue mapping. The switch uses strict priority to schedule each transmit queue; therefore, the egress port transmits frames from each queue with the higher priority queues transmitting before lower priority queues. CONGESTION CONTROL Network congestion can be experienced when too many data packets are sent through the network at one time, exceeding the available capacity of one or more Ethernet links. This congestion can result in increased latency due to delayed communication, packet loss because packets may be dropped if not processed in time, and overall reduced network performance because the overall rate of successful data transfer is reduced. Developing a network that minimizes or avoids congestion prob- lems requires careful planning, design, and ongoing management. Although it is impossible to completely eliminate congestion under all conditions (especially in high demand environments), there are several strategies to build a network that effectively handles high traffic loads, ensures optimal performance, and minimizes conges- tion. To manage congestion, techniques like traffic shaping, load balancing, and QoS are used to prioritize certain types of traffic and ensure efficient data flow. For critical real-time communication streams like those commonly used in industrial automation and similar applications, the time critical traffic is carefully planned and allocated high priority classes. For tighter timing and guaranteed bandwidth, traffic scheduling, preemption, and similar techniques can be used. Other traffic classes that do not have strict determinism and delivery require- ments are allocated to lower priority classes where techniques like credit-based shaper can be used to provide some fairness among classes. The only way to guarantee that one or more links in the network are not overutilized, resulting in dropped frames, is to restrict the worst-case traffic flow across the network at the producers of traffic. As mentioned, for critical streams, this can be carefully engineered. For non deterministic traffic, methods of bandwidth allocation at the originator of the traffic can be applied (for example, a device can be allowed some maximum bandwidth per class on its transmit interface), this allocation is managed to ensure that the combined bandwidth of all producers can be handled by the network. Some other techniques are available at higher level in the open system interconnect (OSI) model. For example, if the majority of in- termittent or non deterministic traffic is transmission control protocol (TCP)-based, then the TCP window sizes of the streams can be adjusted at the producers to ensure that the frames in flight does not overwhelm the buffering capabilities of the switches between producers and consumers. Similar techniques are available for most bulk transfer protocols operating over user datagram protocol (UDP) as well. For systems that do not have strict determinism and latency re- quirements, congestion management features such as IEEE 802.3x Ethernet flow control are used (not supported in the ADIN3310/ ADIN6310). This mechanism is most effective if all switches in the network, as well as all of the producer nodes that originate high volume traffic, implement the protocol. This approach operates by having the switches monitor their internal buffering resources, when buffer space is reaching a critical level, pause frames are sent to connected devices, which cause incoming traffic flows to be halted for a short period, allowing the switch buffering issues to resolve as frames are transmitted downstream. The typical result is for these pause frames to propagate through the upstream portions of the network until the producers detect them and halt production for a period. This mechanism is commonly used in applications that are reliant on bulk transfers of data but that do not require highly de- terministic operation because this approach causes failure in high performance systems with determinism and latency requirements. PORT FORWARDING MASK The switch supports a per port forwarding port mask, which can be used to further segregate how traffic can be forwarded between ports. The host controller configures the port forwarding mask required per port as part of the device initialization routine. The API to configure this feature is SES_ApplyForwardMask(), which is part of SES_logical_mac.h header file, which is available as part of the software drivers from the ADIN6310 product page. ETHERNET FRAME The Ethernet frame is shown in Figure 27. It consists of a preamble which is a series of 8 bytes of 0x55 followed by the SFD or SMD. The receive front end can handle preambles with fewer bytes down to a minimum of one 0x55 followed by the SMD or SFD. If the frame preemption feature is used, the SMD indicates what type of frame follows, either an express frame, the initial portion of a preemptable packet or a continuation frame of a fragmented preemptable packet. The types of SMDs expected are as follows: ►SMD-E, the express frame delimiter = 0x5D (standard SFD) ►SMD-V, the verify packet = 0x07 ►SMD-R, the respond packet = 0x19 ►SMD-S0 through SMD-S3, the preemptable packet start ►SMD-C0 through SMD-C3, the continuation fragment

destination address to identify the TSN stream in the lookup tables. the receiving port statistics as a large frame error. Figure 27. Ethernet Frame

and calculations for common use cases and lookups. Table 15. Switch Latency vs. Lookup1, 2 1 Measured from ingress SFD to egress SFD or egress host interrupt (for the host port). No interfering traffic, same frequency on ingress and egress. 2 Symbol_Time = 800 ns, 80 ns, 8 ns for 10 Mb, 100 Mb, and 1000 Mb, respectively. 3 How many bytes into the frame the extended lookup analyzes. 4 Frame size is in bytes to transmit. 5 Communication from ports to the SPI host is always store and forward, which is a function of firmware.

readback by the host. The receive statistics are detailed in Table 16. Table 16. Per Port Receive Statistics Unicast Packets Received Number of unicast addresses received on a port, and counter is incremented for errored packets. Broadcast Packets Received Number of broadcast packets received on a port, and counter is incremented for errored packets. Multicast Packets Received Number of multicast packets received on a port, and counter is incremented for errored packets. Frames Received with Alignment Errors Number of packets with alignment errors. Frames Received with CRC and FSC Errors Number of packets with CRC, mCRC, or FSC errors. Frames Received with Large Frame Errors Number of packets received on a port greater than the configured maximum length in bytes. Frames with Receive MAC Errors Number of frames with receive MAC errors. The transmit statistics are detailed in Table 17. Table 17. Per Port Transmit Statistics Bytes Transmitted Number of bytes transmitted. Unicast Packets Transmitted Number of unicast packets transmitted. Broadcast packets Transmitted Number of broadcast packets transmitted. Multicast Packets Transmitted Number of multicast packets transmitted. Frames Transmitted After Single Collision Number of frames that experienced a single collision. Frames Transmitted After Multiple Collision Number of frames that experienced multiple collisions. Frames Dropped After Excessive Collisions Number of frames dropped because of multiple collisions. Frames with a Collision After 512 Bits Number of frames that experienced a late collision. Frames Delayed by Traffic Number of frames delayed by traffic. Carrier busy at first attempt. Frames with Transmit MAC Errors Number of frames with a transmit MAC errors.

The driver library and firmware are paired and must always match. al information and descriptions of the APIs. information base (MIB) databases. processor and loading YANG modules to the switch. between the Sysrepo datastore and the software driver. Figure 29. NETCONF to Switch Overview

communication in dual or quad SPI. be written to or read from the device. reads and is clocked out on the falling edge of SPI_SCLK. pins to read and write data. Data lines are only driven in response to a read command. Table 18. SPI Pin Operation on the ADIN6310 product page. SPI_SIOx pins are driven low during this two clock turnaround time. transmitted first. Similarly, reads use a two clock period turnaround.

Figure 30. Quad SPI Data Read

does not act as interrupt pin and is available as a timer pin. MDIO pin requires an external 1.5 kΩ resistor pulled to VDDIO_B. is commanded to one of the PHY layers. ►Preamble: establishes synchronization at beginning of the frame. ►Start of frame: 01 indicates the start of the frame. 10 for read, and 01 for write. matching PHY address responds. ►REG ADDR: register address, MSB first. time spacing between the register address field and data field. ►DATA: 16-bit field, MSB first. Table 19. Frame Format

10 Mbps and 100 Mbps speeds and full duplex for the 1000

(EEE); therefore, EEE must not be enabled on the PHY layer side. does not control this pin on the host port. the PHY, and each port has a unique PHY address. Table 20. PHY Addressing (RGMII) Table 20. PHY Addressing (RGMII) (Continued) having two PHY layers in the system with Address 0. will interface directly to the switch MAC, with no PHY in the paths. same port address, see Table 21. PHYs get the correct address strapping. Table 21. PHY Addressing (RMII)

50 MHz reference clock that can be provided by the switch (on the

of supporting 10 Mbps and 100 Mbps data rates. data is available on the transmit data pins. Figure 31. RMII Switch PHY Interface Signals (ADIN1200 PHY) Figure 32. RMII Switch PHY Interface Signals (ADIN1100 PHY) thereby reducing the number of data lines for the interface. 1000 Mbps, 100 Mbps, or 10 Mbps modes, respectively. Figure 33. RGMII Switch PHY Interface Signals

configuration to change the host interface is not supported. four TIMERx pins, three of the SPI_SIOx pins, and the SPI_SS pin. resistors to select a different SPI or an Ethernet host interface. and all other ports from the VDDIO_B rail. Table 22. Boot Strapping Pin Configuration—Host Interface (SPI or Ethernet)

1 P2 through P0 select the port for SGMII, RMII, and RGMII host interface, see Table 23. when no external host strapping is used. To configure a different host interface, use the external pull-up and pull-down resistor values per Table 24. typically at the receiving side. For MAC interfaces that do not have the capability to add delay, the switch host strapping supports adding delays on both sides. for other ports can be configured through the Software Driver API, which is available from the ADIN6310 product page. interface) and one for data traffic. Table 23. Boot Strapping Pin Configuration—Host Port Selection face (high or low). When ds = 1, this corresponds to the highest drive strength. Table 24. External Strapping Resistor Values Table 24. External Strapping Resistor Values (Continued) captures as detailed in Table 25. Table 25. Timer Functions function is configured by the packet assist engine. high and stays high, the external strapping pin states are latched. output pins are driven to a High-Z state.

a mix of PHY technology and speeds. Table 28. Power Consumption Per Port Consumption = Base Power + Each Port Power. Table 29. Recommended Decoupling Table 30. ADIN3310 Layout Prioritization for Bypass Capacitors Table 31. ADIN6310 Layout Prioritization for Bypass Capacitors

Data Sheet ADIN3310/ADIN6310 TIME SYNCHRONIZATION analog.com Rev. A | 56 of 86 PRECISION TIME PROTOCOL (PTP) The purpose of time synchronization is to provide all devices on the network with an accurate and reliable time reference by using various profiles of IEEE 1588. The switch can support running a PTP or generalized PTP (gPTP) stack on the packet assist engine with a choice of three different time synchronization profiles, namely IEEE 802.1AS 2020, IEEE 1588-2019 (default profile), or IEEE C37.238-2017 energy profile. The PTP stack is disabled by default and requires configuration by the host to enable the function. TIME DOMAINS The switch supports multiple time domains that allow a working clock to coordinate precise coordination among the elements of a machine or cell and system-wide clocks that can be used to correlate critical events, such as alarms and errors. Different syn- chronization approaches can be coordinated by the switch, bridging time between, for example, one set of ports operating with IEEE 802.1AS-2020 and another port connected to a network synchron- ized with the IEEE 1588-2019 default profile. IEEE 802.1AS 2020 The switch supports running the IEEE 802.1AS 2020 stack on the packet assist engine with two step sync messaging (one step sync will be made available in a future software release). The PTP stack supports running IEEE 802.1AS 2020's best timeTransmitter clock algorithm (BTCA) to determine the highest quality clock in the network. Alternatively, the external port configuration allows ports to have their roles configured manually. The switch supports the IEEE 802.1AS 2020 grandmaster or time- Transmitter capability on all PTP ports and supports PTP end instance and PTP relay instance. Configuration is done using the ieee802-dot1as-ptp.yang module, which includes the following: ►Support for all ports as PTP ports for relay instances ►Peer to peer and common peer delay mechanism for path delay ►External port configuration ►Two step configuration ►One step capability (future software update) ►Application interfaces per Clause 9 IEEE 1588-2019 DEFAULT PROFILE The switch can support running a PTP stack configured for the default profile per IEEE Standard 1588-2019, Annex I. The PTP stack runs on the switch packet assist engine and supports the following: ►I.3 delay request-response default profile ►I.4 peer to peer default profile (will be supported in a future software update) ►Ordinary clocks and boundary clocks (Section 9) ►End to end transparent clocks (Section 10.2) ►Peer to peer transparent clocks (Section 10.3) ►Multiple domains and instances (maximum of 2) ►L2 and L3 transport ►Two step PTP messaging (Section 7.5.2.5) ►One step PTP messaging (Section 7.5.2.5) will be supported in a future software update ►VLAN tagged PTP frames (not supported with VLAN trunk or access port configuration) ►Path trace mechanism, path trace TLV (Section 16.2) ►Data sets (Section 8): defaulltDS, currentDS, parentDS, time- PropertiesDS, pathTraceDS, portDS, descriptionPortDS, exter- nalPortConfigurationPortDS, commonServicesPortDs, cmldsDe- faultDs, cmldsLinkPortDs,cmldsLinkPortStatisticsDs, and cmldsAsymmetryMeasurementModeDs ►Transparent clock data sets (Section 8.3 not supported) ►Backward compatibility with devices supporting Version 1588-2008 ►Different profile on different instances (1588-2019 on one in- stance, and IEEE 802.1AS 2020 profile on another) ►Configuration is done using the ieee1588-ptp-tt.yang module IEEE C37.238.2017 ENERGY PROFILE The IEEE C37.238.2017 energy profile is used for power system applications. The switch supports configuration of the time synchro- nization capability to support this profile.

Data Sheet ADIN3310/ADIN6310 TSN FUNCTIONALITY analog.com Rev. A | 57 of 86 The switch supports IEEE 802.1Q time sensitive networking (TSN) bridging with the following features: ►Scheduled traffic (Qbv) ►Frame preemption (Qbu) ►Per steam filtering and policing (Qci) ►Cyclic queuing and forwarding (Qch) ►Forwarding and queuing enhancements (Qav) SCHEDULED TRAFFIC (IEEE 802.1QBV) Scheduled traffic is a means to provide a time protected channel to ensure priority traffic can egress on time without delays due to other traffic. Scheduled traffic takes advantage of the time capability added to Ethernet from IEEE 802.1AS. By using time synchronization, a time-protected channel can be used to ensure only one type of traffic is on the network at a time thus avoiding interfering traffic. Because Ethernet was originally specified as best-effort, certain traffic could interfere with other traffic even if that traffic was given a higher priority. Therefore, in addition to priority, these traffic classes are scheduled in time to ensure these messages are not interfered with. Packets are placed into queues until the scheduled time arrives, and then the packets in that queue are allowed to pass onto the network until the time window for that queue closes. Because every node on the network has an accurate time base, the schedule windows do not overlap, and therefore, the packets do not interfere with each other. The switch supports eight queues per port with a 256-entry gate control list and seamless switchover when the gate control list is updated. The traffic classes are based on VLAN priority and can be mapped to the eight queues as required. The user can configure the network cycle time individually for each port with control of the cycle time extension and base time. The hardware timer pins (TIMER0 to TIMER3) can also have a network cycle programmed. This feature can be used to provide signals that synchronization application hardware and software with other elements on the network. The configuration of scheduled traffic transmit gates is based on the IEEE 802.1Q scheduled traffic YANG model. The APIs to configure Qbv are part of the SES_scheduled_traffic.h header file, which is available as part of the software drivers from the ADIN6310 product page. Strict Priority Scheduling Each port supports eight queues and operates with strict priority, where the highest priority queued traffic transmits first. Guard Bands When using a schedule to guarantee the transmission time, it is important to guarantee that the transmitter is idle when a higher priority gate is getting ready to open. If the transmitter is not idle, it is possible for a frame of lower priority to potentially block, or at least delay, the start of the transmission of the higher priority traffic. To guarantee that the transmitter is idle and can start immediately sending higher priority traffic when its gate is opened, a guard band is inserted ahead of the gate open time. While active, the guard band inhibits the transmitter from fetching the next frames. To be effective, the guard band must be long enough so that the longest possible message that can be queued transmits completely before the next gate open event occurs. The size of th longest frame that can be queued is defined in the parameter maximum service data unit (maxSDU), in bytes. The switch supports per port and per queue maximum SDU limits and can be set and read using the SES_QbvSetQueueMaxSduTable() API and SES_QbvGetQueue- MaxSduTable() API in SES_scheduled_traffic.h header file, which is available as part of the software drivers from the ADIN6310 product page. The hardware default for per queue maximum SDU frames is 10,000 bytes. The user must configure a more practical SDU size during initial configuration. When guard bands are enabled, the per queue, per port maximum SDU settings are used in conjunction with the established link speed to size the guard band duration. The guard band is applied for both store and forward mode and cut-through forwarding mode to protect the next gate open. Default switching behavior for all queues is to cut traffic through if conditions allow, which is configu- rable through an API call. The QueueMax SDU setting does not apply to cut-through traffic because these frames started forwarding before the hardware knows the size of the frame. However, under- standing the size of the frames and sizing the QueueMax SDU settings accordingly protects the next gate open. When scheduled traffic and frame preemption are used in combina- tion, the device supports hold and release, which allows an explicit guard band to be implemented around a protected transmission window, but one that is smaller in duration than normally needed. This hold and release is used for configurations where the preempt- able traffic gate is scheduled to be open at all times and could have the potential to delay the start of the schedule traffic. Using hold and release allows the express traffic protected window to be completely protected from interference while increasing bandwidth available to the preemptable traffic. FRAME PREEMPTION (IEEE 802.1QBU) Frame preemption can be used to further ensure high priority traffic arrives at a destination with a fixed latency by interrupting transmission of a frame designated preemptable, transmitting the high priority (express) traffic, then resuming transmission of the preempted frame. The receiver node regenerates the preemptable frame from the fragments transmitted between bursts of priority frames. Without frame preemption, the time taken for the highest

μs per hop, or an arrival time jitter reduction of 90%. with SFD or SMD-E, which denotes the beginning of frame data. The frame ends with a 32-bit CRC. continuation fragment to follow. receive side always has preemption enabled. Layer Discovery Protocol (LLDP) frames originating from that port. active at that point in time. enable or activate preemption with the link partner. queues with SMD-S and/or SMD-C. TLV to indicate support only. mal operation and how the switch is intended to be configured. Table 32. Per Port Frame Preemption Statistics (Transmit and Receive)

device can support up to 32 combinations of filters. the frame, perform the required lookups, and handle as required. port timer control unit (TCU). The flow meter allows a certain amount of traffic through the port. The Qch is a popular approach for audio and video applications. Figure 42. Cycling Queuing and Forwarding high priority queues, and the switch has two CBSs per port. transmission and during that the time credit increases.

Figure 43. Credit-Based Shaper

A SendList is a periodic transmission of a number of sublists. relies on dedicating a port in the switch to the SendList function. for this purpose, which does not affect operation on Port 0 to Port 2. ingressing traffic and must be dedicated to the SendList function.

1. Create a SendList with the number of sublists and desired
2. Create sublists with the desired start offset from the start of the
3. Register the SendList frames that will be added to the sublists.
4. Add a static table entry for each registered frame with the
5. Add the registered frames to the appropriate sublists.
6. Configure the schedule for the loopback port.
7. Send registered frame data with the transmit enable parameter

set for each registered frame.

1. Start the SendList with the desired start time.
2. To stop transmitting a specific frame, use the enable or disable

while Sublist 1 to Sublist 3 have just two frame entries. Figure 44. SendList Example with Four Sublists

Figure 47. Simplified HSR Ring, Showing Multicast Frame Path LLDP, leaving a balance for HSR streams and other entries. entries for learning and discarding. this consumes entries available for HSR learning. can participate in the HSR network. The switch supports all the port modes defined in the IEC standard. port are not sent a second time. ports. This mode is used for special network topologies. from all frames that traverse port to port. according to the destination address and/or VLAN. duplicated out the other ring port. correctly from the opposite direction. DANHs/SANs connected to the RedBox at the same interval.

Port B that have HSR tag added. Port B that have HSR tag added. on the link redundancy entity (LRE) Port A or Port B. can accommodate 1024 entries maximum. it does require usage of a duplicate network. duplicate. The DANP can also remove the PRP tag upon egress. Figure 48. Simplified PRP Network them and are assumed to be fail independent. RedBox but switches in the network can be in cut-through mode.

Figure 49. PRP Tag—Trailer at End of Frame can participate in the PRP network. source MAC address for the programmed maximum reside time. connected to the RedBox at the same interval. Port B that have PRP RCT trailers added. Port B that have PRP RCT trailers added. on the LRE Port A or Port B. wrong LAN identifiers received on LRE Port A or Port B. accept based upon received PRP supervision frames for a node. particular node, and it refreshes the node table every 60 seconds. can accommodate 1024 entries maximum. which indicates to the host that the LANs are incorrectly connected.

Table 33. Stream Identification Types The vector algorithm provides a more robust duplicate elimination. which allows early detection of errors. The switch does not support interconnected rings. devices in the ring have the same recovery profile. tion to MRC or MRM roles based on outcome of voting process. the MRP_TopologyChange frames out to the ring.

the MRP_LinkChange frames through both its ring ports. or one MRM with multiple MRCs. in the ADIN6310 6-port switch. ►Disabled: all packets received by the port are dropped. the MRP packets, PTP, and LLDP frames. ►Forwarding: all packets received by the port are forwarded. Figure 52. MRP Ring State Closed and Open MRM is blocking, and all other ports are forwarding. receive its own test frames. allowed in the ring. All other nodes must be MRC. on the ring are configured as MRA.

the lower MAC results in that device becoming the MRM. Figure 53. MRP Voting Before and After and propagates the role change via MRP_TestPropagate. only MRM of the ring and starts to manage the ring.

capability on the remaining ports. DLR, and POWERLINK protocols. path between Port 1, the industrial Ethernet engine, and Port 2. and this pair of ports when this block is active. Operating this block with RMII is not supported. Figure 54. Example of a Logical MAC Group with Three Ports MAC address has 6x xx 00 30 88 fb added at end of the frame. it does not overwrite the port ID information. Table 34. Tail Tag Port Identification the frame automatically sends out that port. additional configuration of the port forwarding.

switch supports an LLDP stack running on the packet assist engine. The stack is compatible with the IEEE 802.1AB – 2016 standard. the host processor can run its own LLDP stack. or a neighbor shutting down. inquire about the status of a specific multicast group. to receive traffic for a specific group. ces of the host for multicast traffic. interested in receiving traffic for a specific multicast group. particular multicast traffic. Figure 57. IGMP Snooping having an active multicast router. considers a host to be a member of a particular multicast group. timeout, the switch forwards the multicast packets to all the ports. Port mirroring is not supported. prevent these loops. The original spanning tree protocol was STP. connections, and disable any ports that can lead to a loop.

Data Sheet ADIN3310/ADIN6310 OTHER FUNCTIONALITY analog.com Rev. A | 73 of 86 tive port, and backup port) and port states per Section 13.16 (dis- carding, learning, and forwarding). MSTP has backward compatibili- ty with RSTP and STP; therefore, the switch can be configured to work in RSTP or STP mode as required. With MSTP, the ports of the switches can be configured to prevent a broadcast storm. If the active path fails after the network con- verged —due to a link or switch in the path going down—MSTP activates an alternate path MSTP supports automatic determination of the multiple spanning tree region with each region mapped to a set of VLAN IDs and au- tomatic reconfiguration of the spanning tree topology as a result of bridge failure or a breakdown in the data path. Four MST instances are supported (MSTIO and MSTIs), this includes the common and internal spanning tree (CIST). MSTP uses bridge protocol data units (BPDUs) to exchange span- ning tree information across the network. Each port in MSTP assumes a specific role within an instance, ensuring proper network behavior and redundancy.

Data Sheet ADIN3310/ADIN6310 APPLICATIONS INFORMATION analog.com Rev. A | 75 of 86 Interface Selection The example in in Figure 58 shows the host configured for RGMII on Port 0. See the Host Interface section for details on other options. MDIO Bus The MDIO bus is routed from the switch to all PHYs. This bus resides in the VDDIO_B voltage domain. In the event there is a PHY on Port 0, and VDDIO_A is at a different supply voltage than VDDIO_B, level shifting may be required on the MDIO bus between the voltage domains. PHY Strapping When using the ADIN1300 or ADIN1200 PHYs, the ADIN6310 and ADIN3310 can provide unique PHY addresses for each PHY; therefore, no external PHY address strapping resistors are neces- sary. If using the ADIN1100 PHY, external PHY address strapping resistors must be used. The default MAC interface of the PHY is the RGMII. In this configuration, the PHY is shown strapped for autonegotiation, all speeds and software power down (SWPD) after reset, with the switch communicating over the MDIO bus to bring the PHYs out of SWPD. For other strapping configurations, visit the ADIN1300 data sheet for further details. SFP Usage In the Figure 58 example, one port is shown connected to an SFP module. The SFP module includes the ac coupling capacitors required. The LOS is an open-drain and/or collector output signal indicating that the received optical power is in normal operation when low or less than the worst-case receiver sensitivity when high. The LOS output expects a pull-up voltage between 2 V and the VCCT voltage level; therefore, it can be connected directly to Px_LINK if VDDIO_x is >2 V. If VDDIO_x is operating from an 1.8 V rail, the LOS must be pulled to VCCT, and a level shifter must be used between the LOS and Px_LINK.

10 Mbps communication with the ADIN1100, 10BASE-T1L Ethernet

Figure 60. Application Circuit for a Field Switch with Two Trunk Ports and Four Spurs Using the ADIN1100 10BASE-T1L PHY MAX20029 DC-DC convertor to provide the four required rails. See the UG-2299 user guide for more details.

Figure 61. Field Switch Evaluation Board Overview

each additional switch adds four spur ports to the system. Figure 62. Cascading Multiple Switches to Build a Larger Field Switch

0.9 V rail required by the PHYs. Figure 63. Overview of a 3-Port Switch Configuration with Three ADIN1300 Ethernet PHYs and Power

Data Sheet ADIN3310/ADIN6310 LAYOUT GUIDELINES analog.com Rev. A | 81 of 86 GENERAL LAYOUT GUIDELINES The general layout guidelines include the following: ►Maintain 50 Ω characteristic impedance for all single-ended traces. ►Maintain 100 Ω characteristic impedance for all differential traces. ►Route the differential circuits away from the noisy clock and power circuit ►Provide adjacent solid GND returns for all the planes and sig- nals. ►Provide a high decoupling connection between the digital GND return and chassis GND. ►Avoid discontinuities such as splits, slots, gaps, and cuts in the ground or return on the board. ►Any component GND pin connecting to GND fill or pour must have a via to the GND plane at the pin. ►In the case of signal transition from layer to layer, provide a GND via adjacent to the signal via. ►Locate high-speed connectors son one corner or on one edge of the board. ►Locate clock drivers near the IC if the device is used for high-fre- quency communication or consider providing these clock drivers locally. ►Avoid routing high-frequency signals beneath or near ringing or noisy circuits or components. ►Avoid overlapping power planes. ►Avoid routing power planes on the edge of the board. ►Avoid routing power planes like traces, instead use planes. ►Avoid stubs on all signal traces, ►Avoid vias where possible, routing signals on one layer as straight as possible or with 45° angles where traces bend. COMPONENT PLACEMENT Prioritization of the critical traces, power planes, and components helps simplify the routing exercises. Place and orient the critical high-speed differential, single-ended, and clock traces, power planes, and components first to ensure an effective layout with minimal turns, vias, and crossing traces. For the switch layout, the important components are the crystal, the MAC interface traces, the SGMII traces, and all bypass capacitors local to the device. Prioritize these components and the routing to them. The following sections provide more detail for each of the areas. For stack up, ensure to provide a solid GND return plane to all the traces and power planes adjacent to it. Power Supply Decoupling From a PCB layout point of view, it is preferred to locate decoupling capacitors on the same side of the IC and close to the IC power pins to help minimize the loop area inductance of the capacitor connected to IC power pins. If the capacitors are on the opposite side, it creates a higher connection Inductance. If there is no room on the top layer, keep decoupling capacitors close to or under the IC. Do not put traces on capacitors for GND connection. Ensure that decoupling capacitors via connection to the power planes and GND plane are not far apart. Avoid decoupling capacitors sharing the GND pour connections with other circuitry components. Choose filtering ferrites of smaller size and appropriate impedance to the frequency of interest. See Table 29 and Table 31 for recommended capacitor values and priority locations. Crystal Oscillator The switch requires a 25 MHz clock that can be an external crystal oscillator applied across the XTAL_IN and XTAL_OUT pins or an external clock applied to the XTAL_IN pin. To ensure minimum current consumption and to minimize stray capacitance, make connections between the crystal, capacitors, and ground as close to the device as possible. If possible, place the crystal and capacitors on the same side of PCB as the switch device as follows: ►Provide symmetrical traces. ►Provide the same GND return for the crystal oscillator, its traces, and load capacitors, and ensure that capacitor GND pads are well stitched to all the GND layers, especially adjacent to solid GND returns. MAC Interface Each port can support the RMII or RGMII, and four of the ports (Port 1 to Port 4) can support the SGMII. RMII and RGMII The RMII is an eight signal interface for each port capable of 10 Mbps and 100 Mbps speeds, while the RGMII can support data rates of 10 Mbps, 100 Mbps, and 1000 Mbps speeds requiring 12 pins. Where possible, route these interface pins on the same side as component pins, as follows: ►Keep trace lengths as short as possible. ►Route traces with an impedance of 50 Ω to ground. ►All signals within the transmit group must be length matched (to within 100 mil), similarly for all signals within the receive group. Note that, no matching is required from port to port. ►Avoid vias where possible, routing signals on one layer as straight as possible or with 45° angles where traces bend.

►It is recommended to route traces on the same layer.

10 Mbps, 100 Mbps, and 1 Gbps full duplex communication with

to an SFP transceiver for fiber communication or over a backplane. shield on both sides of the traces or use a ground pour. ►Keep routing lengths short and avoid stubs. tial pairs is not necessary. via adjacent to the signal via. ►Components or vias on the differential pair must be symmetrical. all signal traces. Avoid routing signal traces across plane splits. Figure 64. Things to Avoid when Routing Differential Pairs line must have a 1.5 kΩ pull-up resistor to the VDDIO_x line. Length match the MDIO interface traces to within 100 mils. better for low inductance connections and interplane capacitance. ►Avoid overlapping power planes. ►Avoid routing power planes on the edge of the board. ►Avoid routing power planes like traces, and use planes.

This anomaly list describes the known bugs, anomalies, and workarounds for the switch. outlined within this section. Table 35. Functionality Issues Table 36. Statistic Counters for Per Stream Filtering and Policing Function (Qci) Background Statistic counters gathered for debugging and diagnostic purposes are not presented per the 802.1Qci specification. function or proper flow of the traffic across switch. filters associated with a stream ID, therefore, multiple stream filters could increment the same counters. Stream gate: statistic counters are indexed by their own identifiers (0 to 15) instead of the active stream filter (0 to 31). Flow meter: statistics are indexed by their own identifiers (0 to 7) instead of the active stream filter (0 to 31). Table 37. PRP Function Handling of Traffic in a Misconfigured Network (Wrong LAN Connections) performs a duplicate discard and strips the PRP trailer. host to handle it accordingly. Workaround Error counters are available for the host to manage this situation at the application level. Table 38. PRP Traffic with Wrong LSDU Size in the PRP Tag Gets Dropped Background PRP frames with wrong LSDU size is dropped. out time (that is, lreDupListResideMax). Table 39. FRER Frame Without CB Tag Is Modified by the Transmit Transform Background Frames matching the stream entry with no CB-tag gets corrupted. bytes are removed from the end of the frame.

Table 40. SGMII Alignment Errors Background Alignment error count increments on odd sized frames. count does not increment unless the frame is corrupt. Workaround Alignment errors without corresponding FCS errors can be ignored. Errored frames can be detected by FCS errors alone. Table 41. Extended Table Lookup Cannot Inspect Last 10 Bytes of Frame Background An extended lookup cannot perform a search on the last 10 bytes of the frame at Gigabit speed. previous lookup (destination address and VLAN ID, source address and VLAN ID, or miss). Workaround Ensure extended lookups do not extend into the last 10 bytes of the frame. Increase the frame size to ensure lookup can be performed. Table 42. Transform to Remove VLAN Tag from a 64-Byte Frame Results in Corrupted Frame Background Application of a transform to remove a VLAN tag from a 64-byte frame results in a corrupted frame. <68 bytes results in a runt frame. This behavior is not conformant with the IEEE802.1Q Annex G standard.

Figure 65. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A.

1.00 REF

12.00 REF

Figure 66. 256-Ball Chip Scale Package Ball Grid Array [CSP_BGA]