ADIN2111BCPZ-R7

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 125

Technical content

Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►10BASE-T1L IEEE Standard 802.3cg-2019 compliant ►Supports 1.0 V p-p and 2.4 V p-p transmit levels ►Cable reach ►Up to 1700 meters with 1.0 V p-p transmit level ►Up to 1700 meters with 2.4 V p-p transmit level ►Low power consumption ►Single supply 1.0 V p-p: 90 mW typical ►Dual supply 1.0 V p-p: 77 mW typical ►Integrated switch with SPI ►10 Mbps full duplex ►16 MAC addresses supported for frame forwarding ►Supports OPEN Alliance 10BASE-T1x MACPHY SPI ►MDIO memory map accessible via SPI ►Supports high and low priority queues ►Total buffer memory of 28 kB shared between ports and host ►Autonegotiation capability ►Managed or unmanaged configuration ►Cut through or store and forward operation ►IEEE 1588 time stamp capture on transmit and receive ►Diagnostics ►Frame generator and checker ►Multiple loopback modes ►IEEE test mode support ►Port dedicated statistics counters ►Link and cable diagnostics ►25 MHz crystal or external clock input ►Single or dual supply with 1.8 V or 3.3 V operation ►Integrated power supply monitoring and POR ►Small package: 48-lead, 7 mm × 7 mm LFCSP ►Temperature range ►Industrial: −40°C to +85°C ►Extended: −40°C to +105°C

APPLICATIONS

►Building automation and fire safety ►Factory automation ►Edge sensors and actuators ►Condition monitoring and machine connectivity FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADIN2111 is a low power, low complexity, two-Ethernet ports switch with integrated 10BASE-T1L PHYs and one serial peripheral interface (SPI) port. The device is designed for industrial Ethernet applications using low power constrained nodes and is compliant with the IEEE® 802.3cg-2019™ Ethernet standard for long reach 10 Mbps single pair Ethernet (SPE). The switch (cut through or store and forward) supports various routing configurations between the two Ethernet ports and the SPI host port providing a flexible solution for line, daisy-chain, or ring network topologies. The ADIN2111 supports cable reach of up to 1700 meters with ultra low power consumption of 77 mW. The two PHY cores support the 1.0 V p-p operating mode and the 2.4 V p-p operating mode defined in the IEEE 802.3cg standard, and can operate from a single power supply rail of 1.8 V or 3.3 V. The ADIN2111 can be used in unmanaged configurations where the device automatically forwards the traffic between the two Ethernet ports. The device integrates the switch, two Ethernet physical layer (PHY) cores with a media access control (MAC) interface and all the asso- ciated analog circuitry, and input and output clock buffering. The device also includes internal buffer queues, the SPI and subsystem registers, as well as the control logic to manage the reset and clock control and hardware pin configuration. The ADIN2111 has an integrated voltage supply monitoring circuit and power-on reset (POR) circuitry to improve system level robust- ness. The 4-wire SPI for communication with the host can be configured to OPEN Alliance SPI or generic SPI. Both modes support optional data protection or cyclic redundancy check (CRC). Analog Devices is in the process of updating documentation to provide terminology and language that is culturally appropriate. This is a process with a wide scope and will be phased in as quickly as possible. Thank you for your patience.

analog.com Rev. 0 | 2 of 125 Ethernet Daisy Chain, Line, and Ring

REVISION HISTORY

12/2021—Revision 0: Initial Version

at −40°C to +105°C, unless otherwise noted. Table 1. General Specifications

1 Load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics. 2 RP and CP are the values of the equivalent parallel RC circuit to ac ground (RP||CP), modeling the driving point impedance of the XTAL_I/CLK_IN pin. Table 2. 10BASE-T1L Specifications

Table 3. Power-Up Timing 1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required. Figure 2. Power-Up Timing 1 Guaranteed by design and characterization. Not production tested. 2 All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDDIO) and timed from a voltage level of 1.2 V. 3 Capacitive load on the SDO pin is 10 pF.

Figure 3. Serial Interface Timing Diagram

TA = 25°C, unless otherwise noted.

1 See the Pin Configuration and Function Descriptions section for a full list of SPI

extended periods may affect device reliability. measured in a one cubic foot sealed enclosure. Table 6. Thermal Resistance circuit board for surface-mount packages.

2 Test Condition 1: thermal impedance simulated values are based on a JE-

DEC 2S2P thermal test board with thermal vias. See JEDEC JESD51. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 7. ADIN2111, 48-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 4. Pin Configuration Table 8. Pin Function Descriptions (Pin 22), which provides a 25 MHz clock. XTAL_O open circuit. See the External Clock Input section. management interrupt. This pin requires a 1.5 kΩ pull-up resistor to VDDIO. 42 SDI PD Serial Data Input. Data is clocked in on the SDI pin on each rising edge. 43 SDO/SPI_CFG0 PD Serial Data Output (SDO). Data is clocked out on the SDO pin on each falling edge.

Table 22 for details. The default configuration for this pin is with protection/CRC enabled. This pin is provided with an internal pull-up resistor. 44 SCLK PD Clock Input. Data is clocked into the shift register on each falling edge. 45 CS PD Active Low Chip Select. left floating if a hardware reset is not required. See the Hardware Reset section. 4 P2_TXN N/A Port 2 10BASE-T1L Transmit/Receive Negative Pin. 5 P2_TXP N/A Port 2 10BASE-T1L Transmit/Receive Positive Pin. 27 P1_TXN N/A Port 1 10BASE-T1L Transmit/Receive Negative Pin. 28 P1_TXP N/A Port 1 10BASE-T1L Transmit/Receive Positive Pin. 16 TEST_3 PU Test Pin 3. No function currently assigned. Do not connect. 17 TEST_2 PD Test Pin 2. No function currently assigned. Do not connect. default configuration is P1_LED_0 enabled. See the Status LEDs section. transmit amplitude. See Table 19. This pin is provided with an internal pull-down resistor. 41 TEST_0/P1_SWPD_EN PD Test Pin 0 (TEST_0). No function currently assigned. VDDIO. This pin is provided with an internal pull-down resistor. default configuration is P2_LED_0 enabled. See the Status LEDs section.

is provided with an internal pull-down resistor. source for an external circuit. close as possible to this pin. Do not use this pin as a voltage source for an external circuit. source for an external circuit. close as possible to this pin. Do not use this pin as a voltage source for an external circuit. rail can be supplied by 1.8 V to 3.3 V depending on the transmit level configuration. supported. If AVDD_H is 1.8 V, only the 1.0 V p-p transmit operating mode is supported. Connect 0.1 μF and 0.01 μF capacitors to GND as close as possible to this pin. close as possible to this pin. capacitors to GND as close as possible to the pin. 4 × 4 array of thermal vias beneath the exposed GND pad is also recommended. 2, 3, 8, 11, 25, 26, 31, 34 DNC N/A Do Not Connect. These pins must be left open circuit. 1 Where a pin is shared between a functional signal and a hardware configuration pin signal, the hardware configuration pin signal is listed last. 2 PU is pull-up, and PD is pull-down. The internal pull-up or pull-down resistor is predefined and nonconfigurable. N/A means not applicable.

analog.com Rev. 0 | 12 of 125 OVERVIEW The ADIN2111 is a low power, low complexity Ethernet switch (LES) with a dual port 10BASE-T1L transceiver designed for Ethernet applications. The chip is available on a 7 mm × 7 mm, 48-lead lead frame chip scale package (LFCSP) and includes the following features: ►Two Ethernet PHY cores with common analog circuitry ►10 Mbps full duplex SPI for frame transfer and system register control ►MAC with support for 16 MAC addresses ►Switch with cut through or store and forward operation ►SPI to MDIO bridge to access the PHY registers ►Input and output clock buffering ►On-chip first in, first outs (FIFOs): ►8 kB high priority reception FIFO for the SPI host port ►8 kB low priority reception FIFO for the SPI host port ►8 kB transmission FIFO for the two Ethernet ports ►4 kB transmission FIFO for the SPI host ►Hardware configuration pins ►Configurable hardware interrupt pin ►Four configurable LED pins for activity monitoring Note that two different SPI protocols are supported to communicate with the switch: a generic SPI protocol similar to protocols used in other Analog Devices products, and the OPEN Alliance MACPHY SPI protocol. POWER SUPPLY DOMAINS The ADIN2111 has five power supply domains and requires a minimum of one supply rail. See the following power supplies: ►AVDD_H is the analog power supply input for the analog front end (AFE) circuitry in the ADIN2111. ►AVDD_L is the analog supply voltage for the internal LDO cir- cuits. AVDD_L can be connected to the AVDD_H rail in single- supply mode, or to an alternative lower voltage rail in dual-supply mode for lower power consumption. ►DVDD1_1P1 and DVDD2_1P1 are the 1.1 V digital core power supply inputs for Port 1 and Port 2 PHYs. DVDD_1P1 and DVDD2_1P1 can operate from the internal 1.1 V LDO outputs available on the DLDO1_1P1 and DLDO2_1P1 pins. Alterna- tively, DVDD1_1P1 and DVDD2_1P1 can be driven from an external 1.1 V supply for lower power consumption. Note that DLDO1_1P1 and DLDO2_1P1 must not be connected together. ►VDDIO is the digital power supply input for the ADIN2111 MAC interface, MDIO, and digital inputs/outputs (I/Os). VDDIO can be connected directly to the AVDD_L rail or to an external power rail. The System Level Power Management section describes various application circuits that can be used as reference. Single-Supply Applications In a single-supply application, connect AVDD_H and AVDD_L to VDDIO and connect DVDD1_1P1 to DLDO1_1P1 and DVDD2_1P1 to DLDO2_1P1. The appropriate supply voltage used depends on the end application and cable length. A recommended circuit is shown in the Single-Supply Configuration section. Long Reach and Trunk/Spur Applications The 1.0 V p-p transmit operating mode supports the spur use case and can operate at a lower AVDD_H supply voltage of 1.8 V. This mode supports intrinsic safety applications. The higher transmit operating mode of 2.4 V p-p supports trunk applications and requires a higher AVDD_H supply voltage of 3.3 V. This mode can be used for longer cable lengths in industrial Ethernet environments with higher noise levels. ANALOG FRONT-END The AFE stage consists of a hybrid stage, 9-level DAC, line driver, analog receive filter, input buffer, and ADC. The line driver transmits the signal onto the line via the Port 1 (respectively Port 2) MDI interface pins, P1_TXP and P1_TXN (respectively P2_TXP and P2_TXN). The hybrid stage subtracts the transmitted signal from the received signal on the Port 1 (respec- tively Port 2) MDI pins, thereby allowing full duplex operation on the single-pair cable. The received signal then passes through the analog receive filter and reaches the input buffer before being sent to the ADC. TWO PORT SWITCH The ADIN2111 internal two port switch manages the traffic between the SPI host, Port 1 PHY, and Port 2 PHY. The following modes of operations are available for the switch: ►Store and forward (to or from the SPI host) ►Store and forward (port to port) ►Cut through (port to port or SPI host to port). The port to port traffic is set to cut through by default. To change to store and forward operation, reset the port cut through enable bit (PORT_CUT_THRU_EN) to 0 in the Configuration Register 2. The switch has a table of 16 MAC addresses that are used deter- mine where to forward frames. A configurable default operation exists for frames with unknown destination addresses (DAs). The switch integrates seven FIFOs with a total of 28 kB of buffer to support the port to port and host to port traffic: ►4 kB host to Port 1 PHY/Port 2 PHY transmit FIFO ►4 kB Port 1 PHY to host high priority receive FIFO ►4 kB Port 1 PHY to host low priority receive FIFO ►4 kB Port 2 PHY to host high priority receive FIFO

the device to work properly. those two pins (see the Transmit Amplitude Advertisement section). assignment does not generally matter. PHY role. This bit is only used when autonegotiation is disabled. (see the Autonegotiation section). Table 9. CFG_MST Settings

0 Prefer slave

1 Prefer master

Table 10. Port 1 and Port 2 Master/Slave Default Configuration

2 Prefer slave

selection are configured for the linked devices. sequence timers and DME pages timing related to autonegotiation.

Table 11. AN_ADV_B10L_TX_LVL_HI_ABL Settings Table 12. AN_ADV_B10L_TX_LVL_HI_REQ Settings Port 1 (respectively Port 2). based on the link partner capabilities. is operation at the 1.0 V p-p transmit level. the 2.4 V p-p transmit level.

2 PHY) can also be configured in software using the following

setting that the remote PHY advertises.

Table 13. Determination of Transmit Level by Autonegotiation1 slave, prefer master, or prefer slave. details on the master/slave configuration. advertisement register, Bits[15:0] (AN_ADV_ABILITY_L). link partner can be predefined or defined during autonegotiation. so only one master is present on the link. PHY with a preferred setting.

Table 14. Determination of Master/Slave by Autonegotiation

0 X 1 0 Master Slave

0 X 1 1 Slave Master

autonegotiation process completes. registers via the SPI to MDIO bridge. (see the Hardware Configuration Pins section). bits for driving the interrupt pin register (IMASK1).

analog.com Rev. 0 | 17 of 125 Those conditions can be set to enable an interrupt on the INT pin using the PHY subsystem interrupt mask register (PHY_SUB- SYS_IRQ_MASK). Following a hardware interrupt on the INT pin, the interrupt source can be checked using the PHY subsystem interrupt status register (PHY_SUBSYS_IRQ_STATUS). Hardware Reset Interrupt Each PHY of the ADIN2111 can also be configured to generate a hardware interrupt after a hardware reset (RESET pin pulled low) by setting the CRSM_HRD_RST_IRQ_EN bit in the system interrupt mask register (CRSM_IRQ_MASK) of the respective PHY. Although both PHYs can be used to generate a hardware interrupt, it is recommended to use PHY 1 for this purpose. Following a hardware interrupt received on the SPI host from the INT pin, the PHYINT bit (respectively P2_PHYINT bit) on the Status Register 0 (respectively Status Register 1) is also set to 1, notifying an interrupt from PHY 1 (respectively PHY 2). The interrupt source can then be checked using the CRSM_HRD_RST_IRQ_LH bit in the system interrupt status reg- ister (CRSM_IRQ_STATUS) of the respective PHY. Software Requested Interrupt For system validation with an external host controller, each PHY of the ADIN2111 can be requested to generate a hardware interrupt on the INT pin using the CRSM_SW_IRQ_REQ bit in the system interrupt mask register (CRSM_IRQ_MASK). Although both PHYs can be used to generate a hardware interrupt, it is recommended to use PHY 1 for this purpose. Following a hardware interrupt received on the SPI host from the INT pin, the PHYINT bit (respectively P2_PHYINT bit) in the Status Register 0 (respectively Status Register 1) is also set to 1, notifying an interrupt from PHY 1 (respectively PHY 2). The interrupt source can then be checked using the CRSM_SW_IRQ_LH bit in the system interrupt status register (CRSM_IRQ_STATUS) of the respective PHY. PHY System Error Interrupts Each of the ADIN2111 PHYs can also generate system errors interrupts. The interrupt flags are located within the reserved bit sections of system interrupt status register (CRSM_IRQ_STATUS) of the respective PHY. The system interrupt mask register (CRSM_IRQ_MASK) must be configured on the respective PHY to allow system error interrupts. Refer to Table 212 for details on the interrupts mask. The ADIN2111 must be hardware reset to recover from a system error interrupt from one of the two PHYs (CRSM_IRQ_STATUS reserved bits read as 1 on the respective PHY). RESET OPERATIONS The ADIN2111 supports the following chip resets: ►Power-on reset ►Hardware reset ►Software reset ►MAC subsystem reset ►PHY 1/PHY 2 subsystem reset All of these resets put the ADIN2111, including the two PHY cores and the internal switch, into a known state. Power-On Reset The ADIN2111 includes a power supply monitoring circuit to ensure that the chip has the proper voltage supply before initiating the power-up sequence. During power-up, the ADIN2111 is held in hardware reset until each of the supplies crosses its minimum rising threshold value and the power is considered good. Hardware Reset A hardware reset is initiated by the power-on reset circuitry or by asserting the RESET pin low for a minimum of 10 µs. The ADIN2111 includes deglitch circuitry on this pin to reject pulses shorter than 1 µs. When the RESET pin is deasserted, all the input/output (I/O) pins are held in tristate mode, the hardware configuration pins are latched, and the I/O pins are configured to their functional mode. When all the external and internal supplies are valid and stable, the crystal oscillator circuit is enabled. After the crystal starts up and stabilizes, the phase-locked loop (PLL) enables. After a delay of 90 ms (maximum) from the deassertion of the RESET pin, all the internal clocks are valid, the internal logic releases from reset, and all the internal SPI, PHY 1, and PHY 2 registers are accessible from the SPI. The CLK25_REF clock output stays low while the RESET pin is asserted low and remains low for another 70 ms (maximum) after the RESET pin deasserts. Software Reset A chip software reset can be initiated by writing 1 to the SWRESET field of the software reset register (SOFT_RST). Note that the software reset does not reset PORT2 PHY. The PORT2 PHY can be reset using the hardware reset or PHY subsystem reset. If a transmission is taking place when the SPI software reset is initiated, the frame transmission stops abruptly and a runt or a

analog.com Rev. 0 | 18 of 125 frame with a bad cyclic redundancy check CRC can be transmitted. Once the chip is reset, the ADIN2111 is ready to bring up links. When this software reset is initiated, a full initialization of the chip, almost equivalent to a hardware reset, is done. The I/O pins are held in tristate mode, the hardware configuration pins are latched, and the I/O pins are configured for their functional mode. The crys- tal oscillator circuit is enabled, and after the crystal starts up and stabilizes, the PLL is enabled. Approximately 10 ms (maximum) after writing the SOFT_RST keys, the internal logic releases from reset and the internal SPI, as well as the two PHY registers, are accessible. The system ready bit (CRSM_SYS_RDY) in the system status register (CRESM_STAT) on each PHY indicates that the start-up sequence is complete, and the respective PHY is ready for normal operation. The CLK25_REF clock output remains low for 25 ms (maximum) following a software reset. PHY Subsystem Reset A PHY subsystem reset is initiated on the ADIN2111 PHY 1 (respectively PHY 2) by setting the respective PHY subsystem reset register bit (CRSM_PHY_SUBSYS_RST) to 1 in the PHY subsystem reset register (CRSM_PHY_SUBSYS_RST). The reset is applied for typically 1.2 µs, and then this bit self clears. All of the PHY 1 (respectively PHY 2) digital circuitry is reset, and any available active link drops. The PHY 1 (respectively PHY 2) subsystem reset does not alter the values of the management registers, which remain accessible throughout the sequence. The subsystem reset is a short reset and can be used to put the device into a known state while retaining the internal register contents. MAC Subsystem Reset A MAC only software reset can be initiated by writing the required pair of keys to the software reset register (SOFT_RST). The reset is applied for about 1.2 µs. The MAC subsystem reset interrupts any transmit/receive packet exchange between the MAC and the two PHYs, but does not drop any existing link or prevent a link from being established. The MAC subsystem reset does not alter the values of the PHY registers. Note that PHY 1 must be out of software power-down for the MAC subsystem reset to take effect. STATUS LEDS The ADIN2111 provides two configurable LED pins for each port: P1_LED_0, P1_LED_1, P2_LED_0, and P2_LED_1 (also noted as Px_LED_x). The LED pin signals can be used to connect external LEDs to indicate the ADIN2111 link status and transmit or receive activity. The activity assigned to each LED is configurable through the LED control register (LED_CNTRL). The LED pins are suitable for ultra low power LEDs. The maximum output current for each LED pin is 8 mA with a VDDIO = 3.3 V. For higher LED power requirements, use an external transistor, as described in the Transistor Controlled LED section. The LED pins can also be connected to a host microcontroller general-purpose input/output (GPIO) (configured as a pulse-width modulated input or hardware interrupt). This configuration is useful in applications where the user interface must be fully handled by an external host controller (for example, an external LED module or display). If the LED pins are directly connected to a host controller, place a low value resistance in series between the ADIN2111 LED pins and the host controller to avoid any potential current surge. The resistor value must be defined based on host controller capabilities and the ADIN2111 LED pins output current capabilities listed in Table 1. LED Pin Multiplexing For the Px_LED_1 pins only (P1_LED_1 and P2_LED_1), an inter- nal multiplexer must be configured to enable the LED signal on the respective pin. Px_LED_1 signals are disabled by default and can be enabled using the DIGIO_LED1_PINMUX bits in the Pin Mux Configuration 1 register (DIGIO_PINMUX) within the respective PHY. The Px_LED_0 pins (P1_LED_0 and P2_LED_1) do not need multiplexing. LED Polarity The four LED pins can be configured to support various LED circuit polarities using the LED polarity register (LED_POLARITY) on the respective PHY. Three polarity modes are available for each LED, as follows: ►Autosense (default) ►Active high ►Active low In autosense mode, the ADIN2111 automatically senses the pin at power-up or reset to select the appropriate polarity configuration. In active high mode, the ADIN2111 is configured to drive the LED from the anode side. In active low mode, the ADIN2111 is configured to drive the LED from the cathode side. Example circuits are described in the LED Circuit Examples sec- tion. LED Function The LED pins can be configured to display various activities of the ADIN2111 using the LED function feature. The LED function

LED1_FUNCTION bits in the LED control register (LED_CNTRL). TION and LED1_FUNCTION are not available in LED Mode 2. See Table 15 for the configuration options of the Px_LED_x pins. Table 15. LED Pins Configuration Summary 1 The 7, 8, 9, and 10 (decimal) settings for the LEDx_FUNCTION bits are not available in Mode 2.

analog.com Rev. 0 | 20 of 125 POWER-DOWN MODES The ADIN2111 supports the following two power-down modes. ►Hardware power-down ►Software power-down Hardware power-down mode achieves the lowest power consump- tion. In this mode, the ADIN2111 is fully turned off and the SPI and the two PHY registers are not accessible. Hardware Power-Down Mode The hardware power-down mode can be used when no operation is required on the ADIN2111 and the power consumption needs to be minimized. The device enters hardware power-down mode when the RESET pin is asserted and held low. In this mode, all analog and digital circuits are disabled, the clocks are gated off, and all the I/O pins are held in tristate mode. In this mode, the ADIN2111 power consumption is equivalent to the internal circuit leakage. The internal registers are not accessible in this mode. Software Power-Down Mode Software power-down mode can be used on each PHY to configure the ADIN2111 registers before bringing a link up. In this mode, the PHY 1 (respectively PHY 2) analog and digital circuits are in a low power state, and the PLL is active and can provide output clocks if configured to do so. Any signals exposed to the MDI pins, P1_TXP and P1_TXN (respectively P2_TXP, P2_TXN), are ignored and any active link on the respective PHY is dropped. The SPI registers are accessible, and the device can be configured using software. The PHY 1 (respectively PHY 2) can be configured to automati- cally enter software power-down mode after power-up, hardware reset, or software reset using the P1_SWPD_EN (respectively P2_SWPD_EN) hardware configuration pin signal. The ADIN2111 can also be instructed to enter software power-down mode by set- ting the software power-down bit (CRSM_SFT_PD) in the software power-down control register (CRSM_SFT_PD_CNTRL) within the respective PHY. The software power-down status bit (CRSM_SFT_PD_RDY) in the system status register (CRSM_STAT) indicates that the respective PHY is in software power-down mode. The ADIN2111 PHY 1 (respectively PHY 2) exits software power- down mode when the CRSM_SFT_PD bit is cleared within the respective PHY. After exiting software power-down, and if autone- gotiation is completed, the PHY 1 (respectively PHY 2) attempts to bring a link up. Note that it is necessary to bring PHY 1 out of software power-down mode to establish a link on PHY 2.

tions with the use of the hardware configuration pins. of the ADIN2111 port settings without the need for software control. and the store and forward switch can be configured in software. through mode (port to port forwarding). Software Power-Down Mode section). configure the device as required by the application. ADIN2111 to active mode using the management interface. is required, refer to Table 17 for the suggested external pin control. Table 16. Default Hardware Configuration Modes Table 17. Recommended Control for Hardware Configuration Pins 1 A low value series resistor is recommended. 2 An external pull-down resistor is recommended. The P1_SWPD_EN pin has a weak internal pull-down resistor. software power-down after reset enabled. power-down after reset disabled.

Table 18. Port 1/Port 2 Software Power-Down (Hardware Configuration)

0 PHY in software power-down after reset

1 PHY not in software power-down after reset

defined in Table 19 and Table 20. 10BASE-T1L high transmit voltage mode, as described in Table 21. and the value of B10L_TX_LVL_HI_ABLE is 1. The Px_TX2P4_EN pins have a weak internal pull-down resistor. 1.0 V p-p and 2.4 V p-p voltage levels on Port 1 and Port 2. Table 19. Port 1 Transmit Amplitude Selection (Hardware Configuration) Table 20. Port 2 Transmit Amplitude Selection (Hardware Configuration) Table 21. B10L_TX_LVL_HI_ABLE Settings transmit level operating mode. Table 22. SPI Protocol (Hardware Configuration)

section for more detailed explanations. bring up a link in unmanaged applications. default (due to the internal pull-up resistor). how to configure the software power-down after reset function. advertise support of the 1.0 V p-p transmit level operation. and 2.4 V p-p transmit levels (due to the internal pull-down resistor). V p-p transmit level on the relevant port. the transmit amplitude level. active, the PHY can start autonegotiation and try to bring up a link. ganizationally unique identifier (OUI), model, and revision numbers. 0x2, and Register Address 0x3 (Clause 22 and Clause 45). device identifier high register (MMD1_DEV_ID1). device identifier low register (MMD1_DEV_ID2). Table 23. ADIN2111 Unique Identifier Values and the system is ready for normal operation.

BRINGING UP 10BASE-T1L LINKS analog.com Rev. 0 | 24 of 125 (PHY 1) and P1_SWPD_EN (PHY 2) hardware configuration pin signals. Switch Initialization After power-up, hardware reset, or software reset, the ADIN2111 switch can be configured via the SPI. Configure the Interrupt Mask Register 0 (IMASK0) register and the mask bits for driving the interrupt pin (IMASK1) register to enable interrupts as required. Write CONFIG0 and CONFIG2 to set up the required functionality of the switch. For example, set the OPEN Alliance chunk size or enable cut through, if required. When the switch is configured, write 1 to the SYNC field in the CONFIG0 register to indicate that the switch configuration is com- plete. By default, the switch drops all frames after power up. The default frame forwarding operation of the switch can be configured via the P1_FWD_UNK2P2, P2_FWD_UNK2P1, P1_FWD_UNK2HOST, and P2_FWD_UNK2HOST bits in the Configuration Register 2 (CONFIG2). The filtering table also needs to be configured. See the Frame Forwarding on Receive section for more details. Configuring the Device for Linking After power-up or reset, configure the ADIN2111 for the desired operation for linking. The ADIN2111 may already be configured as required by the hardware configuration pins, but greater control is available using the management registers via the SPI. The autonegotiation process is used to match the operating mode between a local and remote PHY. For example, autonegotiation is used to ensure that the modes agree between the two devices on which PHY operates as master and which as slave. Autonegotiation is also used to match the transmit level between the two PHYs. Autonegotiation is enabled by default for the ADIN2111 PHYs, and it is strongly recommended to always keep autonegotiation enabled. Autonegotiation is defined by the IEEE standard and in- cludes a number of mechanisms to ensure robust linking operation between PHYs. Autonegotiation is the fastest way to bring up a link. Configuration of Transmit Level Mode The ADIN2111 PHYs can support transmit level operation at either 1.0 V p-p or 2.4 V p-p if the B10L_TX_LVL_HI_ABLE bit in the 10BASE-T1L PMA status register (B10L_PMA_STAT) on the respective PHY is set to 1 and a 3.3 V supply is provided on the AVDD_H pins. The higher transmit level can support longer reach but also has higher power consumption. The ADIN2111 PHYs can support 1.0 V p-p transmit level operation with a 1.8 V supply on the AVDD_H pins at very low power consumption. Each PHY of the ADIN2111 can either be configured to advertise support of both 1.0 V p-p and 2.4 V p-p transmit level operation or to advertise support of only 1.0 V p-p transmit level operation. Refer to the Transmit Level Mode Advertisement section for more details.

1.0 V p-p transmit level operation is required for intrinsically safe

operation. Enable High Voltage Transmit Ability The high voltage transmit ability is set on Port 1 (respectively Port 2) using the P1_TX2P4_EN (respectively P2_TX2P4_EN) hardware configuration pin signal. This signal internally sets the high voltage transmit ability bit B10L_TX_LVL_HI_ABLE (read only), for each PHY, as described in the Transmit Amplitude section. Enable 1.0 V p-p and 2.4 V p-p Transmit Levels To allow both 1.0 V p-p and 2.4 V p-p transmit level operation, set the 10BASE-T1L high level transmit operating mode ability bit (AN_ADV_B10L_TX_LVL_HI_ABL) in the BASE-T1 autonegotiation advertisement register, Bits[47:32] (AN_ADV_ABILITY_H) to 1 to indicate that the device is capable of 2.4 V p-p transmit level operation. A 3.3 V supply is required on the AVDD_H pins. Set 2.4 V p-p Transmit Level as Preferred If 2.4 V p-p transmit level operation is preferred on PHY 1 or PHY 2, set the 10BASE-T1L high level transmit operating mode request bit (AN_ADV_B10L_TX_LVL_HI_REQ) in the BASE-T1 autonego- tiation advertisement register, Bits[47:32] (AN_ADV_ABILITY_H) to 1 on the respective PHY. Set 1.0 V p-p Transmit Level as Preferred If 1.0 V p-p transmit level operation is preferred on PHY 1 or PHY 2, set the AN_ADV_B10L_TX_LVL_HI_REQ bit in the BASE-T1 autonegotiation advertisement register, Bits[47:32] (AN_ADV_B10L_TX_LVL_HI_REQ) to 0 on the respective PHY. Note that autonegotiation determines the transmit level at which the link operates. Enable 1.0 V p-p Transmit Level Only If it is required to only operate the PHY 1 or PHY 2 at the 1.0 V p-p transmit level operation, set the 10BASE-T1L high level trans- mit operating mode ability bit (AN_ADV_B10L_TX_LVL_HI_ABL) in the BASE-T1 autonegotiation advertisement register, Bits[47:32] (AN_ADV_ABILITY_H) to 0 so that the 2.4 V p-p transmit level operation is not advertised. In this case, autonegotiation can only resolve to the 1.0 V p-p transmit level operation, irrespective of the setting that the remote PHY advertises. For very long cable lengths, depending on the characteristics of the cable, it may not be possible to bring up a link at the 1.0 V p-p operation.

BRINGING UP 10BASE-T1L LINKS analog.com Rev. 0 | 25 of 125 When a high level transmit is disabled on PHY1 (respectively PHY2) through the P1_TX2P4_EN (respectively P2_TX2P4_EN) pin signal, the AVDD_H supply can be supplied from either 1.8 V or 3.3 V for the 1.0 V p-p transmit level operation. Transmit Level Mode Advertisement Enable High Voltage Transmit Ability The AVDD_H power rail must be provided with a 3.3 V supply for the ADIN2111 to support the 2.4 V p-p transmit level on Port 1 and Port 2. The high voltage transmit ability is enabled on the ADIN2111 PHY 1 (respectively PHY 2) by setting the P1_TX2P4_EN (respective- ly P2_TX2P4_EN) hardware configuration pin signal low during power-up, hardware reset, or software reset. The 10BASE-T1L high voltage transmit ability bit (B10L_TX_LVL_HI_ABLE) in the 10BASE-T1L PMA status register (B10L_PMA_STAT) of the re- spective PHY is set automatically to the defined hardware configu- ration as follows: ►B10L_TX_LVL_HI_ABLE = 0: 1.0 V p-p only ability ►B10L_TX_LVL_HI_ABLE = 1: 1.0 V p-p and 2.4 V p-p ability See the Configuration of Transmit Level Mode section for more details. Advertise High Voltage Transmit Ability To advertise the high voltage transmit ability during autonegotia- tion between PHY 1 (respectively PHY 2) and a link partner, set the 10BASE-T1L high level transmit operating mode ability bit (AN_ADV_B10L_TX_LVL_HI_ABL) in the BASE-T1 autonegotia- tion advertisement register, Bits[47:32] (AN_ADV_ABILITY_H) to 1 on PHY 1 (respectively PHY 2). This bit can only be set if the ADIN2111 PHY 1 (respectively PHY 2) has the ability to transmit in high voltage mode (B10L_TX_LVL_HI_ABLE = 1 in the 10BASE- T1L PMA status register). High voltage transmit ability only enables the ADIN2111 PHY 1 (respectively PHY 2) to advertise support for both the 2.4 V p-p and 1.0 V p-p levels. The selected level is determined by autonego- tiation with the link partner. See the Transmit Amplitude Advertisement section for more details. Advertise a Request for High Voltage Transmit Level For each PHY, set the 10BASE-T1L high level transmit oper- ating mode request bit (AN_ADV_B10L_TX_LVL_HI_REQ) in the BASE-T1 autonegotiation advertisement register, Bits[47:32] (AN_ADV_ABILITY_H) to 1 to advertise a request for 2.4 V p-p transmit level operation during autonegotiation. This bit can only be set if the ADIN2111 respective PHY has the ability to transmit in high voltage mode (B10L_TX_LVL_HI_ABLE = 1 in the 10BASE- T1L PMA status register). See the Transmit Amplitude Advertisement section for more details. Read Link Partner Advertised Transmit Level For each PHY, the link partner advertised transmit infor- mation can be read from the transmit operating mode ability bit (AN_LP_ADV_B10L_TX_LVL_HI_ABL) and the link partner high level transmit operating mode request bit (AN_LP_ADV_B10L_TX_LVL_HI_REQ) in the BASE-T1 autone- gotiation link partner base page ability register, Bits[47:32] (AN_LP_ADV_ABILITY_H) of the respective PHY. These bits are valid when autonegotiation completes (AN_COMPLETE = 1 in the BASE-T1 autonegotiation status register). See the Transmit Amplitude Advertisement section for more details. Completion of Autonegotiation When autonegotiation completes on PHY 1 or PHY 2, the autone- gotiation complete indication register bit (AN_LINK_GOOD) in the extra autonegotiation status register (AN_STATUS_EXTRA) is set to 1 on the respective PHY. This bit indicates the completion of the autonegotiation sequence and that the enabled PHY link is setting up or active. When autonegotiation completes and the link is up, the autone- gotiation complete register bit (AN_COMPLETE in the BASE-T1 autonegotiation status register) is set to 1, and the contents of the following registers are valid on the respective PHY: ►BASE-T1 autonegotiation advertisement registers: ►BASE-T1 autonegotiation advertisement register, Bits[15:0] (AN_ADV_ABILITY_L) ►BASE-T1 autonegotiation advertisement register, Bits[31:16] (AN_ADV_ABILITY_M) ►BASE-T1 autonegotiation advertisement register, Bits[47:32] (AN_ADV_ABILITY_H) ►BASE-T1 autonegotiation link partner base page ability registers: ►BASE-T1 autonegotiation link partner base page ability regis- ter, Bits[15:0] (AN_LP_ADV_ABILITY_L) ►BASE-T1 autonegotiation link partner base page ability regis- ter, Bits[31:16] (AN_LP_ADV_ABILITY_M) ►BASE-T1 autonegotiation link partner base page ability regis- ter, Bits[47:32] (AN_LP_ADV_ABILITY_H) Link Status The status of each PHY link can be determined by reading the link status register bit (AN_LINK_STATUS) in the BASE-T1 autone- gotiation status register (AN_STATUS) of the respective PHY. This bit latches low. When read as 1, this bit indicates that a valid link is established. If this bit reads 0, the link failed since the last time it was read. This bit latches low. Therefore, if a 0 is read, this bit must be read

BRINGING UP 10BASE-T1L LINKS analog.com Rev. 0 | 26 of 125 a second time to determine if the link status has come up in the interim (see the Latch Low Registers section). If the link is dropped, the autonegotiation process restarts automati- cally. Autonegotiation can be restarted by a request through a write to the autonegotiation restart bit (AN_RESTART) in the BASE-T1 autonegotiation control register (AN_CONTROL) of the respective PHY.

analog.com Rev. 0 | 27 of 125 LOOPBACK MODES Each of the two PHY cores on the ADIN2111 provides the following loopback modes: ►Physical medium attachment (PMA) loopback ►Physical coding sublayer (PCS) loopback ►MAC interface loopback ►MAC interface remote loopback ►MAC loopback ►Host processor loopback These loopback modes test and verify various functional blocks within each PHY. The use of a frame generator and frame checkers allows completely self contained in-circuit testing of the digital and analog datapaths within each PHY core. PMA Loopback The PHY 1 and PHY 2 can be configured in PMA loopback mode. In that case, the MDI must be left open circuit, thereby transmitting into an unterminated connector or cable. In this mode, the signal transmitted from the respective ADIN2111 PHY is echoed back from the open 10BASE-T1L MDI. This test mode is an implementation of the PMA local loopback function defined in Subclause 146.5.6 of the IEEE Standard 802.3cg. Remove any cable connected to the MDI to improve the test mode accuracy. If configured in PMA loopback mode, the respective PHY must be configured in forced link configuration mode (autonegotiation disabled). To enable PMA loopback mode, set the 10BASE-T1L PMA loopback enable bit ( B10L_LB_PMA_LOC_EN ) to 1 in the 10BASE-T1L PMA control register (B10L_PMA_CNTRL) of the respective PHY. PCS Loopback PCS loopback mode loops the transmit data back to the receiver within the PCS block at the input stage of the PHY 1 (respectively PHY 2) digital block. Setting the B10L_LB_PCS_EN bit to 1 in the 10BASE-T1L PCS control register (B10L_PCS_CNTRL) on PHY 1 (respectively PHY 2) enables PCS loopback mode on PHY 1 (respectively PHY 2). When the PCS loopback mode is enabled on PHY 1 (respectively PHY 2), no signal is transmitted to the PHY 1 (respectively PHY 2) MDI pins. MAC Interface Loopback MAC interface loopback mode loops the data received on the ADIN2111 PHY 1 (respectively PHY 2) MAC interface back to the SPI host, and can therefore be used to verify MAC interface connectivity. Set the MAC_IF_LB_EN bit in the MAC interface loop- backs configuration register (MAC_IF_LOOPBACK) to 1 on PHY 1 (respectively PHY 2) to enable MAC interface loopback mode on PHY 1 (respectively PHY 2). If the MAC_IF_LB_TX_SUP_EN bit in MAC_IF_LOOPBACK is set (enabled by default) on PHY 1 (respectively PHY 2), the transmis- sion of the signal received on the PHY MAC interface is not transferred to the ADIN2111 PHY 1 (respectively PHY 2) core. MAC Interface Remote Loopback MAC interface remote loopback mode requires a link up with a remote PHY and enables looping of the data received on the ADIN2111 PHY 1 (respectively PHY 2) to the remote PHY. This linking allows a remote PHY to verify a complete link by ensuring that the PHY receives the proper data. Set the MAC_IF_REM_LB_EN bit in the MAC interface loopbacks configu- ration register (MAC_IF_LOOPBACK) to 1 on PHY 1 (respectively PHY 2) to enable MAC interface remote loopback mode. If the MAC_IF_REM_LB_RX_SUP_EN bit in MAC_IF_LOOPBACK is set (set by default), the data received by the ADIN2111 PHY 1 (respectively PHY 2) from the MDI pins is not transferred to the ADIN2111 MAC. MAC Loopback MAC loopback mode loops the data received on the MAC transmit channel of Port 1 or Port 2 back to the SPI host. MAC loopback mode can be enabled on PORT1 by setting the MAC loopback bit (P1_LOOPBACK_EN) to 1 in the P1 MAC loop- back enable register (P1_LOOP). MAC loopback mode can be enabled on PORT2 by setting the MAC loopback bit (P2_LOOPBACK_EN) to 1 in the P2 MAC loop- back enable register (P2_LOOP). Host Processor Loopback Outside of the loopback modes associated with the PHY cores within the ADIN2111, the host processor can be used to create a full MAC loopback. In a full MAC loopback, whatever frame is received from the MAC is transmitted back to the MAC, as shown in Figure 10.

Figure 10. ADIN2111 Loopback Modes ing and checking functions can be used together or independently. diagnostics clock control register (CRSM_DIAG_CLK_CTRL). the number of frames to be generated. checker error counter registers count these events. errors, and undersized frame errors. delimiter (SSD) state is entered.

Table 24. ADIN2111 Test Modes Summary Test Mode 1 Transmitter output voltage and timing jitter test mode. transmits the data symbol sequence (+1, –1). −1 symbols. This sequence is repeated indefinitely. normal interframe idle signals. specified in Subclause 146.8.3.

1. Enter software power-down mode by writing a 1 to the
2. Check that the ADIN2111 has entered software power-down

status register (CRSM_STAT).

1. Disable autonegotiation by writing a 0 to the AN_EN bit in the

BASE-T1 autonegotiation control register (AN_CONTROL).

1. Set autonegotiation forced mode by writing a 1 to the

ble register (AN_FRC_MODE_EN).

1. Select the desired test mode by writing the appropriate value to

control register (B10L_TEST_MODE_CNTRL).

1. Exit software power-down mode by writing 0 to the

Table 25. PMA Test Modes Configuration

1. Enter software power-down mode by writing a 1 to the
2. Check that the ADIN2111 has entered the software power-down

status register (CRSM_STAT).

1. Disable autonegotiation by writing a 0 to the AN_EN bit in the

BASE-T1 autonegotiation control register (AN_CONTROL).

1. Set autonegotiation forced mode by writing a 1 to the

ble register (AN_FRC_MODE_EN).

1. Set the transmit disable mode by writing a 1 to the
2. Exit software power-down mode by writing 0 to the

2.5 V p-p sine or (filtered) square wave signal. In Figure 20, VS p-p is the peak-to-peak voltage of the clock source. C1 is the series capacitor from the clock source to XTAL_I/CLK_IN. C2 is the capacitor from XTAL_I/CLK_IN to ground. Figure 20. External Clock Connection

following pins: SCLK, CS, SDI, and SDO/SPI_CFG0. transferred over SDI. The last byte is not used. include their own 32-bit CRC. Table 26. Control Write Transaction Table 27. Control Read Transaction Table 28. Burst Write Transaction (Control or Data) Table 29. Burst Read Transaction (Control or Data)

Table 30. Control Write Transaction with CRC Table 31. Control Read Transaction with CRC Table 32. Data Write Transaction with CRC Table 33. Data Read Transaction with CRC cedes the frame data (see Figure 21). stored or discarded by software when reading the receive FIFO. P2_TTSCxH and P2_TTSCxL for Port 2. be started at a defined time relative to the nanoseconds counter.

1. Configure the P1_LED_0 pin to the TS_TIMER function using

the LED control register (LED_CNTRL).

1. To change the default value of the TS_TIMER from 0 to 1,

(TS_CFG). TS_TIMER immediately toggles from 0 to 1.

1. Write to the TS_TIMER_HI and TS_TIMER_LO bits to set the

required high time and low time for the TS_TIMER output.

1. Configure the quantization error correction register (TS_TIM-

1. Write a start time to the TS_TIMER_START register. When the
2. To stop TS_TIMER, write 1 to the TS_TIMER_STOP bit in

to the TS_TIMER_START register.

1. Verify that there is space for the frame by reading the transmit

header and 2-byte size field.

1. Write the size of the frame in bytes, including the 2-byte header
2. Write the frame data including the 2-byte frame header to the

one byte and four bytes of valid data.

1. When the end of frame (EOF) byte of a frame is read from the

triggers if the TX_RDY_MASK is set. Figure 21. MAC Frame: Transmit

3 BYTES

Figure 22. MAC Frame: Receive

Table 34. Frame Header from. Not used on transmit. Set 0 in transmitted frames. ►01: capture in the pair of the TTSCAL and TTSCAH registers. ►10: capture in the pair of the TTSCBL and TTSCBH registers. ►11: capture in the pair of the TTSCCL and TTSCCH registers. ►TIME_STAMP_PARITY: odd parity for the appended time stamp. Not used on transmit. Set to 0 in transmitted frames. transmit. Set to 0 in transmitted frames.

1. Set the Px_RX_RDY_MASK bit to 0 to enable an interrupt when
2. If the Px_RX_RDY bit is asserted, read the MAC receive frame

size register to determine the size of the received frame.

1. Read the frame via the MAC receive register. It is possible to

with 0s if the frame is not a multiple of four bytes in size.

1. Read Px_RX_RDY again. If the value of the bit is 1, another

frame is available to read. Repeat from Step 3. transmit starts immediately on writing to the host transmit FIFO. the frame under runs, the host transmit under run error bit asserts. keys to the SOFT_RST register. TX_FSIZE register without any writes to the transmit register. region of 12 MHz to 16 MHz or greater.

tions for register read/write operations. posed of four bytes of overhead plus the configured payload size. Alliance 10BASE-T1x MACPHY serial interface Version 1.0. control transactions, as shown in Figure 23. Figure 23. Ethernet Data Frame Transfer Followed by Control Transfer

transmit data chunk payload, as shown in Figure 24.

32 BITS

4 BYTES TRANSMIT HEADER AND CHUNK PAYLOAD BYTES

Figure 24. Transmit Data Chunk followed by a 4-byte footer, as shown in Figure 25. Figure 25. Receive Data Chunk without resetting the ADIN2111. transmitted and received frames within the data chunk payload. payloads, as shown in Figure 26 and Figure 27. Figure 26. Transmit Data Chunk Cases

Figure 27. Receive Data Chunk Cases Table 35. Transmit Data Header

1 SEQ NORX RSVD VS DV SV SWO RSVD EV EBO TSC RSVD P

supported by the ADIN2111. This bit must be set to 0. frame data within the current chunk. ►VS[1]: unused, to be set to 0 by the host. ►VS[0]: frame destination port. ►0: frame destination is Port 1. ►1: frame destination is Port 2. this bit is 0, the ADIN2111 ignores the chunk payload. net frame is present in the current transmit data chunk payload. byte described in IEEE Standard 802.3. frame is present in the current transmit data chunk payload. ►01: capture in the pair of the TTSCAL and TTSCAH registers. ►10: capture in the pair of the TTSCBL and TTSCBH registers. ►11: capture in the pair of the TTSCCL and TTSCCH registers. header. The method is odd parity. ►RSVD: reserved. Always set to 0.

Table 36. Receive Data Footer STATUS0 or STATUS1 registers is set and not masked. has received a control or data header with a parity error. ►VS[1]: priority of the received frame. ►0: frame received via the low priority queue. ►1: frame received via the high priority queue. ►VS[0]: port number for received frame. ►0: frame received from Port 1. ►1: frame received from Port 2. this bit is 0, the SPI host ignores the chunk payload. SV is 0, the host must write this field as 0. received frame (EV = 1), and must be 0 at all other times. frame is present in the current receive data chunk payload. byte of the received Ethernet frame. This field is 0 when EV = 0. or 64-bit time stamp is added to the beginning of the SPI frame. This bit must be 0 when SV = 0. a single transaction without incurring a transmit buffer overflow. header. The method is odd parity. register (TX_THRESH) for details. in the Configuration Register 0 (CONFIG0). between a start of frame (SOF) chunk and an EOF chunk. read, the FIFO returns to operating in cut through mode. progress and appends a bad CRC to the frame. MHz and all supported chunk sizes.

Table 37. Receive Latency for 16 MHz for All Supported Chunk Sizes 1 Enough frame data to fill a chunk must be received before a transfer starts on the SPI. The time to receive the frame preamble is also included in this chunk. 3 Realistically, the μC cannot use the data until it receives the receive header at the end of the chunk. Table 38. Control Command Header

0 HDRB WNR AID MMS ADDR [15:0] LEN P

Control transactions consist of one or more control commands. host must always clear this bit. The ADIN2111 ignores this value. ter memory map to access. See Table 39. ►LEN: length. Specifies the number of registers to read or write. a length of 0 reads or writes a single register. Table 39. Register Memory Maps (MMS)

0 Standard control and status (SPI Address 0x00 to Address 0x20)

1 MAC (from SPI Address 0x30)

which register write failed in the case of any bus errors. automatically post incremented. the write command is the last command of the transaction.

32 BITS 32 BITS UNPROTECTED: 32 × (LEN + 1) BITS

Figure 28. OPEN Alliance Control Transaction according to the address increment disable bit in the control header.

32 BITS 32 BITS

Figure 29. Control Read Transaction data from the second start of frame indicator.

bit, and the frame data already in the buffer is dropped. until it receives an end of frame indication (EV = 1). progress of being sent to the SPI host is terminated. error can occur both in store and forward and cut through modes. with frame drop set (FD = 1). keys to the software reset register. tions: the other port and the host SPI port. addresses based on the MAC destination address (DA). set APPLY2PORT1 or APPLY2PORT2 to 1, accordingly. MAC addresses can be masked using the ADDR_MSK_x registers. Figure 30. Frame Forwarding Algorithm high priority FIFO and a low priority FIFO.

Table 40. Port 1 and Port 2 Statistics Counters 1 One set of counters for each port. X represents the port number. P2_RX_DROP_FULL_CNT) counter increments. because it is full, the frame is not counted as a dropped frame. By default, received errored frames do not generate interrupts. error are reported in the error status register (ERR_STATUS). written to the FIFO. A 5-bit ECC is placed alongside the size field. (TX_SPACE) before attempting to write to it. overflow are not counted in the statistics counters. sponds to an MDIO transaction. MSPEED bits in the CONFIG2 register. bits of the next MDIOACCn register. access (this applies to all of the following Clause 45 examples).

analog.com Rev. 0 | 47 of 125 MDIO PHY Address Determination The ADIN2111 allows access to the two PHY registers via an SPI to MDIO master bridge. Each of the two PHYs has a fixed MDIO PHY address, as follows: ►MDIO PHY Address 1: PHY 1 ►MDIO PHY Address 2: PHY 2 Clause 45 MDIO Operation Examples Example write to PHY 1 Register XYZ: 1. Write MDIOACC0 with MDIO_DATA = the address of Regis- ter XYZ, MDIO_DEVAD = the device ID of Register XYZ, MDIO_PRTAD = 0x1, MDIO_OP = 0x0(ADDR), MDIO_ST = 0x0, and TRDONE = 0x0. 2. Write MDIOACC1 with MDIO_DATA = the value to be written to Register XYZ, MDIO_OP = 0x1(WR) and TRDONE = 0x0. 3. Optionally, poll MDIOACC0. TRDONE = 0x1 to determine that the write address operation has completed. 4. Poll MDIOACC1. TRDONE = 0x1 to determine that the write data operation completed. Example read of PHY 1 Register XYZ: 1. Write MDIOACC0 with MDIO_DATA = the address of Register XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0. 2. Write MDIOACC1 with MDIO_OP = 0x3(RD) and TRDONE = 0x0. 3. Poll MDIOACC1. TRDONE = 0x1 to determine that the write data operation completed. MDIOACC1. MDIO_DATA reflects the content of MDIO Register XYZ. Example write operation followed by a read to verify the write operation: 1. Write MDIOACC0 with MDIO_DATA = the address of register ABC and TRDONE = 0x0. 2. Write MDIOACC1 with MDIO_DATA = the value to be written to register ABC, MDIO_OP = 0x1(WR), and TRDONE = 0x0. 3. Write MDIOACC2 MDIO_OP = 0x3(RD) and TRDONE = 0x0. 4. Poll MDIOACC2. TRDONE = 0x1 to verify that all operations completed. MDIO_DATA reflects the content of register ABC. Example of four consecutive writes. It is possible to write a com- mand to all eight registers before checking any. 1. Write MDIOACC0 with MDIO_DATA = the address of Register ABC and TRDONE = 0x0. 2. Write MDIOACC1 with the write data for register ABC, MDIO_OP = 0x1, and TRDONE = 0x0. 3. Write MDIOACC2 with MDIO_DATA = the address of Register DEF and TRDONE = 0x0. 4. Write MDIOACC3 with the write data for register DEF, MDIO_OP = 0x1, and TRDONE = 0x0. 5. Write MDIOACC4 with MDIO_DATA = the address of Register GHJ and TRDONE = 0x0. 6. Write MDIOACC5 with the write data for register GHJ, MDIO_OP = 0x1, and TRDONE = 0x0. 7. Write MDIOACC6 with MDIO_DATA = the address of Register XYZ and TRDONE = 0x0. 8. Write MDIOACC7 with the write data for Register XYZ, MDIO_OP = 0x1, and TRDONE = 0x0. 9. Host polls MDIOACC7. TRDONE = 0x1 to verify that all write data operations are complete. Example burst read starting from Register XYZ: 1. Write MDIOACC0 with MDIO_DATA = the address of the Regis- ter XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0 2. Write MDIOACC1 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 3. Write MDIOACC2 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 4. Write MDIOACC3 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 5. Write MDIOACC4 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 6. Write MDIOACC5 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 7. Write MDIOACC6 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 8. Write MDIOACC7 with MDIO_OP = 0x2(INC_RD) and TRDONE = 0x0. 9. Poll MDIOACC7. TRDONE = 1 to verify that all read data operations are complete. 10.Read MDIOACC1. MDIO_DATA, reflects the content of Register XYZ. 11.Read MDIOACC2. MDIO_DATA, reflects the content of Register XYZ. ADDR + 1. 12.Read MDIOACC3. MDIO_DATA, reflects the content of Register XYZ. ADDR + 2. 13.Read MDIOACC4. MDIO_DATA, reflects the content of Register XYZ. ADDR + 3. 14.Read MDIOACC5. MDIO_DATA, reflects the content of Register XYZ. ADDR + 4. 15.Read MDIOACC6. MDIO_DATA, reflects the content of Register XYZ. ADDR + 5. 16.Read MDIOACC7. MDIO_DATA, reflects the content of Register XYZ. ADDR + 6. Clause 22 MDIO Operations Examples Example of Clause 22 write of Register XYZ: 1. Write MDIOACC0 with MDIO_DATA = write data, MDIO_DEV_AD = the address of the Register XYZ, MDIO_PRTAD = 0x1, MDIO_OP = 0x1(WR), MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

1. Poll MDIOACC0. TRDONE= 0x1 to determine that the write
2. Write MDIOACC0 with MDIO_DEV_AD = the address of the

MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

1. Poll MDIOACC0. TRDONE = 0x1 to determine that the read
2. Write MDIOACC0 with MDIO_DATA = write data,

0x1(Clause 22), and TRDONE = 0x0.

1. Write MDIOACC1 with MDIO_DEV_AD = the address of the

MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

1. Poll MDIOACC1. TRDONE = 0x1 to determine that the read

in the management registers. register addresses from 0x8000 to 0xFFFF. Table 41. Clause 45 Register Groupings MMDs through a single MDIO interface. reads as 0 even if the link has come back up again in the interim. to clear any active latching condition. condition associated with the AN_LINK_STATUS bits. so on, tend to be implemented in multiple clauses.

analog.com Rev. 0 | 49 of 125 ►CRSM_SFT_RST In this example, these are the PMA/PMD, PCS, autonegotiation, and Vendor Specific MMD 1 device address locations (per Table 41). Having multiple address locations for the same register makes the use of the device more complex than necessary, particularly in relation to registers that have latch low or self clear access permissions. This is an unavoidable consequence of the IEEE standard. The ADIN2111 data sheet only calls out a single recommended address location for each of these IEEE registers to simplify the operation and use of the device. In general, the registers intro- duced in the 802.3cg (10BASE-T1L) section of the standard are recommended over older (equivalent) registers. Often, registers in a vendor specific address are recommended, particularly where a register brings a number of useful IEEE register bits into a single register address. The ADIN2111 responds to register accesses to all the IEEE register address locations covered by the 10BASE-T1L standard when the start up completes after a power-on reset, hardware reset, or software reset. PHY Subsystem Registers Read Modify Write Operation All PHY subsystems register write operations must be performed as read modify write operations. If this process is not followed, the value of the register bits can inadvertently change.

Table 42. MAC Register Summary

Table 43. Bit Descriptions for IDVER tion supported by this device. tion supported by this device.

Table 44. Bit Descriptions for PHYID located at PHYID, Bit 31, and OUI, Bit 23 is located at PHYID, Bit 10. Table 45. Bit Descriptions for CAPABILITY 0: transmit FCS validation is not supported. 1: transmit FCS validation is supported. 0: PHY registers are not indirectly accessible. 1: PHY registers are indirectly accessible. 0: PHY registers are not directly accessible. 1: PHY registers are directly accessible. MACPHY to and from the network. 0: cut through not supported. stamps on frame receive from or transmit to the network. 1: IEEE 1588 time stamp capture on frame Tx/Rx is supported. 0: IEEE 1588 time stamp capture on frame Tx/Rx is not supported. Address increment disable is not supported. This field is only used with the Open Alliance SPI protocol. This field is only used with the OPEN Alliance SPI protocol. 1: Tx data chunk sequence and retry is supported.

0: Tx data chunk sequence and retry is not supported. chunk payload Size is 2N, where N is the value of this bit field. This field is only used with the OPEN Alliance SPI protocol. 110: minimum supported chunk payload size is 64 bytes. 101: minimum supported chunk payload size is 32 bytes. 100: minimum supported chunk payload size is 16 bytes. 011: minimum supported chunk payload size is 8 bytes. Table 46. Bit Descriptions for RESET must be held asserted for at least 100 ns for the reset to take effect. This bit is self clearing. Table 47. Bit Descriptions for CONFIG0 upon reset. Once written to a 1 by the SPI host, writing 0 does not clear this bit. Immediately after any reset the SYNC bit clears to 0, RESETC is set to 1, and the interrupt pin asserts. 0: the MACPHY reset and is not configured. 1: the MACPHY is configured. append a CRC to each transmitted frame. frames can begin within any receive chunk when this bit is clear. Only applies to the OA SPI protocol. receive chunk payload when this bit is clear. Only applies to the Open Alliance SPI protocol. be available for writing before INT asserts. Only applies to the OA SPI Protocol.

that data is provided to the device at a rate of > 10 Mbps to ensure frame transmission does not under run. 0: frame receive/transmit time stamps are disabled. 1: frame receive/transmit time stamps are enabled. CRC8. Note this bit cannot be written. Its value is set via sensing a pin on power-up. chunk retries. Not supported. Only applies to the OA SPI Protocol. 0: Support for Tx data chunk sequence and retry is disabled. The MACPHY ignores the Tx header SEQ bit. header and allows the rewriting of Tx data chunks when the SEQ bit does not change. [2:0] CPS Chunk Payload Selector (N). Chunk payload size is 2N. N = 3 minimum and 6 maximum. Default is 64 bytes. chunk payload size for this MACPHY device is indicated in the CPSMIN field of the CAPABILITY register. Only applies to the OA SPI protocol. 100: chunk size is 16 bytes. 101: chunk size is 32 bytes. 110: chunk size is 64 bytes. Table 48. Bit Descriptions for CONFIG2 Port 2. Enables reception of frames that violate the minimum IFG requirement on Port 2.

the frames from the low priority FIFO containing the most data are returned first. . Port 2 contains only low priority frames, all the high priority frames from Port 1 are read first. MAC address, the frame is dropped if this field is 0 and P2_UNK_TO_HOST is 0. MAC address, the frame is dropped if this field is 0 and P1_UNK_TO_HOST is 0. Px_FWD_UNK2HOST or Px_FWD_UNK2Px or writing to the ADDR_FILT_x registers. with the generic SPI protocol. the same 120 MHz clock domain as is used in 1588 timer logic. results in additional jitter on the SFD detection. be burst read in one SPI transaction to ensure all counters are cleared correctly in sequence. clears when using the generic SPI protocol.

receive, the CRC32 is forwarded with the frame to the host where the host verifies it is correct. Port 1. Enables reception of frames that violate the minimum IFG requirement on Port 1. Table 49. Bit Descriptions for STATUS0 bit is reserved with a read-only value of zero. This field is only used with the OPEN Alliance SPI protocol. reset or pin reset this bit is asserted, but this field is masked from asserting an interrupt by default. also sets EXST = 1 in the first Rx footer, or until this bit is cleared by action of the SPI host writing a 1. and the receive frame data was lost. under run error occurs, transmit of the current packet stops.

currently being transmitted is not interrupted by an overflow on the write side of the FIFO. related to the previous frame size written to the TX_FSIZE register. Table 50. Bit Descriptions for STATUS1 used for measuring the IFG on receive can be set in the P2_RX_IFG register. SYS_IRQ_STATUS or CRSM_IRQ_STATUS) on PORT2 PHY to determine the source of the interrupt. can be changed using the RX_LOW_PRI_1ST field. This field is only used with the generic SPI protocol. the ECC error and any other frames in the Tx FIFO is lost/dropped. associated with the ECC error and other frames in the Rx FIFO is not lost/dropped. STATUS0 for OPEN Alliance SPI errors. used for measuring the IFG on receive can be set in the P1_RX_IFG register.

with the generic SPI protocol. Table 51. Bit Descriptions for BUFSTS [15:8] TXC Transmit Credits Available. Number of chunk buffers of transmit data currently available for the SPI host to write. with the OPEN Alliance SPI protocol. [7:0] RCA Receive Chunks Available. Number of chunks of receive data currently available for the SPI host to read. desired. This field is only used with the OPEN Alliance SPI protocol. Table 52. Bit Descriptions for IMASK0 STATUS0 from asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol. error status bit in STATUS0 from asserting the interrupt pin. Available A status bit in STATUS0 from asserting the footer EXST bit. Available A status bit in STATUS0 from asserting the footer EXST bit.

Available A status bit in STATUS0 from asserting the footer EXST bit. STATUS0 from asserting the footer EXST bit. asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol. from asserting the footer EXST bit. status bit in STATUS0 from the footer EXST bit. (TXBUE) status bit in STATUS0 from asserting the footer EXST bit. status bit in STATUS0 from asserting the footer EXST bit. Table 53. Bit Descriptions for IMASK1

when the requested frame was transmitted. Table 54. Bit Descriptions for TTSCAH when the requested frame was transmitted. Table 55. Bit Descriptions for TTSCAL when the requested frame was transmitted. Table 56. Bit Descriptions for TTSCBH when the requested frame was transmitted. Table 57. Bit Descriptions for TTSCBL when the requested frame was transmitted. Table 58. Bit Descriptions for TTSCCH when the requested frame was transmitted. Table 59. Bit Descriptions for TTSCCL

Use this register to access the PHY registers via the SPI to MDIO bridge. Table 60. Bit Descriptions for MDIOACCn MACPHY sets this bit to 1 when the MDIO transaction completes. 10: incremental read command. Clause 45, and called PHY address (PHYAD) for Clause 22. of the MDIO transaction (as indicated by TRDONE), the MACPHY sets this to the 16-bit value read. Table 61. Bit Descriptions for TX_FSIZE field is only used with the generic SPI protocol. The transmit FIFO is written via this register.

Table 62. Bit Descriptions for TX one, two, three, or four bytes valid in the last SPI write of a frame. Only used with the generic SPI protocol. Table 63. Bit Descriptions for TX_SPACE is (64 − 2) × 2 bytes = 124 bytes. Only used with the generic SPI protocol. Table 64. Bit Descriptions for TX_THRESH range of valid values for this field is 1 to 26 half words. Table 65. Bit Descriptions for TX_PRI is set to H50_P50, 50% of the frames transmitted are from the host. options are available: H50_P50, H100_P0, or H0_P100. Values outside of those listed below are reserved.

101: 100/0 host/port. The host is always guaranteed access to wire. 110: 0/100 host/port. Port to port traffic always gets priority. Table 66. Bit Descriptions for FIFO_CLR is appended to the frame. Writes to Rx FIFOs resume at the start of the next received frame. Table 67. Bit Descriptions for SCRATCHn If this register returns 0x00000000_00000001 when read, the oscillator clock is active but the 25 MHz crystal clock is not active. If this register returns 0x00000000_00000003 when read, both the oscillator clock and the 25 MHz crystal clock are active. If this register returns 0x00000000_00000000 (SDO output pad is enabled as CS is low), the SPI slave and MAC core are both still in reset. Only single SPI reads of this register are supported. An SPI burst read must not increment into this register. Table 68. Bit Descriptions for MAC_RST_STATUS 1 MAC_CRYSL_CLK_RDY MAC Crystal Clock Ready. If 0, this field indicates that the MAC core has released from reset. reset when the crystal clock (25 MHz) is ready.

Table 69. Bit Descriptions for SOFT_RST 0x4F1C: Key 1 to reset the MAC logic only. MAC_ONLY reset has no effect. That is, CRSM_SFT_P_CNTRL.CRSM_SFT_PD must be 0. debug access to MAC and PHY registers. 0xA1F6: Key 2 to request release of reset to the MAC core logic. Table 70. Bit Descriptions for SPI_INJ_ERR MISO are properly detected in software. inverted. Also, the time stamp parity bit in the in Rx footer is inverted. from the second word in a burst, the MSB of each echoed 32-bit word is inverted. each 32-bit complement word is inverted. Before modifying the FIFO sizes, frame reception and transmission must be stopped and the FIFOs must be empty. Configure ADDR_RULE to drop all frames and set Px_UNK2HOST and Px_UNK2Px to 0 to ensure all received frames are dropped. Use LES_FIFO_CLR to reset the FIFOs. Then the FIFO sizes can be modified. The total FIFO size must be less than or equal to 28 kB. Table 71. Bit Descriptions for FIFO_SIZE

For debug only. Number of frames in the transmit FIFO. Table 72. Bit Descriptions for TFC Number of Valid Half Words (16 Bits) in the Host Tx FIFO. Table 73. Bit Descriptions for TXSIZE

Table 74. Bit Descriptions for HTX_OVF_FRM_CNT Table 75. Bit Descriptions for MECC_ERR_ADDR and TX_ECC_ERR are cleared, the register is opened to catch the address of the next ECC error. SRAM is 16 bits wide and this address points to a location in SRAM. Table 76. Bit Descriptions for CECC_ERRn CECC_ERR0: low priority Rx FIFO for Port 1. CECC_ERR1: high priority Rx FIFO for Port 2. CECC_ERR2: low priority Rx FIFO for Port 2 (LES only). CECC_ERR3: high priority Rx FIFO for Port 2 (LES only). CECC_ERR4: Tx FIFO from the host. CECC_ERR5: Port 1 to Port 2 Tx FIFO (LES only). CECC_ERR6: Port 2 to Port 1 Tx FIFO (LES only). Contains the upper 16 bits of a MAC address and the forwarding rules associated with the MAC address. When writing the ADDR_FILT_x* registers, two register locations must be written in order for a given table entry. Table 77. Bit Descriptions for ADDR_FILT_UPRn 0: do not apply to Port 2. Do not apply this table entry/rule to frames received on Port 2. 1: apply to Port 2. Apply this table entry/rule to frames received on Port 2.

0: do not apply to Port 1. Do not apply this table entry/rule to frames received on Port 1. 1: apply to Port 1. Apply this table entry/rule to frames received on Port 1. Contains the lower 32 bits of a MAC address in the DA filter table. A write to one of these registers must be preceded by a write to the corresponding ADDR_FILT_UPRn register. Table 78. Bit Descriptions for ADDR_FILT_LWRn The upper 16 bits of a MAC address mask in the DA mask table. order with the UPR register written first and the LWR register written last. Table 79. Bit Descriptions for ADDR_MSK_UPRn The lower 32 bits of a MAC address mask in the DA mask table.

order with the UPR register written first and the LWR register written last. Table 80. Bit Descriptions for ADDR_MSK_LWRn Table 81. Bit Descriptions for TS_ADDEND Table 82. Bit Descriptions for TS_1SEC_CMP Use this register to write to the seconds counter. Table 83. Bit Descriptions for TS_SEC_CNT Use this register to write to the nanoseconds counter. Table 84. Bit Descriptions for TS_NS_CNT 16 decimal. This is because the counters are driven by a 120 MHz clock and increment in steps of 16. Table 85. Bit Descriptions for TS_CFG

the 32-bit free running counter. This bit automatically clears to 0. nanoseconds counter, the seconds counter, and the free running counter. time stamps are captured for all received frames. The counters are not cleared when TS_EN is 0. the counters to get them to a known state before starting again. Table 86. Bit Descriptions for TS_TIMER_HI minimum value that can be written to this field is 16 decimal. Table 87. Bit Descriptions for TS_TIMER_LO minimum value that can be written to this field is 16 decimal.

Table 88. Bit Descriptions for TS_TIMER_QE_CORR the TS_TIMER quantization error. Point in time at which to start the TS_TIMER counter. Table 89. Bit Descriptions for TS_TIMER_START starts, writing to TS_TIMER_STOP stops the timer and return the TS_TIMER output to its default value. Time stamp captured on the assertion of the TS_CAPT pin. Table 90. Bit Descriptions for TS_EXT_CAPT0 Time Stamp Captured on the Assertion of the TS_CAPT Pin. Table 91. Bit Descriptions for TS_EXT_CAPT1 Capture of the free running counter when TS_CAPT asserts. Table 92. Bit Descriptions for TS_FREECNT_CAPT

Table 93. Bit Descriptions for P1_RX_FSIZE frame from a receive FIFO via P1_RX. The receive FIFO is read via this register. It is possible to burst read data from the Rx FIFO over SPI. Table 94. Bit Descriptions for P1_RX Table 95. Bit Descriptions for P1_RX_FRM_CNT Table 96. Bit Descriptions for P1_RX_BCAST_CNT Table 97. Bit Descriptions for P1_RX_MCAST_CNT

Table 98. Bit Descriptions for P1_RX_UCAST_CNT Table 99. Bit Descriptions for P1_RX_CRC_ERR_CNT Table 100. Bit Descriptions for P1_RX_ALGN_ERR_CNT Table 101. Bit Descriptions for P1_RX_LS_ERR_CNT Table 102. Bit Descriptions for P1_RX_PHY_ERR_CNT Table 103. Bit Descriptions for P1_TX_FRM_CNT

Table 104. Bit Descriptions for P1_TX_BCAST_CNT Table 105. Bit Descriptions for P1_TX_MCAST_CNT Table 106. Bit Descriptions for P1_TX_UCAST_CNT Table 107. Bit Descriptions for P1_RX_DROP_FULL_CNT frame is flooded, P1_RX_DROP_FULL_CNT only increments if both FIFOs are full. Table 108. Bit Descriptions for P1_RX_DROP_FILT_CNT Table 109. Bit Descriptions for P1_RX_IFG_ERR_CNT

Table 110. Bit Descriptions for P1_TX_IFG Table 111. Bit Descriptions for P1_LOOP 0: normal operation. Loopback disabled. Table 112. Bit Descriptions for P1_RX_CRC_EN Table 113. Bit Descriptions for P1_RX_IFG supported in this field is 63 decimal. Maximum receive frame length in bytes. Table 114. Bit Descriptions for P1_RX_MAX_LEN

Minimum receive frame length in bytes. Table 115. Bit Descriptions for P1_RX_MIN_LEN The number of frames in the receive FIFO. Table 116. Bit Descriptions for P1_LO_RFC The number of frames in the receive FIFO. Table 117. Bit Descriptions for P1_HI_RFC Number of valid half words (16 bits) in the low priority Rx FIFO. Table 118. Bit Descriptions for P1_LO_RXSIZE Number of valid half words (16 bits) in the high priority Rx FIFO.

Table 119. Bit Descriptions for P1_HI_RXSIZE Number of valid half words (16 Bits) in Port 1 Tx FIFO to be transmitted to Port 2. Table 120. Bit Descriptions for P1TOP2_TXSIZE Table 121. Bit Descriptions for P2_RX_FSIZE P2_RX. Only used with the generic SPI protocol. The receive FIFO is read via this register. It is possible to burst read data from the Rx FIFO over SPI. Table 122. Bit Descriptions for P2_RX returned from the Port 2 Rx FIFOs until the P2_RX_FRM_SIZE register is read first. Table 123. Bit Descriptions for P2_RX_FRM_CNT

Table 124. Bit Descriptions for P2_RX_BCAST_CNT Table 125. Bit Descriptions for P2_RX_MCAST_CNT Table 126. Bit Descriptions for P2_RX_UCAST_CNT Table 127. Bit Descriptions for P2_RX_CRC_ERR_CNT Table 128. Bit Descriptions for P2_RX_ALGN_ERR_CNT Table 129. Bit Descriptions for P2_RX_LS_ERR_CNT

This counter does not increment on LES because a PHY error cannot be determined via the reduced media independent interface (RMII). Table 130. Bit Descriptions for P2_RX_PHY_ERR_CNT Table 131. Bit Descriptions for P2_TX_FRM_CNT Table 132. Bit Descriptions for P2_TX_BCAST_CNT Table 133. Bit Descriptions for P2_TX_MCAST_CNT Table 134. Bit Descriptions for P2_TX_UCAST_CNT Table 135. Bit Descriptions for P2_RX_DROP_FULL_CNT the frame is flooded, the P2_RX_DROP_FULL_CNT only increments if both FIFOs are full.

Table 136. Bit Descriptions for P2_RX_DROP_FILT_CNT Table 137. Bit Descriptions for P2_RX_IFG_ERR_CNT Table 138. Bit Descriptions for P2_TX_IFG Table 139. Bit Descriptions for P2_LOOP 0: normal operation. Loopback disabled. Table 140. Bit Descriptions for P2_RX_CRC_EN

Table 141. Bit Descriptions for P2_RX_IFG supported in this field is 63 decimal. Maximum receive frame length in bytes. Table 142. Bit Descriptions for P2_RX_MAX_LEN Minimum receive frame length in bytes. Table 143. Bit Descriptions for P2_RX_MIN_LEN The number of frames in the receive FIFO. Table 144. Bit Descriptions for P2_LO_RFC The number of frames in the receive FIFO. Table 145. Bit Descriptions for P2_HI_RFC

Number of valid half words (16 bits) in the low priority Rx FIFO. Table 146. Bit Descriptions for P2_LO_RXSIZE Number of valid half words (16 bits) in the high priority Rx FIFO. Table 147. Bit Descriptions for P2_HI_RXSIZE Number of valid half words (16 bits) in Port 2 Tx FIFO to be transmitted to Port 1. Table 148. Bit Descriptions for P2TOP1_TXSIZE when the requested frame was transmitted. Table 149. Bit Descriptions for P2_TTSCAH when the requested frame was transmitted.

Table 150. Bit Descriptions for P2_TTSCAL when the requested frame was transmitted. Table 151. Bit Descriptions for P2_TTSCBH when the requested frame was transmitted. Table 152. Bit Descriptions for P2_TTSCBL when the requested frame was transmitted. Table 153. Bit Descriptions for P2_TTSCCH when the requested frame was transmitted. Table 154. Bit Descriptions for P2_TTSCCL Table 155. ADIN2111 Register Summary

Table 156. Bit Descriptions for MI_CONTROL 14 MI_LOOPBACK Local Loopback (PCS). The loopback bit allows the PHY loopback mode to be engaged. 0 = disable autonegotiation. appropriate software initialization has been performed. Mirrors CRSM_SFT_PD. the PHY is only able to operate in full duplex mode. always reads as 00 because the PHY is only able to operate at 10 Mbps. whether it has determined that a valid link has been established. Table 157. Bit Descriptions for MI_STATUS does not support this technology. indicate that the PHY does not support this technology. indicate that the PHY does not support this technology. that the PHY does not support this technology. indicate that the PHY does not support this technology. to indicate that the PHY does not support this technology.

the PHY does not provide extended status information in Register 0xF. PHY can only transmit data from the MII when it determines that a valid link is established. frames that are not preceded by the preamble pattern. tion process completed and the PHY link is up. Mirrors AN_COMPLETE. PHY has the ability to perform autonegotiation. Mirrors AN_ABLE. cleared until the latching is cleared when the register is read. Mirrors AN_LINK_STATUS. does not incorporate a jabber detect function. The PHY Identifier 1 address allows 16 bits of the OUI to be observed. Table 158. Bit Descriptions for MI_PHY_ID1 The PHY Identifier 2 address allows six bits of the OUI, and the model and revision number to be observed. Table 159. Bit Descriptions for MI_PHY_ID2

Table 160. Bit Descriptions for MMD_ACCESS_CNTRL 01: data, no post increment. 10: data, post increment on reads and writes. 11: data, post increment on writes only. using the interface and mechanisms defined in Clause 22.2.4. Table 161. Bit Descriptions for MMD_ACCESS Table 162. ADIN2111 Register Summary

tisement Register, Bits[15:0]. tisement Register, Bits[31:16]. tisement Register, Bits[47:32]. Page Transmit Register, Bits[15:0].

register is dependent on the hardware configuration pin settings. Table 163. Bit Descriptions for PMA_PMD_CNTRL1 of 1 when a reset is in progress. Otherwise, it returns a value of 0. 11 PMA_SFT_PD PMA Software Power-Down. The PMA software power-down bit puts the chip in a lower power mode. to be held in power-down mode until an appropriate software initialization is performed. and returns it on the receive path. When this bit is set to 0, the PMA works in normal mode.

Table 164. Bit Descriptions for PMA_PMD_STAT1 indicates that the link has dropped since the last time the bit was read. Table 165. Bit Descriptions for PMA_PMD_DEVS_IN_PKG1 autonegotiation MMDs are present. Table 166. Bit Descriptions for PMA_PMD_DEVS_IN_PKG2 Table 167. Bit Descriptions for PMA_PMD_CNTRL2 the only valid value for this bit field is for BASE-T1 PMA/PMD. 0000000: TS_10GBASE_CX4_PMA_PMD. 0000001: TS_10GBASE_EW_PMA_PMD. 0000010: TS_10GBASE_LW_PMA_PMD. 0000011: TS_10GBASE_SW_PMA_PMD. 0000100: TS_10GBASE_LX4_PMA_PMD. 0000101: TS_10GBASE_ER_PMA_PMD. 0000110: TS_10GBASE_LR_PMA_PMD. 0000111: TS_10GBASE_SR_PMA_PMD. 0001000: TS_10GBASE_LRM_PMA_PMD. 0001010: TS_10GBASE_KX4_PMA_PMD. 0001011: TS_10GBASE_KR_PMA_PMD.

0001110: TS_100BASE_TX_PMA_PMD. 0100000: TS_40GBASE_KR4_PMA_PMD. 0100001: TS_40GBASE_CR4_PMA_PMD. 0100010: TS_40GBASE_SR4_PMA_PMD. 0100011: TS_40GBASE_LR4_PMA_PMD. 0100100: TS_40GBASE_FR_PMA_PMD. 0100101: TS_40GBASE_ER4_PMA_PMD. 0101010: TS_100GBASE_LR4_PMA_PMD. 0101011: TS_100GBASE_ER4_PMA_PMD. 0101100: TS_100GBASE_KP4_PMA_PMD. 0101101: TS_100GBASE_KR4_PMA_PMD. 0101110: TS_100GBASE_CR4_PMA_PMD. 0101111: TS_100GBASE_SR4_PMA_PMD. 0110010: TS_10GPASS_XR_D_PMA_PMD. 0110011: TS_10GPASS_XR_U_PMA_PMD. 0110101: TS_25GBASE_LR_PMA_PMD. 0110110: TS_25GBASE_ER_PMA_PMD. 0111000: TS_25GBASE_CR_OR_25GBASE_CR_S_PMA_PMD.

0111001: TS_25GBASE_KR_OR_25GBASE_KR_S_PMA_PMD. 0111010: TS_25GBASE_SR_PMA_PMD. 0111101: TS_BASE_T1_PMA_PMD. 1010011: TS_200GBASE_DR4_PMA_PMD. 1010100: TS_200GBASE_FR4_PMA_PMD. 1010101: TS_200GBASE_LR4_PMA_PMD. 1011010: TS_400GBASE_DR4_PMA_PMD. 1011011: TS_400GBASE_FR8_PMA_PMD. 1011100: TS_400GBASE_LR8_PMA_PMD. Table 168. Bit Descriptions for PMA_PMD_STAT2 listed in PMA_PMD_EXT_ABILITY. Table 169. Bit Descriptions for PMA_PMD_TX_DIS the PMD enables the output on the transmit path. Table 170. Bit Descriptions for PMA_PMD_EXT_ABILITY

read only and writes have no effect. Table 171. Bit Descriptions for PMA_PMD_BT1_ABILITY Table 172. Bit Descriptions for PMA_PMD_BT1_CONTROL 14 CFG_MST Master and Slave Configuration. CFG_MST is used only when autonegotiation is disabled. as 1, the device is configured as a master. Otherwise, the device is configured as a slave. process itself. Note that for ADIN2111, the only valid value is for 10BASE-T1L.

Table 173. Bit Descriptions for B10L_PMA_CNTRL transmit path. Otherwise, it enables output on the transmit path. operating mode. Otherwise, the device works in the 1.0 V p-p operating mode. Table 174. Bit Descriptions for B10L_PMA_STAT T1L high voltage (2.4 V p-p) transmit level operating mode. value of this register selects normal operation without management intervention as the initial state of the device. Table 175. Bit Descriptions for B10L_TEST_MODE_CNTRL enabled, the PHY repeatedly transmits the data symbol sequence (+1, −1). transmits ten +1 symbols followed by ten −1 symbols.

Table 176. Bit Descriptions for B10L_PMA_LINK_STAT the remote receiver status is OK. local receiver status is OK. that the descrambler status is OK. Table 177. Bit Descriptions for MSE_VAL 10BASE-T1L idle symbol power is 0.64422. Table 178. Bit Descriptions for PCS_CNTRL1

on the receive path. When this bit is set to 0, the PCS works in normal mode. Table 179. Bit Descriptions for PCS_STAT1 Table 180. Bit Descriptions for PCS_DEVS_IN_PKG1 Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. Table 181. Bit Descriptions for PCS_DEVS_IN_PKG2 Table 182. Bit Descriptions for PCS_STAT2

Table 183. Bit Descriptions for B10L_PCS_CNTRL Table 184. Bit Descriptions for B10L_PCS_STAT descrambler has unlocked since the last time the bit was read. Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 185. Bit Descriptions for AN_DEVS_IN_PKG1 autonegotiation MMDs are present. Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. Table 186. Bit Descriptions for AN_DEVS_IN_PKG2

Table 187. Bit Descriptions for AN_CONTROL default and it is strongly recommended that it is always enabled. it returns a value of one until the autonegotiation process is initiated. Table 188. Bit Descriptions for AN_STATUS resets to 0 on a read of the AN_STATUS register. registers are valid. This bit returns 0 if the autonegotiation is disabled, clearing the AN_EN bit. link failed since the last time it was read. Table 189. Bit Descriptions for AN_ADV_ABILITY_L figuration. When this bit is set as 0, the master/slave configuration is a preferred mode.

Table 190. Bit Descriptions for AN_ADV_ABILITY_M configuration is Bit 4 of the transmitted nonce field). Table 191. Bit Descriptions for AN_ADV_ABILITY_H AN_ADV_B10L_TX_LVL_HI_REQ bit for more details. must use the low voltage (1.0 V p-p) transmit operating mode.

AN_LP_ADV_ABILITY_L is read. Table 192. Bit Descriptions for AN_LP_ADV_ABILITY_L 0: preferred mode (AN_LP_ADV_MST is a preferred configuration). 1: forced mode (AN_LP_ADV_MST is a forced configuration). the latched value rather than the current value. Table 193. Bit Descriptions for AN_LP_ADV_ABILITY_M

the latched value rather than the current value. Table 194. Bit Descriptions for AN_LP_ADV_ABILITY_H capable of using 10BASE-T1L energy efficient Ethernet. 13 AN_LP_ADV_B10L_TX_LVL_HI_ABL Link Partner 10BASE-T1L High Level Transmit Operating Mode Ability. is capable of using 10BASE-T1S half duplex. set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L. Table 195. Bit Descriptions for AN_NEXT_PAGE_L

as 0 (the toggle bit is set automatically by the arbitration state machine). the valid values are defined in IEEE Standard 802.3. 5: organizationally unique identifier tagged message. 6: autonegotiation device identifier tag code. set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L. Table 196. Bit Descriptions for AN_NEXT_PAGE_M set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L. Table 197. Bit Descriptions for AN_NEXT_PAGE_H of Standard 802.3. The values of AN_LP_NEXT_PAGE_M and AN_LP_NEXT_PAGE_H are latched when this register is read. Table 198. Bit Descriptions for AN_LP_NEXT_PAGE_L

5: organizationally unique identifier tagged message. 6: autonegotiation device identifier tag code. latched value rather than the current value. Table 199. Bit Descriptions for AN_LP_NEXT_PAGE_M rather than the current value. Table 200. Bit Descriptions for AN_LP_NEXT_PAGE_H Table 201. Bit Descriptions for AN_B10_ADV_ABILITY duplicate of the AN_ADV_B10L_TX_LVL_HI_ABL bit. a duplicate of the AN_ADV_B10L_TX_LVL_HI_REQ bit.

Table 202. Bit Descriptions for AN_B10_LP_ADV_ABILITY duplicate of the AN_LP_ADV_B10L_TX_LVL_HI_ABL bit. duplicate of the AN_LP_ADV_B10L_TX_LVL_HI_REQ bit. (AN_EN = 0), forced mode is engaged if AN_FRC_MODE_EN is 1. Table 203. Bit Descriptions for AN_FRC_MODE_EN This register is provided in addition to AN_STATUS. Table 204. Bit Descriptions for AN_STATUS_EXTRA entering the autonegotiation good check state. 2: success, low transmit levels (1.0 V p-p) selected. 3: success, high transmit levels (2.4 V p-p) selected.

2: success, PHY is configured as slave. 3: success, PHY is configured as master. are not shown to be reserved. register is a consistent set, that is, a set of values in effect at the time the register address is read. Table 205. Bit Descriptions for AN_PHY_INST_STATUS check state or the AN good state. That is, the link_control signals have not been set to enable. PHY is operating as master (and not slave). PHY is operating as slave (and not master). the organizationally unique identifier (OUI) to be observed. Table 206. Bit Descriptions for MMD1_DEV_ID1

the OUI along with the model number and revision number to be observed. Table 207. Bit Descriptions for MMD1_DEV_ID2 Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 208. Bit Descriptions for MMD1_DEVS_IN_PKG1 autonegotiation MMDs are present. Table 209. Bit Descriptions for MMD1_DEVS_IN_PKG2 Table 210. Bit Descriptions for MMD1_STATUS 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address.

associated interrupts are not enabled. A reserved interrupt being triggered indicates a fatal error in the system. Table 211. Bit Descriptions for CRSM_IRQ_STATUS Controls whether or not the interrupt signal is asserted in response to various events. Table 212. Bit Descriptions for CRSM_IRQ_MASK level testing. This bit always reads as 0 because it is self clearing. interrupt because this bit is initialized when a hardware reset occurs. Table 213. Bit Descriptions for CRSM_SFT_RST fully initializes, almost equivalent to a hardware reset. Table 214. Bit Descriptions for CRSM_SFT_PD_CNTRL 0 CRSM_SFT_PD Software Power-down. The software power-down register puts the chip in a lower power mode. the chip to be held in power-down mode until an appropriate software initialization is performed.

Table 215. Bit Descriptions for CRSM_PHY_SUBSYS_RST Table 216. Bit Descriptions for CRSM_MAC_IF_RST Table 217. Bit Descriptions for CRSM_STAT Table 218. Bit Descriptions for CRSM_PMG_CNTRL CRSM diagnostics clock control. Table 219. Bit Descriptions for CRSM_DIAG_CLK_CTRL

The MGMT_CFG_VAL address allows reading of the package configuration values. Table 220. Bit Descriptions for MGMT_PRT_PKG Table 221. Bit Descriptions for MGMT_MDIO_CNTRL only be set in those cases, and cleared immediately after the initialization is complete. Table 222. Bit Descriptions for DIGIO_PINMUX 111: LED_1 output not enabled.

LED on blink time = LED0_ON_N4MS × 4 ms. LED off blink time = LED0_OFF_N4MS × 4 ms. LED switches off for either loss of link or receipt of activity. If LEDx_FUNCTION is programmed to an activity signal, the LED is off with no activity. The LED switches on upon receipt of activity. Table 223. Bit Descriptions for LED0_BLINK_TIME_CNTRL [15:8] LED0_ON_N4MS LED_0 On Blink Time. LED_0 on blink time is calculated by 4 ms × LED0_ON_N4MS bit field. Recommended value is greater than 3. [7:0] LED0_OFF_N4MS LED_0 Off Blink Time. LED_0 off blink time is calculated by 4 ms × LED0_OFF_N4MS bit field. Recommended value is greater than 3. LED on blink time = LED1_ON_N4MS × 4 ms. LED off blink time = LED1_OFF_N4MS × 4 ms. LED switches off for either loss of link or receipt of activity. If LEDx_FUNCTION is programmed to an activity signal, the LED is off with no activity. The LED switches on upon receipt of activity.

Table 224. Bit Descriptions for LED1_BLINK_TIME_CNTRL [15:8] LED1_ON_N4MS LED_1 On Blink Time. LED_1 on blink time is calculated by 4 ms × LED1_ON_N4MS bit field. Recommended value is greater than 3. [7:0] LED1_OFF_N4MS LED_1 Off Blink Time. LED_1 off blink time is calculated by 4 ms × LED1_OFF_N4MS bit field. Recommended value is greater than 3. Table 225. Bit Descriptions for LED_CNTRL LED1_FUNCTION selection and activity. 0: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave not qualified by link_status. 1: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave are qualified by link_status. 0: LED Mode 1. If there is activity, blink at the rate defined by MMR LED1_BLINK_TIME_CNTRL. chip is dependent on the selected clock source frequency. REM_RCVR_STATUS, CLK25_REF, TX_TCLK, and CLK_120MHz. this is controlled via the LED1_LINK_ST_QUALIFY MMR.

LED0_FUNCTION selection and activity. 0: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave not qualified by link_status. 1: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave are qualified by link_status. 0: LED Mode 1. If activity, blink at the rate defined by MMR LED0_BLINK_TIME_CNTRL. The CLK25_REF, TX_TCLK, CLK_120MHZ options are clock out features with the LED controller bypassed. The waveform transmitted off chip is dependent on the selected clock source frequency. REM_RCVR_STATUS, CLK25_REF, TX_TCLK and CLK_120MHz. is controlled via the LED0_LINK_ST_QUALIFY MMR.

Allows the LED polarity to be automatically sensed by the internal logic or allows reconfiguration by the user. Table 226. Bit Descriptions for LED_POLARITY 0: LED autosense. LED active high or low as per autosense. 0: LED autosense. LED active high or low as per autosense. Table 227. Bit Descriptions for MMD2_DEV_ID1

Table 228. Bit Descriptions for MMD2_DEV_ID2 Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 229. Bit Descriptions for MMD2_DEVS_IN_PKG1 autonegotiation MMDs are present. Vendor Specific 1 and Vendor Specific 2 MMDs are present. Table 230. Bit Descriptions for MMD2_DEVS_IN_PKG2 This address corresponds to the Vendor Specific MMD 2 status register. Table 231. Bit Descriptions for MMD2_STATUS 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address. bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system.

Table 232. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS Controls whether or not the interrupt signal is asserted in response to various events. Table 233. Bit Descriptions for PHY_SUBSYS_IRQ_MASK and error counter registers count these events. Table 234. Bit Descriptions for FC_EN checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit. The status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register.

Table 235. Bit Descriptions for FC_IRQ_EN received data after it is looped back at the MAC interface. Table 236. Bit Descriptions for FC_TX_SEL to be transmitted by the PHY. 1: check frames from the MAC interface to be transmitted by the PHY. 0: check frames received by the PHY from the remote end. The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY. Table 237. Bit Descriptions for RX_ERR_CNT this bit is self clearing upon reading. read, the receive frame counter register is latched so that the error count and the receive frame count are synchronized. Table 238. Bit Descriptions for FC_FRM_CNT_H the receive frame counter register is latched so that the error count and receive frame count are synchronized.

Table 239. Bit Descriptions for FC_FRM_CNT_L This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status. error count and receive frame count are synchronized. Table 240. Bit Descriptions for FC_LEN_ERR_CNT error count and the receive frame count are synchronized. Table 241. Bit Descriptions for FC_ALGN_ERR_CNT This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set. frame receive count are synchronized. Table 242. Bit Descriptions for FC_SYMB_ERR_CNT oversized error count and the receive frame count are synchronized. Table 243. Bit Descriptions for FC_OSZ_CNT

This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes. frame error count and the receive frame count are synchronized. Table 244. Bit Descriptions for FC_USZ_CNT nibble frame count and the receive frame count are synchronized. Table 245. Bit Descriptions for FC_ODD_CNT ensures that the odd preamble packet count and the receive frame count are synchronized. Table 246. Bit Descriptions for FC_ODD_PRE_CNT false carrier events count and the receive frame count are synchronized. Table 247. Bit Descriptions for FC_FALSE_CARRIER_CNT generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled (CRSM_DIAG_CLK_EN).

Table 248. Bit Descriptions for FG_EN or all zeros. The FG_RSTRT bit restarts the frame generator. Table 249. Bit Descriptions for FG_CNTRL_RSTRT 000: no frames after completion of current frame. 001: random number data frame. 100: alternative 0x55 data field. 101: data field decrementing from 255 (decimal) to 0. frames generated is specified by the FG_NFRM_H and FG_NFRM_L registers. Table 250. Bit Descriptions for FG_CONT_MODE_EN continuous mode or burst mode. generating frames indefinitely. generated. Enable the frame checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit.

Table 251. Bit Descriptions for FG_IRQ_EN interrupt when it has transmitted the programmed number of frames. 1: enable the frame generator interrupt. 0: disable the frame generator interrupt. Table 252. Bit Descriptions for FG_FRM_LEN This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator. Table 253. Bit Descriptions for FG_IFG_LEN inserted between frames by the frame generator. Table 254. Bit Descriptions for FG_NFRM_H Table 255. Bit Descriptions for FG_NFRM_L

Table 256. Bit Descriptions for FG_DONE this bit goes high and it latches high until it is unlatched by reading. MAC interface loopbacks configuration. Table 257. Bit Descriptions for MAC_IF_LOOPBACK Table 258. Bit Descriptions for MAC_IF_SOP_CNTRL set if no SFD is received in the first eight bytes. is set. The RX SOP signal remains set until the end of the frame.

PCB LAYOUT RECOMMENDATIONS analog.com Rev. 0 | 124 of 125 LAND PATTERN The LFCSP has an exposed pad underneath the package that must be soldered to the PCB ground for mechanical, electrical, and thermal reasons. For thermal impedance performance and to maximize heat transfer to the PCB, the use of a 4 × 4 array of thermal vias beneath the exposed ground pad is recommended. Via tenting is also recommended. COMPONENT PLACEMENT AND ROUTING Prioritization of the critical traces and components helps simplify the routing exercise. Place and orient the critical traces and compo- nents first to ensure an effective layout. The critical components are the crystal and load capacitors, the CEXT_2, CEXT_3, CEXT_6, and CEXT_7 capacitors, and all bypass capacitors local to the ADIN2111 device. Prioritize these components for placement and routing, as follows: ►Place the decoupling capacitor as close as possible to their input pins. ►Minimize traces turns, and use a 45° corner. ►Avoid traces crossing power planes on adjacent layers. ►Avoid stubs. ►Keep the MDI traces (P1_TXP, P1_TXN, P2_TXP, and P2_TXN) as short as possible. ►Use matched length differential lines for each port with a differen- tial impedance of 100 Ω. ►Avoid vias on a high speed signal. Place ground vias next to the signal vias to improve the return current path. CRYSTAL PLACEMENT AND ROUTING Particular attention is required on the crystal placement and routing to ensure minimum current consumption, reduce stray capacitance, and improve noise immunity. Follow these recommendations: ►Place the crystal, capacitors as close as possible to the ADIN2111 XTAL_I/CLK_IN and XTAL_O pins. ►Place the load capacitors close to each other. ►Use a local GND plane (copper island) for the crystal and load capacitors with a single point connection to the main GND. ►Reduce parasitic capacitance by keeping the XTAL_I and XTAL_O traces away from each other. ►Adding a copper keepout on the layer beneath the crystal can also reduce the parasitic capacitance. PCB STACK Follow these recommendations for the PCB stack: ►Use a PCB stack with a minimum of four layers. Consider six layers or more with external layers used as ground planes to improve EMI issues (optional). ►Define copper layer thickness based on the application and power requirements. ►Use internal layers for the power and ground planes. ►Use external layers for the signal traces. ►Use via stitching to improve ground and reduce EMI. The stitching pattern and via to via gaps are defined based on the application.

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A.

0.02 NOM

0.203 REF

0.20 MIN

5.50 REF

Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP]