ADIN1200

ADIN1200 (Rev.B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 88

Technical content

Robust, Industrial, Low Power, 10 Mbps and 100 Mbps Ethernet PHY Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►10BASE-Te/100BASE-TX IEEE® 802.3TM compliant ►MII, RMII and RGMII MAC interfaces ►100BASE-TX RGMII latency transmit: <124 ns, receive <250 ns ►100BASE-TX MII latency transmit: <52 ns, receive <248 ns ►Programmable RGMII timing delay and drive current ►Supports TSN ►EMC test standards ►IEC 61000-4-5 surge (±4 kV) ►IEC 61000-4-4 electrical fast transient (EFT) (±4 kV) ►IEC 61000-4-6 conducted immunity (10 V) ►EN55032 radiated emissions (Class A) ►EN55032 conducted emissions (Class A) ►Unmanaged configuration using multilevel pin strapping ►MDIO/MDC management interface and interrupt pin ►EEE in accordance with IEEE 802.3az ►Start of packet detection for IEEE 1588 time stamp support ►Enhanced link detection ►Cable diagnostics (TDR and signal analysis) ►Configurable LED ►Crystal oscillator/clock input: 25 MHz ►25 MHz/125 MHz synchronous clock output ►Jumbo frame support up to 16 kBytes ►Synchronous Ethernet (SyncE) clock recovery ►32-lead, 5 mm × 5 mm LFCSP small package ►Wide temperature range: specified for −40°C to +105°C and −40°C to +85°C ambient operation ►Low power consumption ►139 mW for 100BASE-TX ►3.3 V/2.5 V/1.8 V MAC interface VDDIO supply ►Single-supply operation with 3.3 V VDDIO ►Integrated power supply monitoring and POR

APPLICATIONS

►Industrial automation ►Process control ►Factory automation ►Robotics and motion control ►Time sensitive networking (TSN) ►Building automation ►Test and measurement ►Industrial internet of things (IoT) GENERAL DESCRIPTION The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps Ethernet transceiver with low latency specifications designed for industrial Ethernet applications. This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circui- try, input and output clock buffering, management interface and subsystem registers, and media access control (MAC) interface and control logic to manage the reset, clock control and pin configura- tion. The ADIN1200 is available in a 5 mm × 5 mm, 32-lead lead frame chip scale package (LFCSP) and can operate with a single 3.3 V supply, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1200 allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value and the power is considered good. Brownout protection is provided by monitoring the supplies to detect if one or more of them drops below a minimum falling threshold and holding the device in hardware reset until the power supplies return and satisfy the power-on-reset (POR) circuit. The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC and the ADIN1200, allowing access to control and status information in the PHY core management registers. The interface is compatible with both IEEE® 802.3™ Standard Clause 22 and Clause 45 management frame structures. The ADIN1200 can support cable lengths up to 180 meters. Note that throughout this data sheet, multifunction pins, such as XTAL_I/CLK_IN/REF_CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL_I, when only that function is relevant. Table 1. Related Products with a wide scope and will be phased in as quickly as possible. Thank you for your patience.

analog.com Rev. B | 2 of 88 Detailed Overview of fido5200 and

REVISION HISTORY

5/2024—Rev. A to Rev. B 10/2023—Rev. 0 to Rev. A

analog.com Rev. B | 3 of 88

analog.com Rev. B | 4 of 88 11/2019—Revision 0: Initial Version

analog.com Rev. B | 5 of 88 Figure 1.

analog.com Rev. B | 6 of 88 AVDD_3P3 = 3.3 V, VDDIO = 1.8 V, all specifications at −40oC to +105oC, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS Supply Voltages AVDD_3P3 3.135 3.3 3.465 V VDDIO 3.135 3.3 3.465 V 3.3 V mode 2.25 2.5 2.75 V 2.5 V mode 1.71 1.8 1.89 V 1.8 V mode POWER CONSUMPTION1 100% data throughput, full activity Supply Current 100BASE-TX AVDD_3P3 Current (IAVDD_3P3) 31 mA VDDIO Current (IVDDIO) 22 mA 3.3 V mode 21 mA 2.5 V mode 20 mA 1.8 V mode Power 100% data throughput, full activity 100BASE-TX 175 mW VDDIO = 3.3 V 155 mW VDDIO = 2.5 V 139 mW VDDIO = 1.8 V TIMING/LATENCY2 100BASE-TX MII Transmit 52 ns Receive 248 ns Total 300 ns 100BASE-TX RGMII3 Transmit 84 88 92 ns Receive 250 ns Total 334 338 342 ns 100BASE-TX RGMII4 Transmit 84 104 124 ns Receive 250 ns Total 334 354 374 ns 100BASE-TX RMII5 Transmit 72 92 ns Receive 328 348 368 ns Total 400 430 460 ns DIGITAL INPUTS/OUTPUTS Applies to MAC interface, MDC pin, MDIO pin, and INT_N pin VDDIO = 3.3 V Input Low Voltage (VIL) 0.8 V Input High Voltage (VIH) 2.0 V Output Low Voltage (VOL) 0.4 V Output low current (IOL) minimum = 4 mA Output High Voltage (VOH) 2.4 V Output high current (IOH) minimum = 4 mA VDDIO = 2.5 V VIL 0.7 V VIH 1.7 V

Table 2. (Continued)

1.7 IOH minimum = 4 mA

50 MHz RMII mode

1 MAC Interface capacitive load of 5 pF, REFCLK is disabled. 2 The DPTH_MII_BYTE register defines whether the programmed transmit first in, first out (FIFO) depth is bytes or nibbles for MII modes (10BASE-Te and 100BASE-TX). FIFO is larger and is observed as longer latency times. The latency specifications in Table 2 have this bit set to 0 for MII. ADIN1200 reference clock). Refer to the FIFO_SYNC Register section. handles any phase difference. 6 Where load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

Rise and fall time specifications are defined from 10% to 90%, unless otherwise noted. Table 3. Power-Up Timing 1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required. Figure 2. Power-Up Timing Table 4. Hardware Reset Timing

Table 11. RMII Timing Figure 9. RMII Timing

TA = 25°C, unless otherwise noted. ing conditions for extended periods may affect product reliability. measured in a one cubic foot sealed enclosure. θJC_TOP is the junction to case thermal resistance. Table 13. Thermal Resistance

1 Test Condition 1: thermal impedance simulated values are based on a JE-

DEC 2S2P thermal test board with thermal vias. See JEDEC JESD51. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 10. Pin Configuration Table 14. Pin Function Descriptions XTAL_I/CLK_IN/REF_CLK, leave XTAL_O open circuit. 8 XTAL_I/CLK_IN/REF_CLKAVDD_3P3 Input for Crystal (XTAL_I). Single-Ended 25 MHz Reference Clock (CLK_IN). 50 MHz RMII Reference Clock Input in RMII Mode (REF_CLK). MII Carrier Sense Output (CRS). Indicates the presence of a carrier to MAC. 18 MDC Management Data Clock Input up to 5.5 MHz. requires a 1.5 kΩ pull-up resistor to VDDIO. 11 MDI_0_P AVDD_3P3 Transmit/Receive Differential Pair 0 Supporting 10 Mbps and 100 Mbps. 12 MDI_0_N AVDD_3P3 Transmit/Receive Differential Pair 0 Supporting 10 Mbps and 100 Mbps. 13 MDI_1_P AVDD_3P3 Transmit/Receive Differential Pair 1 Supporting 10 Mbps and 100 Mbps. 14 MDI_1_N AVDD_3P3 Transmit/Receive Differential Pair 1 Supporting 10 Mbps and 100 Mbps. 1 TXD_0 VDDIO RGMII/RMII/MII Transmit Data 0 Input. See the MAC Interface section.

Table 14. Pin Function Descriptions (Continued) 2 TXD_1 VDDIO RGMII/RMII/MII Transmit Data 1 Input. See the MAC Interface section. 3 TXD_2 VDDIO RGMII/MII Transmit Data 2 Input. See the MAC Interface section. 4 TXD_3 VDDIO RGMII/MII Transmit Data 3 Input. See the MAC Interface section. 23 RXD_3/PHYAD_3 VDDIO RGMII/MII Receive Data 3 Output (RXD_3). See the MAC Interface section. PHY Address Hardware Configuration Pin (PHYAD_3). 24 RXD_2/PHYAD_2 VDDIO RGMII/MII Receive Data 2 Output (RXD_2). See the MAC Interface section. PHY Address Hardware Configuration Pin (PHYAD_2). 26 RXD_1/PHYAD_1 VDDIO RGMII/RMII/MII Receive Data 1 Output (RXD_1). See the MAC Interface section. PHY Address Hardware Configuration Pin (PHYAD_1). 27 RXD_0/PHYAD_0 VDDIO RGMII/RMII/MII Receive Data 0 Output (RXD_0). See the MAC Interface section. PHY Address Hardware Configuration Pin (PHYAD_0). 28 RXC/RX_CLK/MACIF_SEL0VDDIO RGMII Receive Clock Output (RXC). 25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps. MII Receive Clock Output (RX_CLK). 25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps. MAC Interface Selection Hardware Configuration Pin (MACIF_SEL0). See Table 26.

29 RX_CTL/RX_DV/CRS_DV/

and RX_ER signals using both edges of RXC. cates that valid data is present on RXD_0 to RXD_3 in MII mode. is nonidle. See the RMII Interface Mode section. MAC Interface Selection Hardware Configuration Pin (MACIF_SEL1). See Table 26. relationship to the XTAL_I/CLK_IN clock. TX_ER signals using both edges of TXC. indicates that transmission data is available on the TXD_x lines. (LED_0). The LED can be active high or active low. Recommended use is active low. activity (this behavior can be changed by software). MII Collision Detect Output (COL). COL indicates a collision condition. 100 ppm/°C temperature coefficient (TC)) to GND.

21 GP_CLK/RX_ER/MDIX_MODEVDDIO General-Purpose Output on Which PHY Clocks Can Be Made Available (GP_CLK). indicates that the PHY has detected a receive error. capacitor to GND as close as possible to this pin. 5 GND Ground. This pin must be connected to ground on the board. capacitors to GND as close as possible to these pins. and AVDD_3P3 can be connected to the same supply to minimize power supplies. vias beneath the exposed GND pad is also required. internal power rails, the area around these is a keepout zone. and the pin is referred to using the functional signal(s) name throughout the data sheet. Table 15. Pin Function Descriptions for Each MAC Interface Option

1 TXD_0 Yes TXD_0 TXD_0 TXD_0 TXD_0

2 TXD_1 Yes TXD_1 TXD_1 TXD_1 TXD_1

3 TXD_2 Yes TXD_2 TXD_2 TXD_2

4 TXD_3 Yes TXD_3 TXD_3 TXD_3

8 XTAL_I/CLK_IN/REF_CLKNo REF_CLK6

16 LED_07/COL/TX_ER No COL TX_ER

17 INT_N6/CRS Yes CRS

21 GP_CLK6/RX_ER No RX_ER RX_ER RX_ER

23 RXD_3 Yes RXD_3 RXD_3 RXD_3

24 RXD_2 Yes RXD_2 RXD_2 RXD_2

26 RXD_1 Yes RXD_1 RXD_1 RXD_1 RXD_1

27 RXD_0 Yes RXD_0 RXD_0 RXD_0 RXD_0

28 RXC/RX_CLK Yes RXC RX_CLK RX_CLK

Table 15. Pin Function Descriptions for Each MAC Interface Option (Continued)

29 RX_CTL/RX_DV/CRS_DVYes RX_CTL RX_DV RX_DV CRS_DV

30 TX_CTL/TX_EN Yes TX_CTL TX_EN TX_EN TX_EN

31 TXC/TX_CLK Yes TXC TX_CLK TX_CLK

1 Hardware pin configuration signal(s) have been omitted for clarity. 3 Wherever the field is left blank, the pin function is the first function listed in the Mnemonic column. 4 EEE advertisement enabled/disabled using hardware pin configuration. See the Hardware Configuration Pins section. 5 EEE does not support half-duplex. Therefore, no CRS or COL pin is required. 6 A 50 MHz reference clock must be supplied on the XTAL_I/CLK_IN/REF_CLK pin when using the RMII MAC interface option. 7 These pin functions can also be reconfigured via software.

supporting 10 Mbps and 100 Mbps data rates. Figure 21. RGMII MAC-PHY Interface Signals

2.5 MHz RXC signal to synchronize the RXD_x receive data in

2.5 MHz in 100BASE-TX or 10BASE-Te modes respectively and

Figure 22. DLL Waveform Figure 23. MII MAC to PHY Interface Signals (COL) is asserted in a collision condition.

Figure 24. RMII MAC-PHY Interface Signals CLK_IN/REF_CLK pin for both the transmit and receive interfaces. false carrier can be disabled by software. transmission data is available on the TXD_0 and TXD_1 pins. ities and compares them to those received from the link partner. duplex setting common across the two devices. RESTART_ANEG bit in the MII control register. 802.3 standard details the timers related to autonegotiation. detected, it is identified in the PHY_STATUS_1 register. access via the MDIO interface. 16 and Table 17, respectively. ►OP: the operation code indicates type of frame transaction.

spacing between register address field and data field. user-selectable conditions (IRQ_MASK register, Address 0x0018). each device to determine the origin of the interrupt. Table 16. Clause 22 Management Interface Frame Format Table 17. Clause 45 Management Interface Frame Format

configuration and to transmit when operating in MDIX configuration. Figure 25. Media Dependent Interface Table 18. MDI/MDI-X Pin Mapping these put the ADIN1200, including the PHY core in a known state. until each supply crosses its minimum rising threshold value. Table 19. Brown Out Protection Threshold Values the RESET_N pin low. Bring the pin low for a minimum of 10 µs. controls when the PHY is brought up. The RESET_N pin is referenced to the AVDD_3P3 voltage domain. input voltage thresholds of the RESET_N pin. registers are accessible 3 ms after the deassertion of RESET_N. registers in the subsystem and PHY core registers. ►The MAC interface block is reset. configured to enter software power- down mode after reset).

analog.com Rev. B | 25 of 88 Software Reset The ADIN1200 supports the following software resets that reset specific circuit blocks under software control: ►Subsystem software reset with pin configuration ►Subsystem software reset ►PHY core software reset Subsystem Software Reset with Pin Configuration The ADIN1200 supports a software reset capability that behaves in a similar way to a hardware reset (see Row 1 and Row 2 of Table 20). A subsystem reset with a pin configuration can be initiated by setting GE_SFT_RST_CFG_EN (Address 0xFF0D) to 1 before setting GE_SFT_RST bit (Address 0xFF0C) to 1. This subsystem software reset follows the same reset sequence as the POR and hardware reset except that the crystal oscillator is not disabled and the clock stabilization step is skipped. The state of the hardware configuration pins is read and latched. These configuration pins set the default values of the pin dependent registers in the subsystem and PHY core registers. The MAC interface block and PHY core are reset. If a 125 MHz clock is selected as the PHY output clock the GP_CLK pin, the PHY core CMU is not reset. Otherwise, the CMU is reset. The main difference between this type of reset and a hardware reset is that the crystal oscillator is not disabled. Note that the GE_SFT_RST_CFG_EN bit is reset to its default value of 0 by this type of reset. The following events occur after a subsystem software reset with pin configuration: ►The crystal oscillator circuit is not disabled during this type of reset. ►The hardware configuration pins are read and the values latch- ed. These pins set the default values of the pin dependent registers in the subsystem and PHY core registers. ►The MAC interface block is reset. ►The PHY core is reset. ►The PHY core CMU is reset. ►If a 125 MHz clock is selected as the PHY output clock, it is not available on GP_CLK during this reset. Subsystem Software Reset The subsystem can be reset by setting GE_SFT_RST (Subsystem Register 0xFF0C, Bit 0) to 1. This bit is self clearing. Setting this bit resets the sub-system and PHY core registers, the MAC interface block and the PHY core. It does not reread the hardware configu- ration pins and uses previously latched values of the hardware configuration pins to set the default values of the pin dependent registers in the subsystem and PHY core registers. The following events occur after a subsystem software reset: ►The crystal oscillator circuit is not disabled during this type of reset. ►The hardware configuration pins are not reread. The pin depend- ent registers in the subsystem registers and PHY core registers are reset to the default values defined by the previously latched values of the hardware configuration pins. ►The MAC interface block is reset. ►The PHY core is reset. ►If a 125 MHz clock is selected as the PHY output clock (GP_CLK), the PHY core CMU is not reset. Otherwise, the CMU is reset. ►The selected PHY output clock (if enabled) is available on GP_CLK during this reset. PHY Core Software Reset The PHY core registers can be reset by setting the SFT_RST bit in the MII_CONTROL register, Address 0x0000 to 1. This bit is self clearing. Setting this bit resets the PHY core registers, the MAC interface block and the PHY core. This bit does not reread the hardware configuration pins and uses previously latched values of the hardware pins to set the default values of the pin-dependent registers in the PHY core registers. The subsystem registers are not reset to default values. This is a useful way to reset the PHY core registers to a known configuration defined by software without resetting the rest of the ADIN1200 circuitry. The following events occur after a PHY core software reset: ►The crystal oscillator circuit is not disabled during this type of reset. ►The hardware configuration pins are not reread. The pin depend- ent registers in PHY core registers are reset to the default values defined by the previously latched values of the hardware configuration pins. The subsystem registers are not reset to their default values. ►The MAC interface block is not reset. ►The PHY core is reset. ►If a 125 MHz clock is selected as the PHY output clock (GP_CLK), the PHY core CMU is not reset. Otherwise, the CMU is reset. ►The selected PHY output clock (if enabled) is available on GP_CLK during this reset.

Table 20. ADIN1200 Reset Options Summary

analog.com Rev. B | 27 of 88 POWER-DOWN MODES The ADIN1200 supports a number of power-down modes: hard- ware, software, energy detect power-down, and EEE LPI mode. The lowest power mode is hardware power-down where the device is turned fully off and is not accessible. Hardware Power-Down Mode Hardware power-down mode is useful when operation of the ADIN1200 is not required and power is to be minimized. The ADIN1200 enters hardware power-down mode when the RESET_N pin is asserted and held low. In this mode, all analog and digital circuits are disabled, the CMU is disabled, the clocks are gated off and the only power is the leakage power of the circuits. The management interface registers are not accessible in this mode. The following events occur in hardware power-down mode: ►All analog and digital circuits are disabled. ►The MAC interface output pins (output pins with respect to the ADIN1200) are tristated. Internally, these pins have a weak pull-down resistor, so these outputs are pulled low. This assumes no external pull-up resistors connected to these pins. ►All internal clocks are gated off. ►The PHY output clock (available on GP_CLK) is disabled. ►The management interface registers are not accessible. Software Power-Down Mode In software power-down mode, the ADIN1200 is powered down, the management interface can be accessed, and the ADIN1200 can be configured. The ADIN1200 does not attempt to bring up links until enabled. Software power-down mode is useful when the device is being configured by software before links are brought up. The ADIN1200 can be configured to enter software power-down mode after reset using the appropriate pull-up/pull-down resistors on the LINK_ST pin and LED_0 pin, which sets the default value of the SFT_PD bit, Address 0x0000, to 1. The ADIN1200 also enters software power-down mode when the SFT_PD bit is set to 1. In software power-down mode, the analog and digital circuits are in a low power state. Typically, the CMU is disabled, most clocks are gated off, and the clock for the remaining digital circuitry runs at 25 MHz. Any signal or energy on the MDI pins (MDI_x_x) is ignored and no links are brought up. The management interface registers are accessible and the device can be configured using software. If the ADIN1200 is configured to output a 125 MHz clock on the GP_CLK pin, the CMU is enabled and the power in this mode is higher. The following events occur in software power-down mode: ►All analog transmit and receive circuits are disabled. ►The MAC interface output pins (output pins with respect to the ADIN1200) are driven to a known idle state. All outputs except RXC/RX_CLK are driven low and RXC/RX_CLK is driven high. ►Most internal clocks are gated off. ►The selected PHY output clock (if enabled) is available on GP_CLK. ►The management interface registers are accessible. The ADIN1200 exits software power-down mode when the SFT_PD bit is cleared. At this point, the PHY attempts to bring up links according to its configuration. For example, if autonegotiation is enabled and all speeds are enabled, it advertises all speeds and starts to send autonegotiation link pulses. Energy Detect Power-Down Mode In energy detect power-down mode, the ADIN1200 is powered down but still monitors the line for signal energy. Typically, the ADIN1200 enters this mode when there is no cable plugged in and remains in this mode until a remote link partner is available. Energy detect power-down mode can be enabled using the ap- propriate pull-up/pull-down resistors on the LINK_ST pin and LED_0 pin (see Table 24) or by setting the NRG_PD_EN bit (PHY_CTRL_STATUS_2 register, Address 0x0015) to 1. When the PHY is in normal operation (not software power-down) and energy detect power-down mode is enabled, the PHY enters energy detect power-down mode after a number of seconds of silence on the line. This is a very low power mode in which the analog and digital circuits are in a low power state. Typically, the CMU is disabled and most clocks are gated off. The PHY monitors the line for signal energy and sends a link pulse once every second. If signal energy is detected, the PHY exits energy detect power-down mode and starts sending link pulses. The following events occur when in energy detect power-down mode: ►All analog and digital circuits are disabled. ►Most internal clocks are gated off. ►The selected PHY output clock (if enabled) is available on the GP_CLK pin. ►The management interface registers are accessible. ►The PHY monitors the line for signal energy. Typically, the PHY enters energy detect power-down mode when the cable is unplugged and exits this mode when a cable is plugged in and a remote link partner appears. In this mode, the PHY periodically wakes up and transmits a link pulse on the MDI_0_x and MDI_1_x pins to ensure that a lock out is avoided where both local and remote PHY are in an energy detect power-down mode. EEE, Low Power Idle Mode The ADIN1200 supports EEE and is compliant with the IEEE 802.3 standard. EEE can be used to reduce power consumption when no data is being transmitted by either the local or remote end. Both devices must have EEE enabled and advertised. If EEE is advertised by the local and remote PHYs, an EEE link is brought

analog.com Rev. B | 29 of 88 This clock selection is configured in software. By default, the PHY clock is off. Note that selecting the 125 MHz free running clock has an impact on power consumption, because the CMU is powered except during reset and power-up. POWER SUPPLY DOMAINS The ADIN1200 has two power supply domains, as follows, and can be supplied with a single supply if VDDIO is powered from 3.3 V: ►AVDD_3P3 is the 3.3 V analog power supply input for the PHY MDI interface, XTAL oscillator, DLL, RESET_N, and LED circuitry. ►VDDIO enables the MDIO and MAC interface voltage supply to be configured independently of the other circuitry on the ADIN1200. In most cases, RMII/MII is operated at 3.3 V and RGMII at 2.5 V. However, the MAC interface can operate at 3.3 V, 2.5 V, or 1.8 V to allow maximum system flexibility, depending on what is supported by the MAC. There are no power supply sequencing requirements for the order of power being applied to the device. See the Power-Up Timing section for more details.

power is applied to the device. AVDD_3P3 rail rather than VDDIO. Figure 27. Hardware Configuration Pin Implementation resistor used in Mode 1 and Mode 4 with a 2.5 kΩ resistor. Table 21. Configuration Mode Resistor Values 1 Note that the supply rail for the LED_0 pin is AVDD_3P3 rather than VDDIO. Therefore, pull up any pull-up resistor on the LED_0 pin to AVDD_3P3. resistor ratios for the values used. ADIN1200 pins are available for configuring the PHY address. has internal pull-up resistors on these pins.

Table 22. Hardware Configuration Pin Summary 1 Hardware configuration pin is the last pin name in the pin mnemonic. 2 The internal pull-down resistor has a typical value of 45 kΩ. 3 The internal pull-down resistor is only enabled while RESET_N is asserted. Table 23. PHY Address Configuration

0 Low Low Low Low

1 Low Low Low High

2 Low Low High Low

3 Low Low High High

4 Low High Low Low

5 Low High Low High

6 Low High High Low

7 Low High High High

8 High Low Low Low

9 High Low Low High

10 High Low High Low

11 High Low High High

12 High High Low Low

13 High High Low High

14 High High High Low

15 High High High High

Table 24. PHY Configuration

10 HD/FD and 100 HD/FD Downspeed, EDPD and EEE MODE_4 MODE_4 1

10 HD/FD and 100 HD/FD MODE_1 MODE_4 2

10 HD/FD and 100 HD/FD Software power-down mode after reset MODE_3 MODE_4 3

10 FD and 100 FD MODE_4 MODE_3 4

100 FD MODE_4 MODE_1 5

Table 24. PHY Configuration (Continued)

10 FD MODE_1 MODE_2 6

100 HD MODE_2 MODE_2 7

100 FD MODE_3 MODE_3 8

1 HD means half duplex and FD means full duplex. 2 If no function is listed in this column, only the PHY speed is configured using this row. shared with the LINK_ST and LED_0 functional pins, respectively. as enable or disable autonegotiation. and the speed is forced (Row 6 to Row 8 of Table 24). and AUTONEG_ADV (Address 0x0004). (MII_CONTROL register, Address 0x0000). at the MDI_x_x pins, the ADIN1200 enters a low power mode. ed or the remote PHY is powered down. Idle Mode section for more details. Table 25. Auto MDIX Configuration

be used to select any of the remaining MAC interface modes. changes are made to the MAC interface configuration registers. software to configure the MAC interface to RMII. Table 26. MAC Interface Selection

enables external cable loopback. must be set to enable line driver loopback. bit (MII_CONTROL register, Address 0x0000, Bit 14). Figure 28. Loopback Modes

PHY comes from the frame generator and not the MAC interface. bled (DIAG_CLK_EN bit, PHY_CTRL_1 register, Address 0x0012). frame generator done bit is set (FG_DONE bit, Address 0x941E). register count these events. register (Address 0x940A and Address 0x940B, respectively). times the bad start of stream delimiter (SSD) state is entered. and checked by the PHY 1 frame checker. Figure 29. Remote Loopback Used Across Two PHYs for Self Check Purposes

analog.com Rev. B | 36 of 88 CABLE DIAGNOSTICS The ADIN1200 has on-chip cable diagnostics capabilities. This cable analysis can be used to detect cable impairments that may be preventing the establishment of the link speed or degrading performance and can be performed both when the link is up or when the link is down. Cable Length Estimate Each time a 100BASE-TX link is brought up, the ADIN1200 reports an estimate (typically ±15 m) of the cable length based on the signal processing. This can be read in the cable diagnostics cable length estimate register (CDIAG_CBL_LEN_EST register, Address 0xBA25). This estimate is not available for a 10BASE-Te link. Cable Analysis with TDR When the link is down, the ADIN1200 can run cable fault detection using time domain reflectometry (TDR). By transmitting pulses and analyzing the reflections, the PHY can detect cable faults like opens, shorts, cross pair shorts, and the distance to the nearest fault. The PHY can also determine that each differential pair is well terminated and does not have any faults. Put the remote PHY in a power-down state or disconnect the PHY to run cable fault detection because remote PHY link pulses can interfere with the analysis of the reflected pulses and can return a pair busy result. The cable fault detection is automatically run on the two pairs looking at all combinations of pair faults by first putting the PHY in standby (clear the LINK_EN bit, PHY_CTRL_3 register, Address 0x0017) and then enabling the diagnostic clock (set the DIAG_CLK_EN bit, PHY_CTRL_1 register, Address 0x0012). Cable diagnostics can then be run (set the CDIAG_RUN bit in the CDIAG_RUN register, Address 0xBA1B). The results are reported for each pair in the cable diagnostics results registers, the CDIAG_DTLD_RSLTS_0 and the CDIAG_DTLD_RSLTS_1 (Ad- dress 0xBA1D and Address 0xBA1E, respectively). The distance to the first fault for each pair is reported in the cable fault distance registers, CDIAG_FLT_DIST_0, CDIAG_FLT_DIST_1 (Addresses 0xBA21 and Addresses 0xBA22, respectively). Cable Polarity Inversion, Pair Swaps A polarity inversion on each pair is reported in the pair polarity inversion register bits (PHY_2_STATUS register, Address 0x001F, Bits[13:10]) and the B_10_POL_INV bit (PHY_STATUS_1 register, Address 0x001A). Pair swaps are reported in the pair swap register bit (PAIR_01_SWAP bit, Address 0x001A). Cable Signal Quality, MSE The ADIN1200 provides a measure of the signal quality of the established link. This relates directly to the signal to noise seen by the PHY receiver. When the link is up, the signal quality on each pair is indicated in the mean square error (MSE) register for each pair (MSE_A register, Address 0x8402). The MSE register values in the range of 3 to 5 are expected into a cable length up to 100 m, as the cable length gets longer and external noise increases, the MSE reported increases. To calculate the associated signal-to-noise ratio (SNR) during idle, apply the following formula to the MSE value read: SNR (dB) = 10 × Log10 (MSE/1024) (1) An SNR value > 21 dB (MSE of 8 or 9) indicates essentially error-free performance. At 18 dB or 19 dB (MSE of 13 or 14), occasional errors may be observed over a 24-hour period. ENHANCED LINK DETECTION The ADIN1200 supports enhanced link detection, which is early detection and indication of link loss. This is a feature where the received signal is monitored, and if a significant number of consec- utive samples of the signal are not as expected, early indication of link down is indicated. The ADIN1200 can simultaneously monitor for a significant number of consecutive 0s, a significant number of consecutive 1s, or a significant number of consecutive invalid levels. If enhanced link detection is enabled (it is enabled by default), the ADIN1200 typically reacts to a break in the cable within 10 μs and indicates link down via the LINK_ST pin. If enhanced link detection is not enabled, the ADIN1200 follows the IEEE standard, and in 100BASE-TX, it can take more than either 350 ms or 750 ms. Enhanced link detection is enabled by default. To change the configuration for 100BASE-TX via the enhanced link detection 100BASE-TX enable register bits (FLD_EN register, Address 0x8E27, Bit 5, Bit 3, and Bit 1). The latched status of the enhanced link detection function can be read via the enhanced link detection status bit, FAST_ LINK_DOWN_LAT (Address 0x8E38). Having enhanced link detection enabled is not suitable for all applications. This causes the PHY to react quickly to high levels of disturbance on the MDI lines. This configuration must be consid- ered when performing conformance testing and EMC testing where the media dependent interface can be exposed to fast transients. These transients can trigger enhanced link detection to bring the link down during such tests. In this case,users must configure all bits in the FLD_EN register to 0. START OF PACKET INDICATION The ADIN1200 includes the detection and indication of the start of packets (SOP) on the transmit and receive side to support IEEE 1588 time stamp controls and give the MAC more accurate timing information.

analog.com Rev. B | 37 of 88 The transmit and receive SOP indication can be made available at any of the following pins under software configuration: GP_CLK, LINK_ST, INT_N, and LED_0 using the following override control registers: ►GE_IO_GP_CLK_OR_CNTRL bits, Address 0xFF3D ►GE_IO_GP_OUT_OR_CNTRL bits, Address 0xFF3E ►GE_IO_INT_N_OR_CNTRL bits, Address 0xFF3F ►GE_IO_LED_A_OR_CNTRL bits, Address 0xFF41 The detection of the transmit SOP is done after internal PHY FIFO. Therefore, there is a fixed delay between the SOP indication at the pin to the actual SOP at the MDI_x_x pins. Start of packet indication is enabled via the SOP transmit and receive enables (set the SOP_TX_EN bit, and the SOP_RX_EN bit, Address 0x9428). The SOP is asserted by default on the first byte or nibble of the frame. The SOP can be configured to be asserted when the start frame delimitator (SFD) is detected in the frame by setting the SOP SFD enable bit (SOP_SFD_EN, Address 0x9428). The SOP indication, by default, is asserted for the duration of the frame. The SOP can be configured to be asserted for a program- mable number of cycles. This is configured by setting the SOP N-cycle enable bit (SOP_NCYC_EN, Address 0x9428), and the number of cycles in this case is configured via the SOP N by 8 minus 1 cycles register (SOP_N_8_CYC_M_1_D_EN register, Address 0x9428, Bits[6:4]). The ADIN1200 start of packet detection and indication circuit in- cludes the ability to delay each of the SOP transmit and receive indications by a programmable number of clock cycles. The pur- pose of this on the receive side is to support MAC interfaces with long latency so that the received frame SOP indication is not asserted before the MAC receives the frame. The purpose of this on the transmit side is to align the transmit SOP indication assertion close to the reference point set on the MDI_x_x pins (so that the time stamping point does not have to be adjusted at the MAC/switch side). There are programmable registers for the delays for 100BASE-TX mode, and 10BASE-T mode for transmit and receive. These are programmed via the SOP_RX_DEL register and SOP_TX_DEL register, Address 0x9429 and Address 0x942A, respectively.

each MAC interface configuration mode. protocol by firmware that is downloaded from a host processor. Figure 30. Simplified Typical Application Block Diagram

tion pins, providing the ability to configure 16 PHY addresses. may affect the expected PHY address setting. MACIF_SEL0 = MODE_4 by pulling it to VDDIO. resistors are as shown in Table 21. for its configuration and must be configured with external resistors. configuration suited to the link partner. Table 27. Auto MDIX Configuration and the PHYs and a 1.2 V rail for the switch. The ADIN1200 operates from a minimum of one power supply rail. configured independently of the other circuitry on the ADIN1200. VDDIO can be supplied from 1.8 V to 3.3 V.

Figure 31. Detailed Block Diagram of the fido5200 with Two ADIN1200 PHYs common-mode noise to reach the PHY. method because there is no overhead in terms of configuration. = 0 and bit GE_RGMII_RX_ID_EN = 1.

802.3 with an additional set of registers that are accessed indirectly. provided using the interface specified under Clause 22. ister Summary section list the PHY core and subsystem registers. Table 29. PHY Core Register Summary

Table 29. PHY Core Register Summary (Continued)

Table 30. Bit Descriptions for MII_CONTROL be configured in unmanaged applications. configured in unmanaged applications. 1: enable autonegotiation process. 0: disable autonegotiation process.

Table 30. Bit Descriptions for MII_CONTROL (Continued) configuration pins. The PHY can be held in reset until initialized by the software. 1: electrically isolate PHY from MAC interface by setting MAC interface pins to tristate (even if active). 1: restart the autonegotiation process. 1: enable collision signal test. 0: disable collision signal test. independent interface is only enabled when the PHY has determined that a valid link has been established. Table 31. Bit Descriptions for MII_STATUS

Table 31. Bit Descriptions for MII_STATUS (Continued) information in Register 0x000F. accepts management frames with preamble suppressed. 1: autonegotiation process completed. 0: autonegotiation process not completed. 1: remote fault condition detected. 0: no remote fault condition detected. 1: PHY is able to perform autonegotiation. 0: PHY is not able to perform autonegotiation. 1: jabber condition detected. 0: no jabber condition detected. organizationally unique identifier (OUI) to be observed. Table 32. Bit Descriptions for PHY_ID_1 with the model number and revision number to be observed. Table 33. Bit Descriptions for PHY_ID_2

Table 33. Bit Descriptions for PHY_ID_2 (Continued) default reset value of this register is dependent on the hardware configuration pins settings. Table 34. Bit Descriptions for AUTONEG_ADV neither has anything additional to transmit. 12 EXT_NEXT_PAGE_ADVThe extended next page bit indicates that the local device supports transmission of extended next pages. The use of extended next page is orthogonal to the negotiated data rate, medium, or link technology. pause operation for full duplex links. and always reads as 1'b0 because this technology is not supported. which allows the default operation of the PHY to be configured in unmanaged applications. pins, which allows the default operation of the PHY to be configured in unmanaged applications. which allows the default operation of the PHY to be configured in unmanaged applications. which allows the default operation of the PHY to be configured in unmanaged applications. indicating that the PHY only supports IEEE Standard 802.3.

Table 35. Bit Descriptions for LP_ABILITY next page bits to Logic 0, indicating that neither has anything additional to transmit. 1: link partner has successfully received its link code word. 0: link partner has not received its link code word. partner advertises asymmetric pause operation for full duplex links. partner advertises pause operation for full duplex links. partner advertises 100BASE-T4. partner advertises 100BASE-TX full duplex. partner advertises 100BASE-TX half duplex. partner advertises 10BASE-T full duplex. partner advertises 10BASE-T half duplex. indicates IEEE Standard 802.3.

Table 36. Bit Descriptions for AUTONEG_EXP 1: received next page storage location is specified by Bit 5 (RX_NP_LOC). 0: received next page storage location is not specified by Bit 5 (RX_NP_LOC). 1: link partner next pages are stored in Register 0x0008. 0: link partner next pages are stored in Register 0x0005. 1: a fault has been detected via the parallel detection function. 0: a fault has not been detected via the parallel detection function. 1: link partner is next page capable. 0: link partner is not next page capable. 1: local device is next page capable. 0: local device is not next page capable. 1: a new page has been received. 0: a new page has not been received. 1: link partner is autonegotiation capable. 0: link partner is not autonegotiation capable. Table 37. Bit Descriptions for TX_NEXT_PAGE the last next page to be transmitted. exchange. This bit always takes the opposite value of the toggle bit in the previously exchanged link code word. Logic 0, the bit encoding of the link code word is interpreted as an unformatted page.

Table 38. Bit Descriptions for LP_RX_NEXT_PAGE next page(s). Otherwise, this is the last next page to be transmitted. 1: link partner has successfully received its link code word. 0: link partner has not received its link code word. 13 LP_NP_MSG_PAGELink partner message page (MP) is used by the next page function to indicate that this is a message page. Otherwise, this is an unformatted page. page bit is set to Logic 0, the bit encoding of the link code word is interpreted as an unformatted page. Table 39. Bit Descriptions for MSTR_SLV_STATUS 1: local receiver okay (LOC_RCVR_STATUS = okay). 0: local receiver not okay (LOC_RCVR_STATUS = not okay). 1: remote receiver okay (REM_RCVR_STATUS = okay). 0: remote receiver not okay (REM_RCVR_STATUS = not okay). PAGE_RX_LAT bit (Register 0x0006, Bit 1) has been set to 1. 1: link partner is capable of 1000BASE-T full duplex. 0: link partner is not capable of 1000BASE-T full duplex. PAGE_RX_LAT bit (6.1) has been set to 1. 1: link partner is capable of 1000BASE-T half duplex. 0: link partner is not capable of 1000BASE-T half duplex.

Table 39. Bit Descriptions for MSTR_SLV_STATUS (Continued) Table 40. Bit Descriptions for EXT_STATUS accessible registers for cases where the station management does not support Clause 45. Table 41. Bit Descriptions for EXT_REG_PTR registers using normal Clause 22 access for cases where the station management does not support Clause 45. reading or writing the EXT_REG_DATA register. An EMI register can be directly accessed using Clause 45 access. accessible registers for cases where the station management does not support Clause 45. Table 42. Bit Descriptions for EXT_REG_DATA registers using normal Clause 22 access for cases where the station management does not support Clause 45. See Table 41 for further details. This register provides access to various PHY control register bits, in particular for diagnostic clocking control and MDI crossover.

Table 43. Bit Descriptions for PHY_CTRL_1 which allows the default operation of the PHY to be configured in unmanaged applications. 1: enable auto MDI/MDIX. Prefer MDI if MAN_MDIX is 1'b0 and prefer MDIX if MAN_MDIX is 1'b1. 1: operate in MDIX configuration. 0: operate in MDI configuration. the frame generator/checker. 1: enable PHY diagnostics clock. 0: disable PHY diagnostics clock. This register provides access to PHY loopback control bits. Table 44. Bit Descriptions for PHY_CTRL_STATUS_1 loopback bit (Register 0x0000, Bit 14) to be set. impedance mismatch. The PHY can then operate by receiving the reflection from its own transmission. received from the remote PHY back to the remote PHY using all of the digital and analog circuitry of the PHY. IEEE loopback bit (Register 0x0000, Bit 14) must not be set.

The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY. Table 45. Bit Descriptions for RX_ERR_CNT Table 46. Bit Descriptions for PHY_CTRL_STATUS_2 1: enable energy detect power-down mode. 0: disable energy detect power-down mode. pins. This allows the default operation of the PHY to be configured in unmanaged applications. 1: enable periodic transmission of the pulse while in energy detect power-down mode. 0: disable periodic transmission of the pulse while in energy detect power-down mode. 1: PHY is in energy detect power-down mode. 0: PHY is not in energy detect power-down mode. This register provides access to various PHY control registers, for control of clocking, group MDIO access, and autonegotiation. Table 47. Bit Descriptions for PHY_CTRL_2 10 DN_SPEED_TO_10_EN Setting this bit enables downspeed to 10BASE-T. Note that autonegotiation must also be enabled. (assuming this speed has been advertised) if necessary. 1: enable downspeed to 10BASE-T.

Table 47. Bit Descriptions for PHY_CTRL_2 (Continued) 0: disable downspeed to 10BASE-T. This register provides access to PHY control register bits for link enable and autonegotiation controls. Table 48. Bit Descriptions for PHY_CTRL_3 attempt to bring up links. The standby state can be used to run diagnostics, including cable diagnostics. link 5 times (4 retries) before downspeeding. The interrupt mask register allows interrupts to be masked or unmasked. Table 49. Bit Descriptions for IRQ_MASK 1: enable cable diagnostics interrupt. 0: disable cable diagnostics interrupt. 1: enable MDIO synchronization lost interrupt. 0: disable MDIO synchronization lost interrupt. 1: enable autonegotiation status changed interrupt. 0: disable autonegotiation status changed interrupt. 1: enabled frame checker/generator interrupt. 0: disable frame checker/generator interrupt.

Table 49. Bit Descriptions for IRQ_MASK (Continued) 1: enable autonegotiation page received interrupt. 0: disable autonegotiation page received interrupt. 1: enable idle error counter saturated interrupt. 0: disable idle error counter saturated interrupt. 1: enable MAC interface FIFO overflow/underflow interrupt. 0: disable MAC interface FIFO overflow/underflow interrupt. 1: enable receive status changed interrupt. 0: disable receive status changed interrupt. 1: enable link status changed interrupt. 0: disable link status changed interrupt. 1: enable speed changed interrupt. 0: disable speed changed interrupt. 1: enable the hardware interrupt pin, INT_N. 0: disable the hardware interrupt pin, INT_N. with enabled interrupts are considered when generating the IRQ_PENDING indication. Table 50. Bit Descriptions for IRQ_STATUS

Table 50. Bit Descriptions for IRQ_STATUS (Continued) it latches high until it is unlatched by reading. since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. 0 IRQ_PENDING If the interrupt pending status bit is 1, this indicates that an interrupt has occurred and is pending. Note that when this bit goes high, it latches high until it is unlatched by reading. This register provides access to various PHY status registers. Table 51. Bit Descriptions for PHY_STATUS_1 be used to run diagnostics, including cable diagnostics.

14 Reserved Reserved 0x0 R

PAR_DET_FLT_STAT bit does not clear PAR_DET_FLT. 011: speed resolved to 100BASE-TX full duplex. 010: speed resolved to 100BASE-TX half duplex. 001: speed resolved to 10BASE-T full duplex. 000: speed resolved to 10BASE-T half duplex.

Table 51. Bit Descriptions for PHY_STATUS_1 (Continued) information as LP_PAUSE_ABLE. duplex links. This bit provides the same information as LP_APAUSE_ABLE. This register provides access to various PHY LED control register bits. Table 52. Bit Descriptions for LED_CTRL_1 1: enable extended configuration set for LED_0 pin. 0: disable extended configuration set for LED_0 pin. register, Address 0x001D, Bits[13:8]). The default blink is a 0.2 sec on and 0.2 sec off pattern. LED_PUL_STR_DUR register (Address 0xBC00, Bits[5:0]). too short to cause an LED to light.

This register provides access to various PHY LED control register bits. Table 53. Bit Descriptions for LED_CTRL_2 if link up and blink on activity). 11111: on if 10BASE-Te link, blink if 100BASE-TX link. 11110: on if 10BASE-Te link. 11101: on if 100BASE-TX link, blink if 10BASE-Te link. 11011: blink if 10BASE-Te link. 10011: on if 100BASE-TX link, blink on activity. 10010: on if 10BASE-Te link, blink on activity. 10000: on if 10BASE-Te or 100BASE-TX link. 01100: on if full duplex link, blink on collision. 01011: on if link, blink if receiving. 01010: on if link, blink on activity. 01000: on if full duplex link. 00111: on if activity (transmitting or receiving).

This register provides access to various PHY LED control register bits. Table 54. Bit Descriptions for LED_CTRL_3 LED_PAT, LED_PAT_TICK_DUR, and LED_PAT_PAUSE_DUR bit fields. 00: read/write access to LED_0 blink pattern registers. default blink is a 0.5 sec on and 0.5 sec off pattern. blink is a 0.5 sec on and 0.5 sec off pattern. This register provides access to various PHY status register bits. Table 55. Bit Descriptions for PHY_STATUS_2 MMD Register Address 3.20. This register is used to indicate the capability of the PCS to support EEE functions for each PHY type. Table 56. Bit Descriptions for EEE_CAPABILITY 1: EEE is supported for 10GBASE-KR. 0: EEE is not supported for 10GBASE-KR.

Table 56. Bit Descriptions for EEE_CAPABILITY (Continued) 1: EEE is supported for 10GBASE-KX4. 0: EEE is not supported for 10GBASE-KX4. 1: EEE is supported for 1000BASE-KX. 0: EEE is not supported for 1000BASE-KX. 1: EEE is supported for 10GBASE-T. 0: EEE is not supported for 10GBASE-T. 1: EEE is supported for 1000BASE-T. 0: EEE is not supported for 1000BASE-T. 1: EEE is supported for 100BASE-TX. 0: EEE is not supported for 100BASE-TX. 0x0000 except where the hardware configuration pins are set to enable EEE. In this case, the reset value is 0x0006. Table 57. Bit Descriptions for EEE_ADV 1: advertise that the 10GBASE-KR has EEE capability. 0: do not advertise that the 10GBASE-KR has EEE capability. 1: advertise that the 10GBASE-KX4 has EEE capability. 0: do not advertise that the 10GBASE-KX4 has EEE capability. 1: advertise that the 1000BASE-KX has EEE capability. 0: do not advertise that the 1000BASE-KX has EEE capability. 1: advertise that the 10GBASE-T has EEE capability. 0: do not advertise that the 10GBASE-T has EEE capability. 1: advertise that the 1000BASE-T has EEE capability. 0: do not advertise that the 1000BASE-T has EEE capability. disabled, the default value is 1'b0. 1: advertise that the 100BASE-TX has EEE capability.

Table 57. Bit Descriptions for EEE_ADV (Continued) 0: do not advertise that the 100BASE-TX has EEE capability. is at MMD Register Address 7.61. This register reflects the EEE advertisement of the link partner during autonegotiation. Table 58. Bit Descriptions for EEE_LP_ABILITY 1: link partner is advertising EEE capability for 10GBASE-KR. 0: link partner is not advertising EEE capability for 10GBASE-KR. 1: link partner is advertising EEE capability for 10GBASE-KX4. 0: link partner is not advertising EEE capability for 10GBASE-KX4. 1: link partner is advertising EEE capability for 1000BASE-KX. 0: link partner is not advertising EEE capability for 1000BASE-KX. 1: link partner is advertising EEE capability for 10GBASE-T. 0: link partner is not advertising EEE capability for 10GBASE-T. 1: link partner is advertising EEE capability for 1000BASE-T. 0: link partner is not advertising EEE capability for 1000BASE-T. 1: link partner is advertising EEE capability for 100BASE-TX. 0: link partner is not advertising EEE capability for 100BASE-TX. This register indicates whether or not the resolved technology after the link has been established is EEE capable. Table 59. Bit Descriptions for EEE_RSLVD 1: resolved technology is EEE capable.

This register is an indication of signal quality and is a measure of the mean square error on Dimension A. Table 60. Bit Descriptions for MSE_A This register controls the enables for the enhanced link detection function. This is early detection and indication of link loss. Table 61. Bit Descriptions for FLD_EN 1 FLD_SLCR_IN_INVLD_B_100_EN Enhanced link detection PMA slicer input invalid level detection enable for 100BASE-TX. This register is the latched status for the enhanced link detection function. This bit is latched until the start of the next link-up, when it is cleared. Table 62. Bit Descriptions for FLD_STAT_LAT Register Address 3.0, Bit 10.

Table 63. Bit Descriptions for RX_MII_CLK_STOP_EN 10 RX_MII_CLK_STOP_ENIf this bit is set, the PHY may stop the receive MII clock while it is signaling low power enable (LPI). Otherwise, it keeps the clock active. 1: the PHY may stop the clock during LPI. which, in the IEEE standard, is at MMD Register Address 3.1, Bits[11:8] and Bit 6. Table 64. Bit Descriptions for PCS_STATUS_1 until it is unlatched by reading. 1: transmit PCS has received LPI. until it is unlatched by reading. 1: receive PCS has received LPI. 1: transmit PCS is currently receiving LPI. 0: PCS is not currently receiving LPI. 1: receive PCS is currently receiving LPI. 0: PCS is not currently receiving LPI. 1: the MAC may stop the clock during LPI. frame checker frame and error counter registers count these events.

Table 65. Bit Descriptions for FC_EN status can be read via the FC_FG_IRQ_STAT bit (IRQ_STATUS register, Address 0x0019). Table 66. Bit Descriptions for FC_IRQ_EN used to check the received data after it is looped back at the MAC interface. Table 67. Bit Descriptions for FC_TX_SEL 1: check frames from the MAC interface to be transmitted by the PHY. 0: check frames received by the PHY from the remote end. This register specifies the maximum frame size. Frames longer than this size are counted as oversized frames. Table 68. Bit Descriptions for FC_MAX_FRM_SIZE oversized frames. Note that this frame length excludes the preamble and start frame delimiter. RX_ERR_CNT is read so that the error count and receive frame count are synchronized.

Table 69. Bit Descriptions for FC_FRM_CNT_H RX_ERR_CNT is read so that the error count and receive frame count are synchronized. Table 70. Bit Descriptions for FC_FRM_CNT_L This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status. ensures that the frame length error count and receive frame count are synchronized. Table 71. Bit Descriptions for FC_LEN_ERR_CNT ensures that the frame alignment error count and receive frame count are synchronized. Table 72. Bit Descriptions for FC_ALGN_ERR_CNT This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set. that the symbol error count and receive frame count are synchronized. Table 73. Bit Descriptions for FC_SYMB_ERR_CNT

error count and receive frame count are synchronized. Table 74. Bit Descriptions for FC_OSZ_CNT latched, which ensures that the undersized frame error count and receive frame count are synchronized. Table 75. Bit Descriptions for FC_USZ_CNT odd nibble frame counter register is latched, which ensures that the odd nibble frame count and receive frame count are synchronized. Table 76. Bit Descriptions for FC_ODD_CNT preamble packet counter register is latched, which ensures that the odd preamble packet count and receive frame count are synchronized. Table 77. Bit Descriptions for FC_ODD_PRE_CNT

register is latched, which ensures that the dribble bits frame count and receive frame count are synchronized. Table 78. Bit Descriptions for FC_DRIBBLE_BITS_CNT This register is a latched copy of the false carrier events counter register. This is a count of the number of times the bad SSD state is entered. ensures that the false carrier events count and receive frame count are synchronized. Table 79. Bit Descriptions for FC_FALSE_CARRIER_CNT (PHY_CTRL_1 register, Address 0x0012, Bit 2). Table 80. Bit Descriptions for FG_EN This register provides frame generator control and restart functions. Table 81. Bit Descriptions for FG_CNTRL_RSTRT 101: data field decrementing from 255 (decimal) to 0. 100: alternative 0x55 in the MAC client data frame field.

Table 81. Bit Descriptions for FG_CNTRL_RSTRT (Continued) 011: all ones in the MAC client data frame field. 010: all zeros in the MAC client data frame field. 001: random number in the MAC client data frame field. 000: no frames after completion of current frame. frames generated is specified by the FG_NFRM_H register and FG_NFRM_L register (Address 0x941C and Address 0x941D). Table 82. Bit Descriptions for FG_CONT_MODE_EN interrupt status can be read via the IRQ_STATUS register, FC_FG_IRQ_STAT bit (Address 0x0019, Bit 7). Table 83. Bit Descriptions for FG_IRQ_EN programmed number of frames. 1: enable the frame generator interrupt. 0: disable the frame generator interrupt. Table 84. Bit Descriptions for FG_FRM_LEN

This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator. Table 85. Bit Descriptions for FG_IFG_LEN Table 86. Bit Descriptions for FG_NFRM_H Table 87. Bit Descriptions for FG_NFRM_L register and FG_NFRM_L register (Address 0x941C and Address 0x941D, respectively). Table 88. Bit Descriptions for FG_DONE high until it is unlatched by reading. When set, the transmit FIFO is configured for synchronous operation to minimize latency.

Table 89. Bit Descriptions for FIFO_SYNC This register controls the start of packet (SOP) detection for IEEE 1588 time stamp controls. Table 90. Bit Descriptions for SOP_CTRL SOP_N_8_CYCM_1 bit field. Otherwise, the SOP indications are set for the duration of the frame. indication variation, the detection is done after the transmit FIFO for modes in which the transmit FIFO is used. This register controls the receive side SOP detection delay. Table 91. Bit Descriptions for SOP_RX_DEL frames SOP indication for 10BASE-T links. frames SOP indication for 100BASE-TX links. This register controls the transmit side SOP detection delay.

Table 92. Bit Descriptions for SOP_TX_DEL on the MDI pins, set this register to 5'd20. set on the MDI pins, set this register to 4'd0. FIFO depth in bytes in MII modes. Table 93. Bit Descriptions for DPTH_MII_BYTE standard is at MMD Register Address 3.22. Table 94. Bit Descriptions for LPI_WAKE_ERR_CNT time required. This field self clears upon reading. When set, this register enables 10BASE-Te operation. 10BASE-Te is a variant of 10BASE-T that transmits at a lower voltage level. Table 95. Bit Descriptions for B_10_E_EN variant of 10BASE-T that transmits at a lower voltage level.

This register provides the ability to transmit a 10BASE-T test signal. Table 96. Bit Descriptions for B_10_TX_TST_MODE 100: transmit 5 MHz square wave on Dimension 1. 011: transmit 5 MHz square wave on Dimension 0. 010: transmit 10 MHz square wave on Dimension 1. 001: transmit 10 MHz square wave on Dimension 0. 000: 10BASE-T test mode disabled. This register provides the ability to transmit a 100BASE-TX test signal. Table 97. Bit Descriptions for B_100_TX_TST_MODE 100: transmit MLT3 test waveform, 112 ns dwell time on Dimension 1. 011: transmit MLT3 test waveform, 112 ns dwell time on Dimension 0. 010: transmit MLT3 test waveform, 16 ns dwell time on Dimension 1. 001: transmit MLT3 test waveform, 16 ns dwell time on Dimension 0. 000: 100BASE-TX test mode disabled. This register provides the ability to configure for the lowest common-mode impedance on the receive pair for 100BASE-TX.

Table 98. Bit Descriptions for B_100_ZPTM_EN_DIMRX 0 B_100_ZPTM_EN_DIMRXApplies to 100BASE-TX. Set to 1 to configure for normal termination on the receive dimension, lowest power (default). Set to 0 to configure for lowest common-mode impedance. This register is used to start the automated running of cable diagnostics and to return results in the cable diagnostic results registers. Table 99. Bit Descriptions for CDIAG_RUN bit (PHY_CTRL_3 register, Address 0x0017, Bit 13). This bit self clears when the cable diagnostics are completed. This register allows the checking of cross pair faults in the cable diagnostics to be disabled. Table 100. Bit Descriptions for CDIAG_XPAIR_DIS 1: disable cross pair fault checking. 0: enable cross pair fault checking. This register provides cable diagnostics results for Pair 0. Table 101. Bit Descriptions for CdiagDtldRslts0 Pair 0 during cable diagnostics.

Table 101. Bit Descriptions for CdiagDtldRslts0 (Continued) This register provides cable diagnostics results for Pair 1. Table 102. Bit Descriptions for CDIAG_DTLD_RSLTS_1 This register provides the distance to the first fault on Pair 0. Table 103. Bit Descriptions for CDIAG_FLT_DIST_0 This register provides the distance to the first fault on Pair 1. Table 104. Bit Descriptions for CDIAG_FLT_DIST_1

Table 105. Bit Descriptions for CDIAG_CBL_LEN_EST LED_PUL_STR_DUR register determines the LED pulse stretching duration. Table 106. Bit Descriptions for LED_PUL_STR_DUR specified by 8 to determine the duration in milliseconds. on LED_0, for Mode 1 and Mode 2, this register returns 0, while for Mode 3 and Mode 4, default to 1. Table 107. Bit Descriptions for LED_A_INV_EN bit is configurable via the hardware configuration pins. specified under Clause 45, these registers can be accessed using Clause 22 access via Register 0x0010 and Register 0x0011. enabled, all speeds advertised, and the ADIN1200 is not configured to enter software power-down after reset. Table 108. Subsystem Register Summary

Table 108. Subsystem Register Summary (Continued) The soft reset register is used to reset the subsystem. Table 109. Bit Descriptions for GE_SFT_RST hardware configuration pin settings are reloaded into the corresponding management registers. In the event of a software reset using the GE_SFT_RST bit, the subsystem behavior depends on the setting of this register bit. Table 110. Bit Descriptions for GE_SFT_RST_CFG_EN on the setting of the GE_SFT_RST_CFG_EN bit. tion pin settings from the chip during the software reset sequence. reloaded into the corresponding management registers.

This register is used to control whether or not the interrupt on INT_N hardware pin is asserted in response to various events. Table 111. Bit Descriptions for GE_IRQ_EN This register is used to check and clear the interrupt on INT_N hardware pin after a hardware reset. Table 112. Bit Descriptions for GE_IRQ_LAT This register allows the subsystem output clock configuration to be controlled. Table 113. Bit Descriptions for GE_CLK_CFG chip to drive the digital recovered heartbeat clock at the GP_CLK pin. to drive the digital free running heartbeat clock at the GP_CLK pin. (having been processed through the digital block).

This register allows the MAC interface RGMII configuration to be controlled. Table 114. Bit Descriptions for GE_RGMII_CFG 1: enable low RGMII latency for 100BASE-TX. 0: disable low RGMII latency for 100BASE-TX. 1: enable low RGMII latency for 10BASE-T. 0: disable low RGMII latency for 10BASE-T. (DLL) unit delay (tU = 200 ps). of the PHY to be configured in unmanaged applications. 1: enable receive clock internal 2 ns delay in RGMII mode. 0: disable receive clock internal 2 ns delay in RGMII mode. of the PHY to be configured in unmanaged applications. 1: enable transmit clock internal 2 ns delay in RGMII mode. 0: disable transmit clock internal 2 ns delay in RGMII mode. to be configured in unmanaged applications.

This register allows the MAC interface RMII configuration to be controlled. Table 115. Bit Descriptions for GE_RMII_CFG start of a frame. This bit allows connecting the RMII receive CRS_DV to the RMII TX_EN signal. something that it is not supported in the RMII specification. is not supported in the RMII specification. RMII interface must be configured from the hardware configuration pins and not from software. link detection 100BASE-TX enable register bit in the PHY only change after a PHY software reset. Table 116. Bit Descriptions for GE_PHY_BASE_CFG

Table 116. Bit Descriptions for GE_PHY_BASE_CFG (Continued) sent to the MAC. Setting this bit causes the GE subsystem to regenerate a full 10BASE-T preamble. Table 117. Bit Descriptions for GE_B10_REGEN_PRE be left at the default value of 0x0 for general use and set to 0x1 for media converter applications. This register allows the characteristics of the RGMII I/O cells to be controlled. Table 118. Bit Descriptions for GE_RGMII_IO_CNTRL correspond to higher drive current. This register allows the characteristics of the clock I/O cells to be controlled. Table 119. Bit Descriptions for GE_CLK_IO_CNTRL correspond to higher drive current. This register allows the link status output signal on the LINK_ST pin to be inverted, meaning that link up is indicated by setting LINK_ST low.

Table 120. Bit Descriptions for GE_LNK_STAT_INV_EN that link up is indicated by setting LINK_ST low. This register allows the default function of the GP_CLK pin to be overridden. Table 121. Bit Descriptions for GE_IO_GP_CLK_OR_CNTRL 111: PHY clock selected by the registers in the GE_CLK_CFG register. 011: receive start of packet indication. 010: transmit start of packet indication. MAC interface. In all other cases, the default function is GP_CLK. This register allows the default function of the LINK_ST pin to be overridden. Table 122. Bit Descriptions for GE_IO_GP_OUT_OR_CNTRL 011: receive start of packet indication. 010: transmit start of packet indication. 000: default function, link status. This register allows the default function of the INT_N pin to be overridden.

Table 123. Bit Descriptions for GE_IO_INT_N_OR_CNTRL 011: receive start of packet indication. 010: transmit start of packet indication. This register allows the default function of the LED_0 pin to be overridden. Table 124. Bit Descriptions for GE_IO_LED_A_OR_CNTRL 0011: receive start of packet indication. 0010: transmit start of packet indication. function is TX_ER. In all other cases, the default is LED_0.

PCB LAYOUT RECOMMENDATIONS analog.com Rev. B | 87 of 88 POWER AND GROUND PLANES From a PCB layout point of view, it is important to place the decoupling capacitors as close as possible to the power and GND pins to minimize the inductance. Magnetics Module Grounding A split ground plane under the transformer minimizes noise cou- pling across the transformer and between adjacent coils within. Ensure a physical separation of the ground planes underneath the transformer. Make the width of this separation at least 100 mil. RJ45 Module Grounding For optimal EMC performance, it is recommended to use a metal shielded RJ45 connector with the shield connected to chassis ground. There must be an isolation gap between the chassis ground and the PHY IC ground with consistent isolation across all layers. LAYOUT GUIDELINES FOR LFCSP PACKAGE The LFCSP package has an exposed pad that must be soldered to a metal plate on the PCB for mechanical reasons and to GND. The package also has two keepout areas to the top and bottom of the exposed pad. No PCB traces or vias can be used in these areas. For thermal impedance performance, use of a JEDEC 2S2P board with a 4 × 4 array of thermal vias beneath the exposed GND pad is required.

©2019-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. B | 88 of 88 Package Drawing (Option) Package Type Package Description CP-32-31 LFCSP 32-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: September 18, 2023 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADIN1200BCP32Z -40°C to +85°C 32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP) CP-32-31 ADIN1200BCP32Z-R7 -40°C to +85°C 32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)Reel, 1500 CP-32-31 ADIN1200CCP32Z -40°C to +105°C 32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP) CP-32-31 ADIN1200CCP32Z-R7 -40°C to +105°C 32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)Reel, 1500 CP-32-31 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-ADIN1200FMCZ Evaluation Board 1 Z = RoHS Compliant Part.