ADIN1100

ADIN1100 (Rev.C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 85

Technical content

Robust, Industrial, Low Power 10BASE-T1L PHY Rev. C DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►10BASE-T1L IEEE Standard 802.3cg-2019 compliant ►Cable reach up to 1700 m with 1.0 V p-p and 2.4 V p-p ►Supports 1.0 V p-p and 2.4 V p-p transmit levels ►MDI polarity detection and correction ►Supports intrinsic safety applications ►Low power consumption: 39 mW (dual supply, 1.0 V p-p) ►Diagnostics ►Cable fault detection with TDR ►Link quality indicator with MSE ►Frame generator and checker ►Multiple loopback modes ►IEEE test mode support ►MII, RMII, and RGMII MAC interfaces ►MDIO management interface ►Unmanaged configuration using pin strapping ►25 MHz crystal or external clock input (50 MHz for RMII) ►Single or dual supply with 1.8 V or 3.3 V operation ►3.3 V, 2.5 V, or 1.8 V MAC interface VDDIO supply ►Integrated power supply monitoring and POR ►EMC test standards ►IEC 61000-4-4 EFT (±4 kV) ►IEC 61000-4-2 ESD (±4 kV contact discharge) ►IEC 61000-4-2 ESD (±8 kV air discharge) ►IEC 61000-4-5 surge (±4 kV) ►IEC 61000-4-6 conducted immunity (10 V/m) ►IEC 61000-4-3 radiated immunity (Class A) ►EN 55032 radiated emissions (Class B) ►Small package: 40-lead, 6 mm × 6 mm LFCSP ►Temperature range ►Industrial: −40°C to +85°C ►Extended: −40°C to +105°C

APPLICATIONS

►Process control ►Factory automation ►Building automation ►Field instruments and switches FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADIN1100 is a low power, single port, 10BASE-T1L transceiver designed for industrial Ethernet applications and is compliant with the IEEE® 802.3cg-2019™ Ethernet standard for long reach 10 Mbps single pair Ethernet (SPE). The ADIN1100 integrates an Ethernet PHY core with all the associated analog circuitry, input and output clock buffering, the management interface control register and subsystem registers, as well as the MAC interface and control logic to manage the reset, clock control, and pin configuration. The ADIN1100 supports cable reach of up to 1700 meters with autonegotiation enabled and has ultra low power consumption of 39 mW. The PHY core supports the 1.0 V p-p operating mode and the 2.4 V p-p operating mode defined in the IEEE 802.3cg standard and can operate from a single power supply rail of 1.8 V or 3.3 V, with the lower voltage option supporting the 1.0 V p-p transmit voltage level. The ADIN1100 has an integrated voltage supply monitoring circuit and power-on reset (POR) circuitry to improve system level robust- ness. The MDIO interface is a 2-wire serial interface for communication between a host processor or MAC and the ADIN1100, thereby allowing access to control and status information in the PHY core management registers. This interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.

analog.com Rev. C | 2 of 85 Electromagnetic Compatibility (EMC) and

REVISION HISTORY

1/2025—Rev. B to Rev. C

analog.com Rev. C | 3 of 85 8/2023—Rev. A to Rev. B 1/2023—Rev. 0 to Rev. A

analog.com Rev. C | 4 of 85 Added External 25 MHz Clock Input for MII and RGMII Modes Section, Figure 24, and Table 27; 9/2021—Revision 0: Initial Version

−40°C to +105°C, unless otherwise noted. Table 1. General Specifications

50 MHz Reduced media independent interface

Table 1. General Specifications (Continued) 1 Load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics. 2 RP and CP are the values of the equivalent parallel RC circuit to ac ground (RP||CP), modeling the driving point impedance of the XTAL_I/CLK_IN pin. Table 2. 10BASE-T1L Specifications

Table 2. 10BASE-T1L Specifications (Continued)

TA = 25°C, unless otherwise noted.

1 See the Pin Configuration and Function Descriptions section for the full list of

ing conditions for extended periods may affect product reliability. Table 6. Thermal Resistance circuit board for surface-mount packages.

2 Test Condition 1: thermal impedance simulated values are based on a JE-

DEC 2S2P thermal test board with thermal vias. See JEDEC JESD51. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 7. ADIN1100, 40-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 4. Pin Configuration Table 8. Pin Function Descriptions 8 XTAL_I/CLK_IN N/A Input for Crystal (XTAL_I). Single-Ended 25 MHz Reference Clock or 50 MHz Clock Input for RMII (CLK_IN). drain and requires a 1.5 kΩ pull-up resistor to VDDIO. 27 MDC PD Management Data Clock Input up to 2.5 MHz. 12 TXN N/A Transmit Negative Pin. 13 RXN N/A Receive Negative Pin. 14 RXP N/A Receive Positive Pin. 15 TXP N/A Transmit Positive Pin.

Table 8. Pin Function Descriptions (Continued) 1 TXD_2 PD Reduced Gigabit Media Independent Interface (RGMII)/MII Transmit Data 2 Input. See the MAC Interface section. 2 TXD_3/MEDIA_CNV PD RGMII/MII Transmit Data 3 Input (TXD_3). See the MAC Interface section. Media Converter Hardware Configuration Pin (MEDIA_CNV). 28 RXD_3/PHYAD_1 PD RGMII/MII Receive Data 3 Output (RXD_3). See the MAC Interface section. PHY Address Hardware Configuration Pin 1 (PHYAD_1). 29 RXD_2/PHYAD_0 PD RGMII/MII Receive Data 2 Output (RXD_2). See the MAC Interface section. PHY Address Hardware Configuration Pin 0 (PHYAD_0). 30 RXD_1/MS_SEL PD RGMII/RMII/MII Receive Data 1 Output (RXD_1). See the MAC Interface section. for prefer follower selection. See Table 18. 31 RXD_0/TX2P4_EN PD RGMII/RMII/MII Receive Data 0 Output (RXD_0). See the MAC Interface section. 32 RX_CLK/RXC/MACIF_SEL0PD 2.5 MHz MII Receive Clock Output (RX_CLK). 2.5 MHz RGMII Receive Clock Output (RXC). MAC Interface Selection section. RX_DV and RX_ER signals using both edges of RXC. the PHY to enter software power-down mode after power-up or reset. See Table 17. RX_ER indicates that the PHY has detected a receive error. 36 TX_ER PD RMII/MII Mode Transmit Error Input Detection from the MAC to the PHY. indicates that transmission data is available on the TXD_x lines. TX_EN and RX_ER signals using both edges of TXC. 38 TX_CLK/TXC PD 2.5 MHz MII Transmit Clock Output (TX_CLK). 2.5 MHz RGMII Transmit Clock Input (TXC). 39 TXD_0 PD RGMII/RMII/MII Transmit Data 0 Input. See the MAC Interface section. 40 TXD_1 PD RGMII/RMII/MII Transmit Data 1 Input. See the MAC Interface section. and blink when there is activity. See the Status LEDs section. established. LINK_ST is active high. PHY Address Hardware Configuration Pin 2 (PHYAD_2). active low. By default, LED_1 is disabled. See the Status LEDs section.

rail can be supplied by 1.8 V to 3.3 V depending on the transmit level configuration. supported. If AVDD_H is 1.8 V, only 1.0 V p-p transmit operating mode is supported. Connect 0.1 μF and 0.01 μF capacitors to GND as close as possible to this pin. 0.01 μF capacitors to GND as close as possible to this pin. as close as possible to this pin. µF to ground as close as possible to this pin. and 0.01 μF capacitors to GND as close as possible to the pin. 10, 11, 18, 21 DNC N/A Do Not Connect. These pins must be left open circuit. 1 Where a pin is shared between a functional signal and a hardware configuration pin signal, the hardware configuration pin signal is listed last.

Figure 5. Power vs. Temperature, 1.8 V Single Supply, Internal LDO Circuit, Figure 6. Power vs. Temperature, 3.3 V Single Supply, Internal LDO Circuit, Figure 7. Power vs. Temperature, AVDD_H = 3.3 V, AVDD_L = 3.3 V, VDDIO =

1.8 V, Internal LDO Circuit, 10BASE-T1L Mode

Figure 8. Power vs. Temperature, AVDD_H = 3.3 V, VDDIO = 3.3 V, AVDD_L = Figure 9. Power vs. Temperature, AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V,

long reach, 10 Mbps single pair Ethernet. end (AFE) circuitry in the ADIN1100. supplies mode for lower power consumption. external 1.1 V supply for lower power consumption. nected directly to the AVDD_L rail or to an external power rail. application circuits that can be used as reference. in the Single-Supply Configuration section. ADIN1100 in this mode supports intrinsic safety applications. Ethernet environments with higher noise levels. hardware configuration pins. different clock and pin mapping requirements. available on the TXD_3 to TXD_0 signal lines. Figure 10. MII MAC PHY Interface Signals

leader through the RXD_1/MS_SEL hardware configuration pin. based on the MS_SEL hardware configuration pin signal level. selection are configured for the linked devices. tiation control register (AN_CONTROL). sequence timers and DME pages timing related to autonegotiation. strongly recommended to always keep it enabled. Table 9. AN_ADV_B10L_TX_LVL_HI_ABL Settings Table 10. AN_ADV_B10L_TX_LVL_HI_REQ Settings ration pin signal to enable the high voltage request advertisement.

is operation at the 1.0 V p-p transmit level. the 2.4 V p-p transmit level. irrespective of the setting that the remote PHY advertises. Table 11. Determination of Transmit Level by Autonegotiation

follower, prefer leader, or prefer follower. status and can be overridden by software via the MDIO interface. The ADIN1100 PHY can be forced to operate as a leader/follower. a PHY with a preferred setting. Table 12. Determination of Leader/Follower by Autonegotiation

0 X 1 0 Leader Follower

0 X 1 1 Follower Leader

Figure 15. Recommended MDI Circuitry with Power Coupling for the ler or external MAC chip using the INT pin. Interrupt Mask Register section). Subsystem Interrupt Status Register section). System Interrupt Mask Register section). (CRSM_IRQ_STATUS reserved bits read as 1). interface output pins are driven to a low state. rising threshold value and the power is considered good. latched, and the I/O pins are configured to their functional mode.

analog.com Rev. C | 21 of 85 The CLK25_REF clock output stays low while the RESET pin is asserted low and remains low for another 70 ms (maximum) after the RESET pin is deasserted. Software Reset A full chip software reset is initiated by setting the software reset bit (CRSM_SFT_RST). When this bit is set, the chip fully initializes, almost equivalent to a hardware reset except that it does not go through the voltage supply validation sequence. The I/O pins are held in tristate mode, the hardware configuration pins are latched, and then the I/O pins are configured to their functional mode. The crystal oscillator circuit is enabled, and after the crystal has started up and stabilized, the PLL is enabled. Approximately 10 ms (maximum) after setting the CRSM_SFT_RST bit, the internal logic is released from reset and all the management interface registers are accessible. The system ready bit (CRSM_SYS_RDY) indicates that the start-up sequence is complete and the system is ready for normal operation. The CLK25_REF clock output remains low for 25 ms (maximum) following a software reset. PHY Subsystem Reset A PHY subsystem reset is initiated on the ADIN1100 by setting the PHY subsystem reset register bit (CRSM_PHY_SUBSYS_RST) to 1. The reset is applied for typically 1.2 µs, and then this bit self clears. All of the PHY digital circuitry is reset, and any available ac- tive link drops. The PHY subsystem reset does not alter the values of the management registers, which remain accessible throughout the sequence. The subsystem reset is a short reset and can be used to put the device into a known state while retaining the internal register contents. MAC Interface Reset A MAC interface reset is initiated on the ADIN1100 by setting the PHY MAC interface reset register bit (CRSM_MAC_IF_RST) to 1. The reset is applied for typically 1.2 µs, and then this bit self clears. A reset sequence is provided to the ADIN1100 MAC interface, but without dropping the available active link. This reset interrupts any packet transmission or reception on the MAC interface, but does not drop an existing active link nor prevent a link from being established. The MAC interface reset does not alter the values of the management registers, which remain accessible throughout the sequence. STATUS LEDS Overview The LED_0 and LED_1 is only available in ADIN1100 pins can be used to connect external LEDs to indicate the ADIN1100 link status and transmit or receive activity. The activity assigned to each LED is configurable through LED_CNTRL (see the LED Control Register section). The LED pins are suitable for ultra low power LEDs. The maximum output current for the LED_0 and LED_1 pins is 8 mA with a VDDIO = 3.3 V. For higher LED power requirements, the use of an external transistor is recommended, as described in the Transistor Controlled LED section. The LED_x pins can also be connected to a host microcontroller GPIO (configured as a pulse-width modulated input or hardware interrupt). This configuration can be useful in applications where the user interface must be fully handled by an external host controller (for example, an external LED module or display). If the LED_0 and LED_1 pins are directly connected to a host controller, it is recommended to place a low value resistance in series between the ADIN1100 LED_x pins and the host controller to avoid any potential current surge. The resistor value must be defined based on host controller capabilities and the ADIN1100 LED_x pin output current capabilities listed in Table 1. LED Pin Multiplexing For the LED_1 pin only, an internal multiplexer must be configured to enable the LED_1 signal on the pin. LED_1 is disabled by default and can be enabled using the DIGIO_LED1_PINMUX bits (see the Pin Mux Configuration 1 Register section). The LED_0 pin does not need multiplexing. LED Polarity The LED_0 and LED_1 pins can be configured to support various LED circuit polarities through the LED polarity mode feature (see the LED Polarity Register section). Three polarity modes are availa- ble for each LED, as follows: ►Autosense (default) ►Active high ►Active low In autosense mode, the ADIN1100 automatically senses the pin at power-up or reset to select the appropriate polarity configuration. In active high mode, the ADIN1100 is configured to drive the LED from the anode side. In active low mode, the ADIN1100 is configured to drive the LED from the cathode side. Example circuits are described in the LED Circuit Examples sec- tion. LED Function LED_0 and LED_1 can be configured to display various activities of the ADIN1100 using the LED function feature. The LED function

bits (see the LED Control Register section). TION are not available in LED Mode 2. See Table 13 for the configuration options of the LED_x pins. Table 13. LED_x Pins Configuration Summary

1 Register section)

1 The 7, 8, 9, and 10 (decimal) settings in the LEDx_FUNCTION bits are not available in Mode 2.

analog.com Rev. C | 23 of 85 LINK STATUS PIN Overview The link status pin (LINK_ST/PHYAD_2) is asserted high when the link status bit (AN_LINK_STATUS) is asserted and indicates that the link between the ADIN1100 and its link partner is active. The LINK_ST/PHYAD_2 pin has a weak internal pull-down resis- tor. The pin is also used as a hardware configuration pin signal (PHYAD_2) during power-up, hardware reset, or software reset. Typical Use The link status pin can be used to connect an external LED or can be connected to a host microcontroller GPIO (configured as a pulse-width modulated input or hardware interrupt). By default, the LINK_ST signal is active high and can be config- ured as either active high or low using the link status polarity bit (DGIO_LINK_ST_POLARITY). See the Pin Mux Configuration 1 Register section. The link status pin is not intended to source current. Use the circuit recommendation in the Transistor Controlled LED section as a reference to interface an LED on this pin. If the link status pin is directly connected to a host controller, it is recommended to place a low value resistance in series between the ADIN1100 link status pin and the host controller to avoid any potential current surge. The resistor value must be defined based on host controller capabilities. POWER-DOWN MODES The ADIN1100 supports two power-down modes. ►Hardware power-down ►Software power-down Hardware Power-Down Mode The hardware power-down mode can be used when no operation is required on the ADIN1100 and the power consumption needs to be minimized. The device enters hardware power-down mode when the RESET pin is asserted and held low. In this mode, all analog and digital circuits are disabled, the clocks are gated off, and all the I/O pins are held in tristate mode. In this mode, the ADIN1100 power consumption is equivalent to the internal circuit leakage. The internal registers are not accessible in this mode. Software Power-Down Mode The software power-down mode can be used to configure the ADIN1100 registers before bringing a link up. In this mode, the analog and digital circuits are in a low power state, and the PLL is active and can provide output clocks if configured to do so. Any signals exposed to the MDI pins (TXP, TXN, RXP, RXN) are ignored and any active link is dropped. The MAC interface output pins are asserted low and internal registers are accessible using the MDIO interface. The device can be configured to automatically enter software power-down mode after power-up, hardware reset, or software reset using the SWPD_EN hardware configuration pin signal. The ADIN1100 can also be instructed to enter software power-down mode by setting the software power-down bit (CRSM_SFT_PD). The software power-down status bit (CRSM_SFT_PD_RDY) indi- cates that the device is in software power-down mode. The ADIN1100 exits software power-down mode when the CRSM_SFT_PD bit is cleared. After exiting software power-down and if autonegotiation is completed, the device attempts to bring a link up.

tions with the use of the hardware configuration pins. configuration pins can then be used with their main pin function. These pins can be used in unmanaged or managed configuration. software control and an external host controller. hardware pins after power-up, hardware reset, or software reset. power-up, hardware reset, or software reset. can dynamically configure the device as required by the application. to active mode using the management interface. suggested external pin control. Table 14. Default Hardware Configuration Modes Table 15. Recommended Control for Hardware Configuration Pins 1 A low value series resistor is recommended. 2 External pull-down resistor is recommended. remote PHY via the MDI pins. MAC Interface Configuration Register section). RGMII device without any media configuration requirements.

Table 16. Media Converter Selection (Hardware Configuration)

0 Normal PHY operation

1 Media converter operation

power-down after reset enabled. where most of the ADIN1100 internal modules are turned off. CRSM_SFT_PD bit to 0 using the MDIO interface. Table 17. Software Power-Down (Hardware Configuration)

0 PHY in software power-down after reset

1 PHY not in software power-down after reset

RXD_1 signal and configures the default leader/follower selection. ware reset, the device is configured by default to prefer follower. software reset, the device is configured by default to prefer leader. The RXD_1/MS_SEL pin has a weak internal pull-down resistor. Thus, by default, the ADIN1100 is configured to prefer follower. which is used when autonegotiation is disabled. Table 18. Leader/Follower Selection (Hardware Configuration)

0 Prefer follower selection

1 Prefer leader selection

The RXD_0/TX2P4_EN pin has a weak internal pull-down resistor. p-p and 2.4 V p-p voltage levels. associated register cannot be changed through the MDIO interface. been hardware pin configured only for 1.0 V p-p.

Table 19. Transmit Amplitude Selection (Hardware Configuration) and the value of B10L_TX_LVL_HI_ABLE is set to 1. and the value of B10L_TX_LVL_HI_ABLE is set to 0. Table 20. B10L_TX_LVL_HI_ABLE Settings transmit level operating mode. Table 21. MAC Interface Selection (Hardware Configuration)

BRINGING UP 10BASE-T1L LINKS analog.com Rev. C | 27 of 85 The following sections provide some recommendations on how to bring a link up between the ADIN1100 and a remote link partner. The sections cover various configurations and some may not be rel- evant to the intended application. Refer to the Theory of Operation section for more detailed explanations. UNMANAGED PHY OPERATION For an unmanaged PHY where there is no control of the ADIN1100 over the management interface, the hardware configuration pins determine the operating mode. See the Hardware Configuration Pins section for more details on how to use the hardware configu- ration pins. The following sections describe the steps required to bring up a link in unmanaged applications. Set the PHY Address The PHY address can be selected by asserting the PHY ad- dress pins: RXD_2/PHYAD_0, RXD_3/PHYAD_1, and LINK_ST/ PHYAD_2. When it exits reset, the ADIN1100 starts autonegotiation and tries to bring up a link after autonegotiation completes. See the PHY Address Configuration section for details on how to use the address pins. Disable Software Power-Down Mode After Reset The software power-down mode must be disabled in unmanaged applications. Otherwise, the ADIN1100 remains in software power- down indefinitely. Assert the RX_DV/RX_CTL/SWPD_EN pin high during power-up and reset so that the PHY does not enter software power-down mode when it exits reset. See the Software Power-Down After Reset section for details on how to configure the software power-down after reset function. Leader/Follower Selection The RXD_1/MS_SEL pin is used to configure the PHY to advertise prefer follower or prefer leader. See the Leader/Follower Preference section for details on how to configure the leader/follower setting. Set Transmit Amplitude Level The RXD_0/TX2P4_EN pin configures the PHY to advertise the support of both 1.0 V p-p and 2.4 V p-p transmit level operation or to only advertise support of 1.0 V p-p transmit level operation. By default, the ADIN1100 is configured to support 1.0 V p-p and 2.4 V p-p transmit levels due to the internal pull-down resistor. Assert the relevant pin high or low to disable the support for the 2.4 V p-p transmit level. See the Transmit Amplitude section for details on how to configure the transmit amplitude level. Select the MAC Interface (RGMII/RMII/MII) The MAC interface type can be selected using the RX_CLK/RXC/ MACIF_SEL0 and RX_ER/MACIF_SEL1 pins. See the MAC Interface Selection for details on how to select the MAC interface. Enable the Media Converter Functionality Assert the TXD_3/MEDIA_CNV pin high if media converter function is required (RMII mode only). See the Media Converter section for details on how to enable the media converter functionality. MANAGED PHY OPERATION In a managed PHY application, a host controller such as a micro- controller is used to configure the ADIN1100 operation in software via the management interface (MDIO). Similar to the unmanaged PHY operation, the hardware configura- tion pins can be used to set up the controlled ADIN1100 (see the Unmanaged PHY Operation section for details). Alternatively, the hardware configuration pins can directly be controlled by the host (for example, GPIO) via an external pull-up or pull-down resistor or both. In managed applications, the software power-down after reset can be enabled. The ADIN1100 stays in software power-down mode until the software has configured the PHY to be active. When active, the PHY can then start autonegotiation and try to bring up a link. Power-Up and Reset Complete A typical way for software to verify that the device has completed the power-up and reset sequence and is available for normal operation is to read the management register that has the IEEE or- ganizationally unique identifier (OUI), model, and revision numbers. The value of this register is unique to each PHY vendor and is a nonzero value. If the device has not completed the power-up, the value does not read correctly. In legacy BASE-T PHYs, this value is at management interface Register Address 0x2 and Register Address 0x3. In the ADIN1100, the OUI, model number, and revision numbers can also be read at Device Address 0x1F Clause 45 only), Register Address 0x2, and Register Address 0x3 (Clause 22 and Clause 45). MMD1_DEV_ID1 contains the OUI, Bits[3:18] (see the Vendor Specific 1 MMD Identifier High Register section).

Vendor Specific 1 MMD Identifier Low Register section. Table 22. ADIN1100 Unique Identifier Values sequence is complete and the system is ready for normal operation. available using the management registers. tion is also used to match the transmit level between the two PHYs. strongly recommended to always keep Autonegotiation enabled. PHYs and is the fastest way to bring up a link. 1.8 V supply on the AVDD_H pins at very low power consumption. Transmit Level Mode Advertisement section for more details.

1.0 V p-p transmit level operation is required for intrinsically safe

bed in the Transmit Amplitude section. required on the AVDD_H pins). mit level that the link operates at. the transmit level that the link operates at. p-p transmit level operation is not advertised. V or 3.3 V for 1.0 V p-p transmit level operation. the ADIN1100 to support the 2.4 V p-p transmit level.

BRINGING UP 10BASE-T1L LINKS analog.com Rev. C | 29 of 85 bit, B10L_TX_LVL_HI_ABLE (read only), is set automatically to the defined hardware configuration as follows: ►B10L_TX_LVL_HI_ABLE = 0: 1.0 V p-p only ability ►B10L_TX_LVL_HI_ABLE = 1: 1.0 V p-p and 2.4 V p-p ability See the Configuration of Transmit Level Mode section for more details. Advertise High Voltage Transmit Ability Set the AN_ADV_B10L_TX_LVL_HI_ABL bit to 1 to advertise the high level transmit mode to the link partner during autonegotiation. This bit can only be set if the ADIN1100 has the ability to transmit in high voltage mode (B10L_TX_LVL_HI_ABLE = 1). High voltage transmit ability only enables the ADIN1100 to adver- tise support for both 2.4 V p-p and 1.0 V p-p levels. The selected level is determined by autonegotiation with the link partner. See the Transmit Amplitude Advertisement section for more details. Advertise a Request for High Voltage Transmit Level Set the AN_ADV_B10L_TX_LVL_HI_REQ bit to 1 to advertise a re- quest for 2.4 V p-p transmit level operation during autonegotiation. This bit can only be set if the ADIN1100 has the ability to transmit in high voltage mode (B10L_TX_LVL_HI_ABLE = 1). See the Transmit Amplitude Advertisement section for more details. Read Link Partner Advertised Transmit Level The link partner advertised transmit information can be read using the link partner high level transmit operating mode ability bit (AN_LP_ADV_B10L_TX_LVL_HI_ABL) and the link partner high level transmit operating mode request bit (AN_LP_ADV_B10L_TX_LVL_HI_REQ). These bits are valid when the autonegotiation is completed (AN_COMPLETE = 1). See the Transmit Amplitude Advertisement section for more details. Completion of Autonegotiation When autonegotiation has completed, the autonegotiation complete indication register bit (AN_LINK_GOOD) is set. This bit indicates the completion of the autonegotiation sequence and that the ena- bled PHY link is setting up or active. When autonegotiation has completed and the link is up, the autone- gotiation complete register bit (AN_COMPLETE) is set to 1 and the contents of the following registers are valid: ►BASE-T1 autonegotiation advertisement registers ►AN_ADV_ABILITY_L: Bits[15:0] ►AN_ADV_ABILITY_M: Bits[31:16] ►AN_ADV_ABILITY_H: Bits[47:32] ►BASE-T1 autonegotiation link partner base page ability registers ►AN_LP_ADV_ABILITY_L: Bits[15:0] ►AN_LP_ADV_ABILITY_M: Bits[31:16] ►AN_LP_ADV_ABILITY_H: Bits[47:32] Link Status The status of the link can be determined by reading the link status register bit (AN_LINK_STATUS). This bit latches low. When read as 1, this bit indicates that a valid link has been established. If this bit reads 0, it means that the link has failed since the last time it was read. This bit latches low. Thus, if a 0 is read, this bit must be read a second time to determine if the link status has come up in the interim (see the Latch Low Registers section). If the link is dropped, the autonegotiation process restarts automati- cally. Autonegotiation can be restarted by request through a write to the autonegotiation restart bit (AN_RESTART) in the AN_CON- TROL register (see the BASE-T1 Autonegotiation Control Register section).

analog data paths within the PHY core. ed to the MDI interface to improve the test mode accuracy. within the PCS block at the input stage of the PHY digital block. MAC interface is not transferred to the ADIN1100 PHY core. complete link by ensuring that the PHY receives the proper data. transferred through the MAC interface. the MAC transmission signal pins to the MAC reception signal pins. The wiring configuration required is described in Table 23. Table 23. External MII/RMII Loopback Wiring must be set to 1 so that CRS_DV can be connected to TX_EN. bits to be set to be enabled.

Figure 16. ADIN1100 Loopback Modes checker can be used to check the echoed self generated frames. Diagnostics Clock Control Register section). the number of frames to be generated. tor Enable Register section). Count Low Register section). errors, and undersized frame errors. delimiter (SSD) state is entered. Configuration Register section).

1. The PHY 1 frames (frame generator) are sent over the

10BASE-T1L single pair cable.

1. PHY 2 receives frames on the PHY 2 MDI pins.
2. The PHY 2 MAC interface loops the frame back.
3. The PHY 2 frames (looped back) are sent over the 10BASE-
4. PHY 1 receives the PHY 2 frames (looped back) on the MDI
5. The PHY 1 frame checker checks the received frames.

Figure 17. Remote Loopback Used Across Two PHYs for Self Check Purposes

testing of the transmitter waveform, distortion, jitter, and droop. teristics of the transmitter and receiver from the normal operation. Table 24. ADIN1100 Test Modes Summary Test Mode 1 Transmitter output voltage and timing jitter test mode. transmits the data symbol sequence (+1, –1). −1 symbols. This sequence is repeated indefinitely. normal interframe idle signals. specified in Subclause 146.8.3.

1. Enter software power-down mode by writing a 1 to the

(see the Software Power-Down Control Register section).

1. Check that the ADIN1100 has entered software power-down

CRSM_STAT register (see the System Status Register).

1. Disable autonegotiation by writing a 0 to the AN_EN bit in
2. Set autonegotiation forced mode by writing a 1 to the

(see the Autonegotiation Forced Mode Enable Register).

1. Select the desired test mode by writing the appropri-

settings for each PMA test mode.

1. Exit software power-down mode by writing 0 to the

(see the Software Power-Down Control Register section). Table 25. PMA Test Modes Configuration

1. Enter software power-down mode by writing a 1 to the

(see the Software Power-Down Control Register section).

1. Check that the ADIN1100 has entered the software power-

CRSM_STAT register (see the System Status Register section).

1. Disable autonegotiation by writing a 0 to the AN_EN bit in
2. Set autonegotiation forced mode by writing a 1 to the
3. Set the transmit disable mode by writing a 1 to the

ter (see the 10BASE-T1L PMA Control Register section).

1. Exit software power-down mode by writing 0 to the

(see the Software Power-Down Control Register section). fault detection, distance to fault, and cable length estimation. cables and more advanced cable diagnostic capabilities. Figure 18. ADIN1100 TDR Engine

maximum of 1600 m, with an accuracy of 2%. is no control over the remote end. so that they can be executed by any low-power microcontroller. meters from the MDI connector. shorted. No load or cable can be connected to the MDI port. depends on the accuracy of the NVP value. stored in nonvolatile memory. accuracy of the cable length used to perform the NVP calibration. Table 26. Length Estimation Error for Different Cables overall 10BASE-T1L link segment/channel quality.

with an absolute error above 0.3125 threshold. counter reports a count of four. its value is the direct read value from the corresponding register.

1. Write a 0x2 to the SPIKE_CNTRS_CNTRL register.
2. Write a 0x2 to the MAX_ABS_VALS_CNTRL register.
3. Read the SLCR_ERR_MAX_ABS_VAL register, which corre-

sponds to the slicer maximum error.

1. Read the SLCR_ERR_SPIKE_CNT register, which corresponds

to the slicer error spike counter. Table 29. Registers to the Slicer Spike and Error Counters SLCR_ERR_SPIKE_CNT0x01 0x8305 Slicer error spike counter. recommended interpretation is explained in Table 30. Table 30. Link Quality Indication Using Slicer Error Spike Counter and Slicer

Figure 29. External 25 MHz Clock Input Circuit for MII and RGMII Modes Table 31. Recommended R1 and R2 Values for Different VS p-p Values on XTAL/CLK_IN with the XTAL_O pin left open circuit. trace) for RMII timing purposes. Figure 30. External 50 MHz Clock Input Circuit for RMII Mode Table 32. C1 and C2 Values for Different VS p-p Values with VCLK_IN = 1 V p-p

1.0 Not applicable 50 Ω

current required by the circuit. In addition, see the IPC-2141 standard for models and guidelines. Table 33. Trace Parasitic Capacitance Examples

Table 33. Trace Parasitic Capacitance Examples (Continued) The ADIN1100 was tested at the system level for EMC and EMI. Table 34 summarizes the results. Table 34. EMC/EMI Tests Conducted on ADIN1100 at System Level

operations in the management registers. some registers after power-up, hardware reset, or software reset. configuration pin setup for managed and unmanaged applications. in 32 different PHY addresses. Table 35. Clause 22 Frame Format Table 36. Clause 22 Input Register Decode

MMDs through a single MDIO interface. address and register specified in the first frame. Table 37. Register Groupings Table 38. Clause 45 Frame Format Table 39. Clause 45 Input Register Decode

opportunity to observe that the link dropped. between MDIO accessible bits that share a register address. with the AN_LINK_STATUS bit. Table 40. Software Reset Bit Access in IEEE MMD Locations hardware reset, or software reset.

Table 41. ADIN1100 Register Summary Table 42. Bit Descriptions for MI_CONTROL 12 MI_AN_EN Autonegotiation Enable. Use the AN_FRC_MODE_EN bit to enable forced link configuration mode. initialization has been performed. Mirrors CRSM_SFT_PD. only able to operate in full duplex mode. only able to operate in full duplex mode, and does not have a collision detect MII (COL) pin. reads as 00 because the PHY is only able to operate at 10 Mbps. has determined that a valid link has been established.

Table 43. Bit Descriptions for MI_STATUS not support this technology. that the PHY does not support this technology. that the PHY does not support this technology. the PHY does not support this technology. indicate that the PHY does not support this technology. indicate that the PHY does not support this technology. PHY does not provide extended status information in Register 0xF. only transmit data from the MII when it has determined that a valid link has been established. not preceded by the preamble pattern. process has been completed and the PHY link is up. Mirrors AN_COMPLETE. the ability to perform autonegotiation. Mirrors AN_ABLE. latching is cleared when the bit is read. Mirrors 7.513.2 (AN_LINK_STATUS). incorporate a jabber detect function. provides an extended set of capabilities that can be accessed through the extended register set. The extended register set consists of all of the management registers except 0x0, 0x1, and 0xF. The PHY Identifier 1 address allows 16 bits of the OUI to be observed. Table 44. Bit Descriptions for MI_PHY_ID1 The PHY Identifier 2 address allows six bits of the OUI, and the model and revision number to be observed.

Table 45. Bit Descriptions for MI_PHY_ID2 Table 46. Bit Descriptions for MMD_ACCESS_CNTRL 01: data, no post increment. 10: data, post increment on reads and writes. 11: data, post increment on writes only. using the interface and mechanisms defined in Clause 22.2.4. Table 47. Bit Descriptions for MMD_ACCESS mechanisms defined in Clause 22.2.4. Table 48. Ethernet Clause 45 Register Summary

Table 48. Ethernet Clause 45 Register Summary (Continued) Page Ability Register, Bits[15:0]. Page Ability Register, Bits[31:16]. Page Ability Register, Bits[47:32]. Page Ability Register, Bits[15:0]. Page Ability Register, Bits[31:16]. Page Ability Register, Bits[47:32].

Power Management Control Register.

register is dependent on the hardware configuration pin settings. Table 49. Bit Descriptions for PMA_PMD_CNTRL1 a reset is in progress. Otherwise, it returns a value of 0. held in power-down mode until an appropriate software initialization is performed. returns it on the receive path. When this bit is set to 0, the PMA works in normal mode.

Table 50. Bit Descriptions for PMA_PMD_STAT1 that the link has dropped since the last time the bit was read. Table 51. Bit Descriptions for PMA_PMD_DEVS_IN_PKG1 autonegotiation MMDs are present. Table 52. Bit Descriptions for PMA_PMD_DEVS_IN_PKG2 Table 53. Bit Descriptions for PMA_PMD_CNTRL2 value for this bit field is for BASE-T1 PMA/PMD. 0000001: 10GBASE-EW PMA/PMD. 0000010: 10GBASE-LW PMA/PMD. 0000011: 10GBASE-SW PMA/PMD. 0000101: 10GBASE-ER PMA/PMD. 0000110: 10GBASE-LR PMA/PMD. 0000111: 10GBASE-SR PMA/PMD. 0001000: 10GBASE-LRM PMA/PMD. 0001011: 10GBASE-KR PMA/PMD.

Table 53. Bit Descriptions for PMA_PMD_CNTRL2 (Continued) 0100100: 40GBASE-FR PMA/PMD. 0110010: 10GPASS-XR-D PMA/PMD. 0110011: 10GPASS-XR-U PMA/PMD. 0110101: 25GBASE-LR PMA/PMD. 0110110: 25GBASE-ER PMA/PMD. 0111000: 25GBASE-CR or 25GBASE-CR-S PMA/PMD. 0111001: 25GBASE-KR or 25GBASE-KR-S PMA/PMD. 0111010: 25GBASE-SR PMA/PMD.

Table 54. Bit Descriptions for PMA_PMD_STAT2 Table 55. Bit Descriptions for PMA_PMD_TX_DIS PMD enables the output on the transmit path. Table 56. Bit Descriptions for PMA_PMD_EXT_ABILITY read only, and writes have no effect.

Table 57. Bit Descriptions for PMA_PMD_BT1_ABILITY Table 58. Bit Descriptions for PMA_PMD_BT1_CONTROL configured as a leader. Otherwise, the device is configured as a follower. enabled. If autonegotiation is enabled, the PHY type is determined by the autonegotiation process itself. Note that for ADIN1100, the only valid value is for 10BASE-T1L. Table 59. Bit Descriptions for B10L_PMA_CNTRL transmit path. Otherwise, it enables output on the transmit path. process. When this bit is set as 1, the device works in the 2.4 V p-p operating mode. Otherwise, the device works in the 1.0 V p-p operating mode.

Table 59. Bit Descriptions for B10L_PMA_CNTRL (Continued) Table 60. Bit Descriptions for B10L_PMA_STAT T1L high voltage (2.4 V p-p) transmit level operating mode. value of this register selects normal operation without management intervention as the initial state of the device. Table 61. Bit Descriptions for B10L_TEST_MODE_CNTRL enabled, the PHY repeatedly transmits the data symbol sequence (+1, −1). transmits ten +1 symbols followed by ten −1 symbols. as in nontest operation and in the leader data mode with data set to normal interframe idle signals. Table 62. Bit Descriptions for B10L_PMA_LINK_STAT

Table 62. Bit Descriptions for B10L_PMA_LINK_STAT (Continued) remote receiver status is OK. Table 63. Bit Descriptions for MSE_VAL 10BASE-T1L idle symbol power is 0.64422. Table 64. Bit Descriptions for PCS_CNTRL1 receive path. When this bit is set to 0, the PCS works in normal mode. Table 65. Bit Descriptions for PCS_STAT1

Table 66. Bit Descriptions for PCS_DEVS_IN_PKG1 Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. Table 67. Bit Descriptions for PCS_DEVS_IN_PKG2 Table 68. Bit Descriptions for PCS_STAT2 Table 69. Bit Descriptions for B10L_PCS_CNTRL Table 70. Bit Descriptions for B10L_PCS_STAT has unlocked since the last time the bit was read.

Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 71. Bit Descriptions for AN_DEVS_IN_PKG1 autonegotiation MMDs are present. Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. Table 72. Bit Descriptions for AN_DEVS_IN_PKG2 Table 73. Bit Descriptions for AN_CONTROL default and it is strongly recommended to always keep it enabled. returns a value of 1 until the autonegotiation process is initiated. Table 74. Bit Descriptions for AN_STATUS resets to 0 on a read of the AN_STATUS register.

Table 74. Bit Descriptions for AN_STATUS (Continued) means that the link has failed since the last time it was read. Table 75. Bit Descriptions for AN_ADV_ABILITY_L configuration. When this bit is set as 0, the leader/follower configuration is a preferred mode. [4:0] AN_ADV_SELECTOR Selector. The value of this bit field is fixed at 00001, which is the IEEE 802.3 selector value. Table 76. Bit Descriptions for AN_ADV_ABILITY_M configuration is Bit 4 of the transmitted nonce field).

Table 77. Bit Descriptions for AN_ADV_ABILITY_H AN_ADV_B10L_TX_LVL_HI_REQ bit for more details. V p-p) transmit operating mode. AN_LP_ADV_ABILITY_L is read. Table 78. Bit Descriptions for AN_LP_ADV_ABILITY_L 0: preferred mode (AN_LP_ADV_MST is a preferred configuration). 1: forced mode (AN_LP_ADV_MST is a forced configuration).

the latched value rather than the current value. Table 79. Bit Descriptions for AN_LP_ADV_ABILITY_M the latched value rather than the current value. Table 80. Bit Descriptions for AN_LP_ADV_ABILITY_H using 10BASE-T1L energy efficient Ethernet. AN_ADV_B10L_TX_LVL_HI_REQ bit for more details. capable of using 10BASE-T1S half duplex.

set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L. Table 81. Bit Descriptions for AN_NEXT_PAGE_L 15 AN_NP_NEXT_PAGE_REQNext Page Request. This bit indicates to the link partner that the PHY wants to send a next page. (the toggle bit is set automatically by the arbitration state machine). values are defined in IEEE Standard 802.3. 5: organizationally unique identifier tagged message. 6: autonegotiation device identifier tag code. set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L. Table 82. Bit Descriptions for AN_NEXT_PAGE_M set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L. Table 83. Bit Descriptions for AN_NEXT_PAGE_H of Standard 802.3. The values of AN_LP_NEXT_PAGE_M and AN_LP_NEXT_PAGE_H are latched when this register is read.

Table 84. Bit Descriptions for AN_LP_NEXT_PAGE_L 5: organizationally unique identifier tagged message. 6: autonegotiation device identifier tag code. latched value rather than the current value. Table 85. Bit Descriptions for AN_LP_NEXT_PAGE_M rather than the current value. Table 86. Bit Descriptions for AN_LP_NEXT_PAGE_H Table 87. Bit Descriptions for AN_B10_ADV_ABILITY does not have the energy efficient Ethernet ability. of the AN_ADV_B10L_TX_LVL_HI_ABL bit.

Table 87. Bit Descriptions for AN_B10_ADV_ABILITY (Continued) duplicate of the AN_ADV_B10L_TX_LVL_HI_REQ bit. Table 88. Bit Descriptions for AN_B10_LP_ADV_ABILITY the AN_LP_ADV_B10L_TX_LVL_HI_ABL bit. of the AN_LP_ADV_B10L_TX_LVL_HI_REQ bit. 0) and AN_FRC_MODE_EN = 1, forced mode is enabled. Table 89. Bit Descriptions for AN_FRC_MODE_EN This register is provided in addition to AN_STATUS. Table 90. Bit Descriptions for AN_STATUS_EXTRA autonegotiation good check state.

Table 90. Bit Descriptions for AN_STATUS_EXTRA (Continued) 2: success, low transmit levels (1.0 V p-p) selected. 3: success, high transmit levels (2.4 V p-p) selected. 2: success, PHY is configured as follower. 3: success, PHY is configured as leader. also AN_COMPLETE, which is similar, but also indicates that the PHY link is up. register is a consistent set, that is, a set of values in effect at the time the register address is read. Table 91. Bit Descriptions for AN_PHY_INST_STATUS state or the AN good state. That is, the link_control signals have not been set to enable. operating as leader (and not follower). is operating as follower (and not leader). the organizationally unique identifier (OUI) to be observed.

Table 92. Bit Descriptions for MMD1_DEV_ID1 the OUI along with the model number and revision number to be observed. Table 93. Bit Descriptions for MMD1_DEV_ID2 Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 94. Bit Descriptions for MMD1_DEVS_IN_PKG1 Vendor Specific 1 and Vendor Specific 2 MMDs are present. Table 95. Bit Descriptions for MMD1_DEVS_IN_PKG2 Table 96. Bit Descriptions for MMD1_STATUS 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address.

associated interrupts are not enabled. A reserved interrupt being triggered indicates a system error, which requires a hardware reset. Table 97. Bit Descriptions for CRSM_IRQ_STATUS Controls whether or not the interrupt signal is asserted in response to various events. Table 98. Bit Descriptions for CRSM_IRQ_MASK testing. This bit always reads as 0 because it is self clearing. because this bit is initialized when a hardware reset occurs. Table 99. Bit Descriptions for CRSM_SFT_RST initializes, almost equivalent to a hardware reset. Table 100. Bit Descriptions for CRSM_SFT_PD_CNTRL chip to be held in power-down mode until an appropriate software initialization is performed.

Table 101. Bit Descriptions for CRSM_PHY_SUBSYS_RST be initiated. When the PHY subsystem is reset, normal operation resumes, and the bit self clears. Table 102. Bit Descriptions for CRSM_MAC_IF_RST Table 103. Bit Descriptions for CRSM_STAT Table 104. Bit Descriptions for CRSM_PMG_CNTRL Configure the MAC interface only by pins. Do not change by software. Table 105. Bit Descriptions for CRSM_MAC_IF_CFG

Table 105. Bit Descriptions for CRSM_MAC_IF_CFG (Continued) only be enabled if an RMII MAC interface is being used. interface only by pins. Do not change by software. interface only by pins. Do not change by software. CRSM diagnostics clock control. Table 106. Bit Descriptions for CRSM_DIAG_CLK_CTRL The MGMT_PRT_PKG_VAL address allows reading of the package configuration values. Table 107. Bit Descriptions for MGMT_PRT_PKG Table 108. Bit Descriptions for MGMT_MDIO_CNTRL address operation to the 5-bit PHY/Port Address 31 (decimal) regardless of its own PHY/port address. those cases, and cleared immediately after the initialization is complete.

Table 109. Bit Descriptions for DIGIO_PINMUX 111: LED_1 output not enabled. Table 110. Bit Descriptions for DIGIO_PINMUX2

Table 110. Bit Descriptions for DIGIO_PINMUX2 (Continued) LED on blink time = LED0_ON_N4MS × 4 ms. LED off blink time = LED0_OFF_N4MS × 4 ms. LED switches off for either loss of link or receipt of activity. If LEDx_FUNCTION is programmed to an activity signal, the LED is off with no activity. The LED switches on upon receipt of activity. Table 111. Bit Descriptions for LED0_BLINK_TIME_CNTRL [15:8] LED0_ON_N4MS LED_0 On Blink Time. LED_0 on blink time is calculated by 4 ms × LED0_ON_N4MS bit field. Recommended value is greater than 3. [7:0] LED0_OFF_N4MS LED_0 Off Blink Time. LED_0 off blink time is calculated by 4 ms × LED0_OFF_N4MS bit field. Recommended value is greater than 3. LED on blink time = LED1_ON_N4MS × 4ms. LED off blink time = LED1_OFF_N4MS × 4 ms. LED switches off for either loss of link or receipt of activity. If LEDx_FUNCTION is programmed to an activity signal, the LED is off with no activity. The LED switches on upon receipt of activity.

Table 112. Bit Descriptions for LED1_BLINK_TIME_CNTRL [15:8] LED1_ON_N4MS LED_1 On Blink Time. LED_1 on blink time is calculated by 4 ms × LED1_ON_N4MS bit field. Recommended value is greater than 3. [7:0] LED1_OFF_N4MS LED_1 Off Blink Time. LED_1 off blink time is calculated by 4 ms × LED1_OFF_N4MS bit field. Recommended value is greater than 3. Table 113. Bit Descriptions for LED_CNTRL 0: TX_LEVEL_2P4, TX_LEVEL_1P0, leader, follower not qualified by link_status. 1: TX_LEVEL_2P4, TX_LEVEL_1P0, leader, follower are qualified by link_status. 0: LED Mode 1. If there is activity, blink at the rate defined by MMR LED1_BLINK_TIME_CNTRL. chip is dependent on the selected clock source frequency. REM_RCVR_STATUS, CLK25_REF, TX_TCLK, and CLK_120MHz. this is controlled via the LED1_LINK_ST_QUALIFY MMR. 7: LINKUP_RX_ER (available in LED Mode 1 only). 8: LINKUP_RX_TX_ER (available in LED Mode 1 only). 9: RX_ER (available in LED Mode 1 only). 10: RX_TX_ER (available in LED Mode 1 only).

Table 113. Bit Descriptions for LED_CNTRL (Continued) 0: TX_LEVEL_2P4, TX_LEVEL_1P0, leader, follower not qualified by link_status. 1: TX_LEVEL_2P4, TX_LEVEL_1P0, leader, follower are qualified by link_status. 0: LED Mode 1. If activity, blink at the rate defined by MMR LED0_BLINK_TIME_CNTRL. The CLK25_REF, TX_TCLK, CLK_120MHZ options are clock out features with the LED controller bypassed. The waveform transmitted off chip is dependent on the selected clock source frequency. REM_RCVR_STATUS, CLK25_REF, TX_TCLK and CLK_120MHz. is controlled via the LED0_LINK_ST_QUALIFY MMR. 7: LINKUP_RX_ER (available in LED Mode 1 only). 8: LINKUP_RX_TX_ER (available in LED Mode 1 only). 9: RX_ER (available in LED Mode 1 only). 10: RX_TX_ER (available in LED Mode 1 only).

Allows the LED polarity to be automatically sensed by the internal logic or allows reconfiguration by the user. Table 114. Bit Descriptions for LED_POLARITY 0: LED autosense. LED active high or low as per autosense. 0: LED autosense. LED active high or low as per autosense. Table 115. Bit Descriptions for MMD2_DEV_ID1

Table 116. Bit Descriptions for MMD2_DEV_ID2 Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 117. Bit Descriptions for MMD2_DEVS_IN_PKG1 Vendor Specific 1 and Vendor Specific 2 MMDs are present. Table 118. Bit Descriptions for MMD2_DEVS_IN_PKG2 This address corresponds to the Vendor Specific MMD 2 status register. Table 119. Bit Descriptions for MMD2_STATUS 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address. bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system. Table 120. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS

Table 120. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS (Continued) Controls whether or not the interrupt signal is asserted in response to various events. Table 121. Bit Descriptions for PHY_SUBSYS_IRQ_MASK and error counter registers count these events. Table 122. Bit Descriptions for FC_EN checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit. The status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register. Table 123. Bit Descriptions for FC_IRQ_EN

received data after it is looped back at the MAC interface. Table 124. Bit Descriptions for FC_TX_SEL 1: check frames from the MAC interface to be transmitted by the PHY. 0: check frames received by the PHY from the remote end. The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY. Table 125. Bit Descriptions for RX_ERR_CNT bit is self clearing upon reading. read, the receive frame counter register is latched so that the error count and the receive frame count are synchronized. Table 126. Bit Descriptions for FC_FRM_CNT_H the receive frame counter register is latched so that the error count and receive frame count are synchronized. Table 127. Bit Descriptions for FC_FRM_CNT_L

This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status. error count and receive frame count are synchronized. Table 128. Bit Descriptions for FC_LEN_ERR_CNT error count and the receive frame count are synchronized. Table 129. Bit Descriptions for FC_ALGN_ERR_CNT This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set. frame receive count are synchronized. Table 130. Bit Descriptions for FC_SYMB_ERR_CNT oversized error count and the receive frame count are synchronized. Table 131. Bit Descriptions for FC_OSZ_CNT This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes. frame error count and the receive frame count are synchronized.

Table 132. Bit Descriptions for FC_USZ_CNT nibble frame count and the receive frame count are synchronized. Table 133. Bit Descriptions for FC_ODD_CNT ensures that the odd preamble packet count and the receive frame count are synchronized. Table 134. Bit Descriptions for FC_ODD_PRE_CNT false carrier events count and the receive frame count are synchronized. Table 135. Bit Descriptions for FC_FALSE_CARRIER_CNT generator and not the MAC interface. Table 136. Bit Descriptions for FG_EN

or all zeros. The FG_RSTRT bit restarts the frame generator. Table 137. Bit Descriptions for FG_CNTRL_RSTRT 000: no frames after completion of current frame. 001: random number data frame. 100: alternative 0x55 data field. 101: data field decrementing from 255 (decimal) to 0. frames generated is specified by the FG_NFRM_H and FG_NFRM_L registers. Table 138. Bit Descriptions for FG_CONT_MODE_EN generated. Enable the frame checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit. The interrupt status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register. Table 139. Bit Descriptions for FG_IRQ_EN when it has transmitted the programmed number of frames. 1: enable the frame generator interrupt. 0: disable the frame generator interrupt.

Table 140. Bit Descriptions for FG_FRM_LEN This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator. Table 141. Bit Descriptions for FG_IFG_LEN inserted between frames by the frame generator. Table 142. Bit Descriptions for FG_NFRM_H Table 143. Bit Descriptions for FG_NFRM_L

Table 144. Bit Descriptions for FG_DONE goes high and it latches high until it is unlatched by reading. Table 145. Bit Descriptions for RMII_CFG mainly intended for debug and test purposes. MAC interface loopbacks configuration. Table 146. Bit Descriptions for MAC_IF_LOOPBACK Table 147. Bit Descriptions for MAC_IF_SOP_CNTRL received in the first eight bytes. set until the end of the frame.

PCB LAYOUT RECOMMENDATIONS analog.com Rev. C | 84 of 85 LAND PATTERN The LFCSP has an exposed pad underneath the package that must be soldered to the PCB ground for mechanical, electrical, and thermal reasons. For thermal impedance performance and to maximize heat transfer to the PCB, the use of a 4 × 4 array of thermal vias beneath the exposed ground pad is recommended. Via tenting is also recommended. COMPONENT PLACEMENT AND ROUTING Prioritization of the critical traces and components helps simplify the routing exercise. Place and orient the critical traces and compo- nents first to ensure an effective layout. The critical components are the crystal and load capacitors, the CEXT_2 and CEXT_3 capacitors, and all bypass capacitors local to the ADIN1100 device. Prioritize these components for placement and routing. ►Place the decoupling capacitor as close as possible to their input pins. ►Minimize traces turns, and use a 45° corner. ►Avoid traces crossing power planes on adjacent layers. ►Avoid stubs. ►Keep the MDI traces (RXP, RXN, TXP, and TXN) as short as possible. ►Avoid vias on a high speed signal. Place ground vias next to the signal vias to improve the return current path. CRYSTAL PLACEMENT AND ROUTING Particular attention is required on the crystal placement and routing to ensure minimum current consumption, reduce stray capacitance, and improve noise immunity. ►Place the crystal, capacitors as close as possible to the ADIN1100 XTAL_I/CLK_IN and XTAL_O pins. ►Place the load capacitors close to each other. ►Use a local GND plane (copper island) for the crystal and load capacitors with a single point connection to the main GND. ►Reduce parasitic capacitance by keeping the XTAL_I and XTAL_O traces away from each other. ►Adding a copper keepout on the layer beneath the crystal can also reduce the parasitic capacitance. PCB STACK Follow these recommendations for the PCB stack: ►Use a PCB stack with a minimum of four layers. Consider six layers or more with external layers used as ground planes to improve EMI issues (optional). ►Define copper layer thickness based on the application and power requirements. ►Use internal layers for the power and ground planes. ►Use external layers for the signal traces. ►Use via stitching to improve ground and reduce EMI. The stitching pattern and via to via gaps are defined based on the application.

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 31. 40-Lead Lead Frame Chip Scale Package [LFCSP]