ADGS1414DBCCZ-RL7

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SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High Density Octal SPST Switch Data Sheet ADGS1414D Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Includes CRC, invalid read and write address, and SCLK count error detection Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and Mode 3 interface compatible Integrated passive components Route through of digital signals and supplies Guaranteed break-before-make switching allowing external wiring of switches to deliver multiplexer configurations 1.5 Ω typical on resistance at 25°C (±15 V dual supply) 0.3 Ω typical on resistance flatness at 25°C (±15 V dual supply) 0.1 Ω typical on resistance match between channels at 25°C (±15 V dual supply) VSS to VDD analog signal range Fully specified at ±15 V, ±5 V, and +12 V 1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V (excludes SPI readback to a 1.8 V device) 4 mm × 5 mm, 30-terminal LGA

APPLICATIONS

Audio and video signal routing Communications systems Relay replacement GENERAL DESCRIPTION The ADGS1414D contains eight independent SPST switches. A serial peripheral interface (SPI) controls the switches. The SPI has robust error detection features, such as cyclic redundancy check (CRC) error detection, invalid read and write address detection, and SCLK count error detection. It is possible to daisy-chain multiple ADGS1414D devices together. Daisy-chain mode enables the configuration of multiple devices with a minimal amount of digital lines. The route of digital signals and supplies through the ADGS1414D allows for a further increase in channel density. Integrated passive components eliminate the need for external passive components. FUNCTIONAL BLOCK DIAGRAM Figure 1. The ADGS1414D is suited to high density switching applications, such as large switching matrices and fanout applications. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Multifunction pin names may be referenced by their relevant function only. PRODUCT HIGHLIGHTS 1. The SPI removes the need for parallel conversion and logic traces and reduces the general-purpose input and output (GPIO) channel count. 2. Daisy-chain mode removes additional logic traces when multiple devices are used. 3. Route through of digital signals and supplies eases routing and allows for an increase in channel density. 4. Integrated passive components eliminate the need for external passive components. 5. CRC error detection, invalid read and write address detection, and SCLK count error detection ensure a robust digital interface. 6. CRC, invalid read and write address, and SCLK error detection capabilities allow for the use of the ADGS1414D in safety critical systems. 7. Minimum distortion. ADGS1414D S6 D6 S7 D7 S8 D8 SDO SCLK SDI VDD VL VSS CS RESET/VL S2 D2 SPI INTERFACE 23895-001

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

6/2020—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 1. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 1.5 Ω typ Source voltage, VS = ±10 V, source current, IS = −10 mA, see Figure 29 On-Resistance Match Between Channels, ∆RON 0.1 Ω typ VS = ±10 V, IS = −10 mA 0.18 0.19 0.21 Ω max On-Resistance Flatness, RFLAT (ON) 0.3 Ω typ VS = ±10 V, IS = −10 mA 0.36 0.4 0.45 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±10 V, drain voltage, VD =  10 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Drain Off Leakage, ID (Off) ±0.03 nA typ VS = ±10 V, VD =  10 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = ±10 V, see Figure 28 ±2 ±4 ±30 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max Sink current, ISINK = 1 mA

0.3 V max ISINK = 100 µA

High, VOH VL − 1.25 V V min Source current, ISOURCE = 1 mA VL − 0.125 V V min ISOURCE = 100 µA Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current Low, IINL or High, IINH 0.001 µA typ Input voltage, VIN = ground voltage, VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 On Time, tON 400 ns typ Load resistance, RL = 300 Ω, load capacitance, CL = 35 pF 475 480 485 ns max VS = 10 V, see Figure 37 Off Time, tOFF 160 ns typ RL = 300 Ω, CL = 35 pF 190 210 225 ns max VS = 10 V, see Figure 37

Rev. 0 | Page 5 of 28 ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 2. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 3.3 Ω typ VS = ±4.5 V, IS = −10 mA, see Figure 29 4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V On-Resistance Match Between Channels, ∆RON 0.13 Ω typ VS = ±4.5 V, IS = −10 mA 0.35 0.43 0.45 Ω max On-Resistance Flatness, RFLAT (ON) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA 1.1 1.24 1.31 Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±4.5 V, VD =  4.5 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Drain Off Leakage, ID (Off) ±0.03 nA typ VS = ±4.5 V, VD =  4.5 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Channel On Leakage, ID (On), IS (On) ±0.05 nA typ VS = VD = ±4.5 V, see Figure 28 ±1.0 ±4 ±30 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 1 mA High, VOH VL − 1.25 V V min ISOURCE = 1 mA VL − 0.125 V V min ISOURCE = 100 µA Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current Low, IINL or High, IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 On Time, tON 510 ns typ RL = 300 Ω, CL = 35 pF 645 680 710 ns max VS = 3 V, see Figure 37 Off Time, tOFF 280 ns typ RL = 300 Ω, CL = 35 pF 365 400 435 ns max VS = 3 V, see Figure 37 Break-Before-Make Time Delay, tD 245 ns typ RL = 300 Ω, CL = 35 pF 200 ns min VS1 = VS2 = 3 V, see Figure 36 Charge Injection, QINJ 10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38 Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31 Channel to Channel Crosstalk −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30

Rev. 0 | Page 6 of 28 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments Total Harmonic Distortion + Noise, THD + N 0.03 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz, see Figure 33 −3 dB Bandwidth 130 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 34 Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 Source Capacitance, CS (Off) 30 pF typ VS = 0 V, f = 1 MHz Drain Capacitance, CD (Off) 31 pF typ VS = 0 V, f = 1 MHz CD (On), CS (On) 116 pF typ VS = 0 V, f = 1 MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V Positive Supply Current, IDD 0.04 µA typ Digital inputs = 0 V or VL, VL = 5.5 V 4.0 µA max 28 µA typ All switches closed, VL = 2.7 V 60 µA max Load Current, IL Inactive 6.3 µA typ Digital inputs = 0 V or VL 8.0 µA max Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 7 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 210 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V 7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V 120 µA typ CS and SCLK = 0 V or VL, VL = 3 V Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V 2.1 mA max 0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V 1.0 mA max Negative Supply Current, ISS 0.04 µA typ Digital inputs = 0 V or VL 4.0 µA max VDD/VSS ±4.5/±16.5 V min/V max GND = 0 V 1 Guaranteed by design. Not subject to production test.

Rev. 0 | Page 7 of 28

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 3. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 2.8 Ω typ VS = 0 V to 10 V, IS = −10 mA, see Figure 29 3.5 4.3 4.8 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match Between Channels, ∆RON 0.13 Ω typ VS = 0 V to 10 V, IS = −10 mA 0.35 0.43 0.45 Ω max On-Resistance Flatness, RFLAT (ON) 0.6 Ω typ VS = 0 V to 10 V, IS = −10 mA 1.1 1.2 1.3 Ω max LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = 1 V/10 V, see Figure 28 ±1.5 ±4 ±30 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 1 mA High, VOH VL − 1.25 V V min ISOURCE = 1 mA VL − 0.125 V V min ISOURCE = 100 µA Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current Low, IINL or High, IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 On Time, tON 470 ns typ RL = 300 Ω, CL = 35 pF 570 595 615 ns max VS = 8 V, see Figure 37 Off Time, tOFF 170 ns typ RL = 300 Ω, CL = 35 pF 215 240 265 ns max VS = 8 V, see Figure 37 Break-Before-Make Time Delay, tD 280 ns typ RL = 300 Ω, CL = 35 pF 225 ns min VS1 = VS2 = 8 V, see Figure 36 Charge Injection, QINJ 10 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 38 Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31

Table 4. Eight Channels On 1 Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins. Table 5. One Channel On 1 Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins. noted. Guaranteed by design and characterization, not production tested. See Figure 2 to Figure 4 for the timing diagrams. 1 Measured with a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.

TA = 25°C, unless otherwise noted. 1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins. operational section of this specification is not implied. extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. PCB thermal design is required. the junction to the bottom of the case value. Table 8. Thermal Resistance

1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with four thermal vias. See JEDEC JESD-51. ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 9. ADGS1414D, 30-Terminal LGA

Figure 5. Pin Configuration Table 10. Pin Function Descriptions 1 D1 Drain Terminal 1. The D1 pin can be an input or an output. 2 D2 Drain Terminal 2. The D2 pin can be an input or an output. 3 S1 Source Terminal 1. The S1 pin can be an input or an output. 4 S2 Source Terminal 2. The S2 pin can be an input or an output. 5 VSS Most Negative Power Supply Potential. In single-supply applications, tie the VSS pin to ground. 6 S3 Source Terminal 3. The S3 pin can be an input or an output. 7 S4 Source Terminal 4. The S4 pin can be an input or an output. 8 D3 Drain Terminal 3. The D3 pin can be an input or an output. 9 D4 Drain Terminal 4. The D4 pin can be an input or an output. 10, 30 VDD Most Positive Power Supply Potential. Both VDD pins are connected internally. 11, 29 GND Ground (0 V) Reference. Both GND pins are connected internally. set to their default. Both RESET and VL are connected internally. 50 MHz. Both SCLK pins are connected internally. 16 D5 Drain Terminal 5. The D5 pin can be an input or an output. 17 D6 Drain Terminal 6. The D6 pin can be an input or an output. 18 S5 Source Terminal 5. The S5 pin can be an input or an output. 19 S6 Source Terminal 6. The S6 pin can be an input or an output. 20 NIC Not Internally Connected. 21 S7 Source Terminal 7. The S7 pin can be an input or an output. 22 S8 Source Terminal 8. The S8 pin can be an input or an output. 23 D7 Drain Terminal 7. The D7 pin can be an input or an output. 24 D8 Drain Terminal 8. The D8 pin can be an input or an output. 27 SDI Serial Data Input. Data is captured on the positive edge of SCLK. maximum thermal capability, it is recommended that the exposed pad is connected to VSS.

1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. THE EXPOSED PAD IS CONNECTED

20 NIC

Figure 6. On Resistance vs. VS or VD for Various Dual Supplies, ±10 V to Figure 7. On Resistance vs. VS or VD for Various Dual Supplies, ±4.5 V to Figure 8. On Resistance vs. VS or VD for Various Single Supplies Figure 9. On Resistance vs. VS or VD for Various Temperatures, Figure 10. On Resistance vs. VS or VD for Various Temperatures, Figure 11. On Resistance vs. VS or VD for Various Temperatures,

Rev. 0 | Page 19 of 28 TERMINOLOGY IDD IDD represents the positive supply current. ISS ISS represents the negative supply current. VD, VS VD and VS represent the analog voltage on Terminal Dx and Terminal Sx, respectively. RON RON represents the ohmic resistance between Terminal Dx and Terminal Sx. ∆RON ∆RON represents the difference between the RON of any two channels. RFLAT (ON) RFLAT (ON) is flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. CIN CIN is the digital input capacitance. COUT COUT is the digital output capacitance. tON tON represents the delay between applying the digital control input and the output switching on. tOFF tOFF represents the delay between applying the digital control input and the output switching off. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. −3 dB Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) THD + N is the ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the ratio of the amplitude of the signal on the output to the amplitude of the modulation. AC PSRR is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

number of SCLK cycles are sent by the microcontroller or CPU.

16 SCLK cycles are received by the device, a write to the register

error asserts when a write to a read only register is attempted. flags register when an invalid read and write address error occurs. disabled by the user through the error configuration register. error flags register resets to zero. of SDI and SDO during burst mode. count error detection operates in a slightly different manner. 24 when CRC is enabled, the SCLK count error flag asserts. Figure 41. Burst Mode Frame configuration changes while in daisy-chain mode. Figure 42. Two ADGS1414D Devices Connected in a Daisy-Chain Configuration

The ADGS1414D exhibits break-before-make switching action. Figure 46. An SPI Controlled Switch Configured into a 4:1 Mux supplies between 5 V and 20 V with VSS connected to GND. The voltage range that can be supplied to VL is from 2.7 V to 5.5 V. An example of a bipolar power solution is shown in Figure 47. in ultralow noise sensitive applications. power digital circuitry within the ADGS1414D. Figure 47. Bipolar Power Solution Table 11. Recommended Power Management Devices

1.8 V LOGIC COMPATIBILITY

The SDO digital output levels are proportional to the VL voltage. then translates the logic level of the SDO from VL to 1.8 V. FPGA cannot tolerate digital input signals that exceed 1.8 V. Figure 48. Using the ADG3231 to Perform a 1.8 V SPI Readback

Table 12. Register Summary

Use the switch data register to control the status of the eight switches of the ADGS1414D. Table 13. Bit Descriptions for SW_DATA Use the error configuration register to enable and disable the relevant error features as required. Table 14. Bit Descriptions for ERR_CONFIG

1 SCLK_ERR_EN Enable the SCLK_ERR_EN bit to detect the correct number of SCLK cycles

cycles are expected when CRC is enabled and burst mode is enabled.

CRC byte during the SPI write for the clear error flags register command to succeed. Table 15. Bit Descriptions for ERR_FLAGS when the target address of an SPI write does not exist or is read only.

1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in an SPI

0 CRC_ERR_FLAG Error flag that determines if a CRC error has occurred during a register

commands without deasserting CS. Table 16. Bit Descriptions for BURST_EN the device reset to their default state. Table 17. Bit Descriptions for SOFT_RESETB to the SOFT_RESETB register.

Figure 49. 30-Terminal Land Grid Array [LGA] registered trademarks are the p roperty of their respective owners.