ADGS1208

ADGS1208/ADGS1209 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 33

Technical content

SPI Interface, Low CON and QINJ, ±15 V/+12 V,

1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches

Data Sheet ADGS1208/ADGS1209 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

SPI interface with error detection Includes CRC, invalid read/write address, and SCLK count error detection Supports burst mode and daisy-chain mode Industry standard SPI Mode 0 and SPI Mode 3 interface compatible Round robin mode allows switching times that are comparable with a parallel interface Four general-purpose digital outputs that can be used to control other devices <1 pC charge injection over full signal range 1 pF off capacitance V SS to VDD analog signal range Fully specified at ±15 V and +12 V 1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V 24-lead LFCSP package

APPLICATIONS

The ADGS1208/ADGS1209 are analog multiplexers comprising eight single channels and four differential channels, respectively. A serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features, such as cyclic redundancy check (CRC) error detection, invalid read/write address detection, and SCLK count error detection. It is possible to daisy-chain multiple ADGS1208/ADGS1209 devices together. Daisy-chain mode enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS1208/ADGS1209 can also operate in burst mode to decrease the time between SPI commands. iCMOS® construction ensures ultralow power dissipation, making the devices ideally suited for portable and battery- powered instruments. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. FUNCTIONAL BLOCK DIAGRAMS ADGS1208 GPO1 CNV SDO GPO2 GPO3 GPO4 D SPI INTERFACE SCLK SDI CS RESET/V L 16724-001 Figure 1. ADGS1208 Functional Block Diagram Figure 2. ADGS1209 Functional Block Diagram low glitch and fast settling are required.

1. SPI interface removes the need for parallel conversion,

logic traces, and reduces GPIO channel count.

1. Daisy-chain mode removes additional logic traces when
2. CRC error detection, invalid read/write address detection,
3. CRC and error detection capabilities allow the use of the

ADGS1208/ADGS1209 in safety critical systems.

ADGS1208/ADGS1209 Data Sheet Rev. 0 | Page 2 of 33 TABLE OF CONTENTS

REVISION HISTORY

4/2018—Revision 0: Initial Version

Data Sheet ADGS1208/ADGS1209 Rev. 0 | Page 3 of 33 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V , unless otherwise noted. Table 1. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 150 Ω typ VS = ±10 V, IS = −1 mA, see Figure 39 200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between Channels, ∆RON 3.5 Ω typ VS = ±10 V, IS = −1 mA 6 10 12 Ω max On Resistance Flatness, RFLAT (ON) 35 Ω typ VS = ±10 V, IS = −1 mA 64 76 83 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage, IS (Off ) ±0.003 nA typ VS = ±10 V, VD =  10 V, see Figure 36 Drain Off Leakage, ID (Off ) ±0.003 nA typ VS = ±10 V, VD =  10 V, see Figure 36 Channel On Leakage, ID (On), IS (On) ±0.02 nA typ VS = VD = ±10 V, see Figure 32 DIGITAL OUTPUTS SDO Output Voltage Low, VOL 0.4 V max Sink current (ISINK) = 5 mA

0.2 V max ISINK = 1 mA

High Impedance Leakage Current 0.001 µA typ Output voltage (VOUT) = VGND or VL ±0.1 µA max High Impedance Output Capacitance 4 pF typ GPOx Output Voltage High, VOH VL − 0.2 V V min ISOURCE = 100 µA Low, VOL 0.2 V max ISINK = 100 µA Timing tON 95 ns typ CL = 15 pF, see Figure 44 115 115 115 ns max tOFF 15 ns typ CL = 15 pF, see Figure 44 20 25 25 ns max Break-Before-Make Time Delay, tD 50 ns typ CL = 15 pF, see Figure 45 35 ns min

ADGS1208/ADGS1209 Data Sheet Rev. 0 | Page 4 of 33 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments DIGITAL INPUTS/OUTPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current, IINL or IINH 0.001 µA typ Input voltage (VIN) = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION 90 ns typ RL = 300 Ω, CL = 35 pF 145 170 195 ns max VS = 10 V, see Figure 41 tON (EN) 92 ns typ RL = 300 Ω, CL = 35 pF 110 140 155 ns max VS = 10 V, see Figure 42 tOFF (EN) 120 ns typ RL = 300 Ω, CL = 35 pF 135 170 190 ns max VS = 10 V, see Figure 42 Break-Before-Make Time Delay, tD 32 ns typ RL = 300 Ω, CL = 35 pF 7 ns min VS1 = VS2 = 10 V, see Figure 40 Charge Injection, QINJ 0.4 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 43 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz, see Figure 34 Channel to Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz, see Figure 33 Total Harmonic Distortion Plus Noise 0.15 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, see Figure 38 −3 dB Bandwidth RL = 50 Ω, CL = 5 pF , see Figure 37 ADGS1208 550 MHz typ ADGS1209 630 MHz typ Insertion Loss −6 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz, see Figure 37 CS (Off ) 1 pF typ VS = 0 V, f = 1 MHz 1.6 pF max VS = 0 V, f = 1 MHz CD (Off ) ADGS1208 5 pF typ VS = 0 V, f = 1 MHz 5.5 pF max VS = 0 V, f = 1 MHz ADGS1209 2 pF typ VS = 0 V, f = 1 MHz 3.5 pF max VS = 0 V, f = 1 MHz CD (On), CS (On) ADGS1208 5 pF typ VS = 0 V, f = 1 MHz 6.5 pF max VS = 0 V, f = 1 MHz ADGS1209 3 pF typ VS = 0 V, f = 1 MHz 4.5 pF max VS = 0 V, f = 1 MHz

Data Sheet ADGS1208/ADGS1209 Rev. 0 | Page 5 of 33 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS V DD = +16.5 V, VSS = −16.5 V IDD 0.002 μA typ All switches open 1.0 μA max 220 μA typ All switches closed, V L = 5.5 V 380 μA max 270 μA typ All switches closed, V L = 2.7 V 440 μA max IL Inactive 6.3 μA typ Digital inputs = 0 V or V L 8.0 μA max Inactive, SCLK = 1 MHz 14 μA typ CS E = VL and SDI = 0 V or VL, VL = 5 V 7 μA typ CS E = VL and SDI = 0 V or VL, VL = 3 V SCLK = 50 MHz 390 μA typ CS E = VL and SDI = 0 V or VL, VL = 5 V 210 μA typ CS E = VL and SDI = 0 V or VL, VL = 3 V Inactive, SDI = 1 MHz 15 μA typ CS E and SCLK = 0 V or VL, VL = 5 V 7.5 μA typ CS E and SCLK = 0 V or VL, VL = 3 V SDI = 25 MHz 230 μA typ CS E and SCLK = 0 V or VL, VL = 5 V 120 μA typ CS E and SCLK = 0 V or VL, VL = 3 V Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V 2.1 mA max 0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V 1.0 mA max ISS 0.002 μA typ Digital inputs = 0 V or V L 1.0 μA max VDD/VSS ±4.5 V min GND = 0 V ±16.5 V max GND = 0 V 1 Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V , VL = 2.7 V to 5.5 V , and GND = 0 V , unless otherwise noted. Table 2. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance, RON 380 Ω typ VS = 0 V to 10 V, IS = −1 mA, see Figure 39 475 570 625 Ω max V DD = 10.8 V, VSS = 0 V On Resistance Match Between Channels, ∆RON 5 Ω typ V S = 0 V to 10 V, IS = −1 mA 16 26 27 Ω max On Resistance Flatness, RFLAT (ON) 200 Ω typ V S = 0 V to 10 V, IS = −1 mA

ADGS1208/ADGS1209 Data Sheet Rev. 0 | Page 6 of 33 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off ) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36 Drain Off Leakage, ID (Off ) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36 Channel On Leakage, ID (On), IS (On) ±0.02 nA typ VS = VD = 1 V/10 V, see Figure 32 DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA High Impedance Leakage Current 0.001 µA typ VOUT = VGND or VL ±0.1 µA max High Impedance Output Capacitance 4 pF typ GPOx Output Voltage High, VOH VL − 0.2 V V min ISOURCE = 100 µA Low, VOL 0.2 V max ISINK = 100 µA Timing tON 95 ns typ CL = 15 pF, see Figure 44 115 115 115 ns max tOFF 15 ns typ CL = 15 pF, see Figure 44 20 25 25 ns max Break-Before-Make Time Delay, tD 50 ns typ CL = 15 pF, see Figure 45 35 ns min DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTIC1 Transition Time, tTRANSITION 110 ns typ RL = 300 Ω, CL = 35 pF 185 220 245 ns max VS = 8 V, see Figure 41 tON (EN) 120 ns typ RL = 300 Ω, CL = 35 pF 140 190 210 ns max VS = 8 V, see Figure 42 tOFF (EN) 130 ns typ RL = 300 Ω, CL = 35 pF 145 195 215 ns max VS = 8 V, see Figure 42 Break-Before-Make Time Delay, tD 35 ns typ RL = 300 Ω, CL = 35 pF 15 ns min VS1 = VS2 = 8 V, see Figure 40 Charge Injection, QINJ −0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 43 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 p F, f = 1 MHz, see Figure 34 Channel to Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz, see Figure 33

Data Sheet ADGS1208/ADGS1209 Rev. 0 | Page 7 of 33 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments −3 dB Bandwidth RL = 50 Ω, CL = 5 pF , see Figure 37 ADGS1208 450 MHz typ ADGS1209 550 MHz typ Insertion Loss −12 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz, see Figure 37 CS (Off ) 1.2 pF typ VS = 0 V, f = 1 MHz 1.8 pF max VS = 0 V, f = 1 MHz CD (Off ) ADGS1208 6 pF typ VS = 0 V, f = 1 MHz 6.5 pF max VS = 0 V, f = 1 MHz ADGS1209 3.2 pF typ VS = 0 V, f = 1 MHz 4 pF max VS = 0 V, f = 1 MHz CD (On), CS (On) ADGS1208 6 pF typ VS = 0 V, f = 1 MHz 7 pF max VS = 0 V, f = 1 MHz ADGS1209 4 pF typ VS = 0 V, f = 1 MHz 4.5 pF max VS = 0 V, f = 1 MHz POWER REQUIREMENTS VDD = 13.2 V IDD 0.002 µA typ All switches open 1.0 µA max 220 µA typ All switches closed, VL = 5.5 V 380 µA max 270 µA typ All switches closed, VL = 2.7 V 440 µA max IL Inactive 6.3 µA typ Digital inputs = 0 V or VL 8.0 µA max Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 7 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 210 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V 7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V 120 µA typ CS and SCLK = 0 V or VL, VL = 3 V Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V 2.1 mA max 0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V 1.0 mA max VDD 5 V min GND = 0 V, VSS = 0 V

16.5 V max GND = 0 V, VSS = 0 V

1 Guaranteed by design; not subject to production test.

Table 3. ADGS1208, One Channel On 1 Sx refers to the S1 to S8 pins. Table 4. ADGS1209, Two Channels On 1 Sx refers to the S1A to S4A and S1B to S4B pins, and Dx refers to the DA and DB pins.

1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Figure 3. Address Mode Timing Diagram

TA = 25°C, unless otherwise noted. 1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins. Only one absolute maximum rating can be applied at any one time. PCB thermal design is required. Table 7. Thermal Resistance 1 θJCB is the junction to the bottom of the case value.

2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with four thermal vias. See JEDEC JESD51.

1. THE EXPOSED PAD IS CONNECTED INTERNALLY.

THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS.

1. NIC = NOT INTERNALLY CONNECTED.

22 SCLK

23 SDI

24 GPO4

Figure 7. ADGS1208 Pin Configuration Table 8. ADGS1208 Pin Function Descriptions 1 GPO1 General-Purpose Output 1. This pin is a digital output. 2 GPO2 General-Purpose Output 2. This pin is a digital output. 3 VSS Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. 4 S1 Source Terminal 1. This pin can be an input or output. 5 S2 Source Terminal 2. This pin can be an input or output. 6 S3 Source Terminal 3. This pin can be an input or output. 7 S4 Source Terminal 4. This pin can be an input or output. 8, 10 NIC Not Internally Connected. These pins are not connected internally. 9 D Drain Terminal. This pin can be an input or output. 11 S8 Source Terminal 8. This pin can be an input or output. 12 S7 Source Terminal 7. This pin can be an input or output. 13 S6 Source Terminal 6. This pin can be an input or output. 14 S5 Source Terminal 5. This pin can be an input or output. 15 VDD Most Positive Power Supply Potential. 16 GND Ground (0 V) Reference. 17 CNV Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels. 18 GPO3 General-Purpose Output 3. This pin is a digital output. SCLK. Pull this open-drain output to VL with an external resistor. 20 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. registers are set to their default values. 21 CS Active Low Control Input. CS is the frame synchronization signal for the input data. 22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. 23 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input. 24 GPO4 General-Purpose Output 4. This pin is a digital output. maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.

1. THE EXPOSED PAD IS CONNECTED INTERNALLY.

THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS.

1. NIC = NOT INTERNALLY CONNECTED.

Figure 8. ADGS1209 Pin Configuration Table 9. ADGS1209 Pin Function Descriptions 1 GPO1 General-Purpose Output 1. This pin is a digital output. 2 GPO2 General-Purpose Output 2. This pin is a digital output. 3 VSS Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. 4 S1A Source Terminal 1A. This pin can be an input or output. 5 S2A Source Terminal 2A. This pin can be an input or output. 6 S3A Source Terminal 3A. This pin can be an input or output. 7 S4A Source Terminal 4A. This pin can be an input or output. 8 NIC Not Internally Connected. This pin is not internally connected. 9 DA Drain Terminal A. This pin can be an input or output. 10 DB Drain Terminal B. This pin can be an input or output. 11 S4B Source Terminal 4B. This pin can be an input or output. 12 S3B Source Terminal 3B. This pin can be an input or output. 13 S2B Source Terminal 2B. This pin can be an input or output. 14 S1B Source Terminal 1B. This pin can be an input or output. 15 VDD Most Positive Power Supply Potential. 16 GND Ground (0 V) Reference. 17 CNV Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels. 18 GPO3 General-Purpose Output 3. This pin is a digital output. SCLK. Pull this open-drain output to VL with an external resistor. 20 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. registers are set to their default values. 21 CS Active Low Control Input. CS is the frame synchronization signal for the input data. 22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. 23 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input. 24 GPO4 General-Purpose Output 4. This pin is a digital output. maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.

Figure 21. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency, Figure 22. THD + N vs. Frequency Figure 23. ADGS1208 Insertion Loss vs. Frequency, ±15 V Dual Supply Figure 24. ADGS1209 Insertion Loss vs. Frequency, ±15 V Dual Supply Figure 25. ADG1208 Capacitance vs. Source Voltage, ±15 V Dual Supply Figure 26. ADG1208 Capacitance vs. Source Voltage,

Data Sheet ADGS1208/ADGS1209 Rev. 0 | Page 21 of 33 TERMINOLOGY IDD IDD is the positive supply current. ISS ISS is the negative supply current. VD, VS VD and VS are the analog voltage on Terminal Dx and Terminal Sx, respectively. RON RON is the ohmic resistance between Terminal Dx and Terminal Sx. ∆RON ∆RON is the difference between the RON of any two channels. RFLAT (ON) RFLAT (ON) is flatness that is the difference between maximum and minimum on resistance values measured over the specified analog signal range. IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. IS (On), ID (On) IS (On) and ID (On) are the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH are the low and high input currents of the digital inputs, respectively. CS (Off) CS (Off) is the off switch source capacitance, which is measured with reference to ground. CD (Off) CD (Off) is the off switch drain capacitance, which is measured with reference to ground. CS (On), CD (On) CS (On) and CD (On) are the on switch capacitances, which are measured with reference the ground. CIN CIN is the digital input capacitance. tON tON is the delay between applying the digital control input and the output switching on. tOFF tOFF is the delay between applying the digital control input and the output switching off. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. −3 dB Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) THD + N is the ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. ACPSRR is a measure of the ability of the devices to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

control another device, which in this example is the ADG758.

1 OF 8

Figure 54. ADGS1208 Device Controlling the ADG758

this current draw, refer to the Specifications section and Figure 31. load on the output of the multiplexer. 0.1 µF decoupling capacitors are required. The voltage range that can be supplied to VL is from 2.7 V to 5.5 V. An example of a bipolar power solution is shown in Figure 55. ADP5070 in ultralow noise sensitive applications. to power digital circuitry within the ADGS1208/ADGS1209. Figure 55. Bipolar Power Solution Table 10. Recommended Power Management Devices

Table 11. ADGS1208 Register Summary Table 12. ADGS1209 Register Summary

outputs. Use the ADGS1208/ADGS1209 truth tables in conjunction with the bit descriptions. Table 13. Bit Descriptions for SW_DATA in the ADGS1208 Table 14. Bit Descriptions for SW_DATA ADGS1209 Table 15. ADGS1208 Truth Table

Table 16. ADGS1209 Truth Table The error configuration register allows the user to enable and disable the relevant error features as required. Table 17. Bit Descriptions for ERR_CONFIG 1 SCLK_ERR_EN Enable bit for detecting the correct number of SCLK cycles in an SPI frame.

16 SCLK cycles are expected when CRC is disabled and burst mode is

expected when CRC is enabled and burst mode is enabled. must include the correct CRC byte during the SPI write for the clear error flags register command to succeed. Table 18. Bit Descriptions for ERR_FLAGS when the target address of an SPI write does not exist or is read only.

1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in an SPI

commands without deasserting CS. Table 19. Bit Descriptions for BURST_EN enabled in the round robin configuration register by presenting the relevant edge on the CNV pin. Table 20. Bit Descriptions for ROUND_ROBIN_EN robin mode, the channels are cycled through in ascending order. Table 21. Bit Descriptions for RROBIN_CHANNEL_CONFIG (ADGS1208) 0 S8 disabled during round robin mode. 1 S8 enabled during round robin mode. 0 S7 disabled during round robin mode. 1 S7 enabled during round robin mode. 0 S6 disabled during round robin mode. 1 S6 enabled during round robin mode. 0 S5 disabled during round robin mode. 1 S5 enabled during round robin mode. 0 S4 disabled during round robin mode. 1 S4 enabled during round robin mode. 0 S3 disabled during round robin mode. 1 S3 enabled during round robin mode.

0 S2 disabled during round robin mode. 1 S2 enabled during round robin mode. 0 S1 disabled during round robin mode. 1 S1 enabled during round robin mode. Table 22. Bit Descriptions for RROBIN_CHANNEL_CONFIG (ADGS1209) 0 S4 disabled during round robin mode. 1 S4 enabled during round robin mode. 0 S3 disabled during round robin mode. 1 S3 enabled during round robin mode. 0 S2 disabled during round robin mode. 1 S2 enabled during round robin mode. 0 S1 disabled during round robin mode. 1 S1 enabled during round robin mode. The CNV edge select register allows the user to select the active edge of the CNV pin when the device is in round robin mode. Table 23. Bit Descriptions for CNV_EDGE_SEL 0 Falling edge of CNV is the active edge. 1 Rising edge of CNV is the active edge. the device reset to their default state. Table 24. Bit Descriptions for SOFT_RESETB

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.