ADGM3121 AD | Alldatasheet
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Technical content
3mm × 3mm DPDT MEMS Switch, 0Hz/DC to 24GHz Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
►−3dB frequency bandwidth: ►RF1A and RF1B: 24GHz ►RF2A and RF2B: 22GHz ►High bit rate capability up to 64Gbps ►RF performance characteristics ►Channel RF1A and Channel RF1B: ►Insertion loss: 0.5dB (typical) at 6GHz ►Return loss: 24dB (typical) at 6GHz ►Isolation: 24dB (typical) at 6GHz ►Channel RF2A and Channel RF2B: ►Insertion loss: 0.4dB (typical) at 6GHz ►Return loss: 29dB (typical) at 6GHz ►Isolation: 26dB (typical) at 6GHz ►High input IIP3: 70dBm (typical) ►High RF power handling: 33dBm (maximum) ►On resistance: 1.9Ω (typical) ►High DC current handling: 200mA ►High switch cycle count: 100 million cycles (minimum at +85°C) ►Fast switching time: 200µs TON (maximum) ►Integrated 3.3V driver for simple control with parallel interface and SPI ►Space saving integrated passive shunt resistors ►Small 3mm × 3mm × 1.5mm, 24-lead land grid array package ►Temperature range: −40°C to +85°C
APPLICATIONS
►ATE load and probe boards ►DC with high speed loopback testing ►Supports digital standards: high speed serialization/deserializa- tion, PCIe Gen4/Gen5/Gen6, USB 4, and PAM 4 ►Relay replacements ►Reconfigurable filters and attenuators ►Military and microwave radios ►Cellular infrastructure: 5G mmWave FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram ADGM3121 refer to the Critical Operational Requirements section.
analog.com Rev. 0 | 2 of 33 Pin Electronics (PE) and Parametric Measurement Unit (PMU) Signal Switching... 26 General RF, DC, and Mixed Signal Switching..27 System Error Considerations Due to On-Resistance Shift Due To Temperature
REVISION HISTORY
12/2025—Revision 0: Initial Version
VDD = 3.0V to 3.6V, GND = 0V, and all specifications at 25°C, unless otherwise noted. Table 1. Specifications
Table 1. Specifications (Continued)
1 Typical specifications tested at 25°C with VDD = 3.3V. 2 RFxx is RF1A, RF1B, RF2A, and RF2B. RFCx is RFCA or RFCB. INx is IN1, IN2, IN3, and IN4. 3 This value shows the time it takes for 1% of a sample lot to fail. 4 Switch is settled after 200µs. Do not apply RF power between 0µs to 200µs. 5 RF power should be removed or less than 5dBm, 50µs before turning the switch off. all the RF nodes to avoid floating nodes.
VDD = 3.0V to 3.6V, GND = 0V and all specifications TMIN to TMAX, unless otherwise noted. Table 2. Timing Characteristics 1 Measured with a 20pF load. t9 determines the maximum SCLK frequency when SDO is used. Figure 2. Addressable Mode Timing
TA = 25°C, unless otherwise noted. Table 3. Absolute Maximum Ratings 1 Limit the current to the maximum ratings shown.
2 This rating is with respect to the switch in the on position with no RF signal
3 This rating is with respect to the switch in the off position with no RF signal
4 This rating is with respect to the switch in the on position and terminated into
5 If a device is dropped during handling, do not use the device. ing conditions for extended periods may affect product reliability. Only one absolute maximum rating may be applied at any one time. measured in a one cubic foot sealed enclosure. θJCT is the junction to the top of the case thermal resistance. θJCB is the junction to the bottom of the case thermal resistance. Table 4. Thermal Resistance ESD-sensitive devices in an ESD-protected area only. Human body model (HBM) as per ANSI/ESDA/JEDEC JS-001. Table 5. ADGM3121, 24-Lead LGA
1 Take proper precautions during handling, as outlined in the Handling Precau-
2 RFxx is RF1A, RF1B, RF2A, and RF2B. RFCx is RFCA and RFCB.
3 A safe automated handling and assembly process is achieved at this rating
level by implementing industry standard ESD controls. devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.
Figure 6. ADGM3121 Pin Configuration Table 6. Pin Function Descriptions as close to this pin as possible. The decoupling capacitor should be rated to at least 16V DC. IN2, IN3, IN4) is enabled when this pin is low. 20 IN1/SDO Parallel Logic Digital Control Input 1. The voltage applied to this pin controls the gate of the RF1A to RFCA MEMS switch. In SPI mode, this pin is the serial data output (SDO) pin. 21 IN2/SCLK Parallel Logic Digital Control Input 2. The voltage applied to this pin controls the gate of the RF2A to RFCA MEMS switch. In SPI mode, this pin is the serial clock (SCLK) pin that synchronizes the target device(s) to the controller device. 22 IN3/CS Parallel Logic Digital Control Input 3. The voltage applied to this pin controls the gate of the RF2B to RFCB MEMS switch. controller device intends to communicate. 23 IN4/SDI Parallel Logic Digital Control Input 4. The voltage applied to this pin controls the gate of the RF1B to RFCB MEMS switch. In SPI mode, this pin is the serial data input (SDI) pin. close to this pin as possible. The decoupling capacitor should be rated to at least 100V DC. EP Exposed Pad. EP is internally connected to GND. Connect this pad to GND.
measurements taken using the test circuit in Figure 64.
10 OF F I SO / 20 − 1 (2)
RL is the 50 Ω load resistance. OFFISO is the measured off isolation. Figure 64. Off Isolation Measurement Test Circuit and CDS(OFF) Derivation
ed for demanding RF applications. used for actuation of the switch. The ADGM3121 can be controlled through a parallel interface. of all the switch channels of the ADGM3121. Setting Pin 19 (PIN/SPI) low enables the parallel control interface. applied to one of these pins, the corresponding switch turns on. Table 7 for the truth table. Table 7. Truth Table in Parallel Digital Interface Mode
Table 10. Register Summary
The switch data register controls the status of the four switches of the ADGM3121. Table 11. Bit Descriptions for SWITCH_DATA
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