ADGM1001

ADGM1001/ADGM1002/ADGM1003 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 33

Technical content

ADGM1001/ADGM1002/ADGM1003

0 Hz/DC to 34 GHz, SPDT MEMS Switches

Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►ADGM1001: DC to 34 GHz ►ADGM1002: DC to 20 GHz ►ADGM1003: DC to 16 GHz ►Insertion loss (ADGM1001) ►0.8 dB (typical) at 18 GHz ►1.5 dB (typical) at 34 GHz ►IIP3: 76 dBm (typical) (ADGM1001) ►Maximum RF power: 33 dBm (ADGM1001) ►On resistance: 3.4 Ω (typical) ►Maximum dc current: 200 mA (ADGM1001) ►Actuation lifetime: 100 million cycles (minimum) ►On switching time (tON): 200 µs (typical) ►Integrated 3.3 V driver for simple control with parallel and SPI ►Independently controllable switches ►Space-saving integrated passive components ►Small, 5.00 mm × 4.00 mm × 0.90 mm, 24-lead LGA package ►Temperature range: –40°C to +85°C

APPLICATIONS

►ATE load and probe boards ►DC and high speed loop back testing ►Relay replacements ►Reconfigurable filters and attenuators ►Military and microwave radios ►Cellular infrastructure: 5G mmWave ►Supports digital standards: PCIe Gen4/Gen5/Gen6, USB 3 and USB 4, and PAM 4 FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADGM1001 is a wideband, single-pole, two-throw (SP2T) switch, fabricated using Analog Devices, Inc., micro-electromechan- ical system (MEMS) switch technology. This technology enables a small form factor, wide RF bandwidth, highly linear, low insertion loss switch that is operational down to 0 Hz/dc, making it an ideal solution for a wide range of RF and precision equipment switching needs. The device is packaged in a 24-lead, 5.00 mm × 4.00 mm × 0.90 mm, land grid array (LGA) package. An integrated control chip generates the high voltage necessary to electrostatically actuate the switch via a complementary metal-ox- ide semiconductor (CMOS)-/low voltage transistor-transistor logic (LVTTL)-compatible parallel interface. All switches are independent- ly controllable. Multifunction pin names may be referenced by their relevant func- tion only. Table 1. ADGM1001/ADGM1002/ADGM1003 Key Specifications

Data Sheet ADGM1001/ADGM1002/ADGM1003 TABLE OF CONTENTS analog.com Rev. A | 2 of 33 ADGM1001/ADGM1002 Typical ADGM1003 Typical Performance System Error Considerations Due to On-Resistance Shift due to Temperature

REVISION HISTORY

2/2023—Rev. 0 to Rev. A 3/2022—Revision 0: Initial Version

VDD = 3.0 V to 3.6 V, AGND and RFGND = 0 V, and all specifications are at TA = 25°C, unless otherwise noted. Table 2. ADGM1001/ADGM1002/ADGM1003 1 Typical specifications tested at 25°C with VDD = 3.3 V. 2 RFx is RF1 or RF2. INx is IN1 or IN2. 3 Switch is settled after 200 μs. Do not apply RF power between 0 µs to 200 µs. 4 RF power must be removed or less than 5 dBm, 50 µs prior to turning the switch off.

5 Disable the internal oscillator to eliminate feedthrough. 7 For more details, see the Low Power Mode section. 8 For more details, see the Internal Oscillator Feedthrough Mitigation section. Table 3. ADGM1001

0.5 V or 9 mA 1 × 109 Actuations

1 V or 18 mA 650 × 106 Actuations

2.5 V or 46 mA 55 × 103 Actuations

Table 3. ADGM1001 (Continued)

3570 MHz, PIN = 30 dBm

1 Typical specifications tested at 25°C with VDD = 3.3 V. 2 RFx is RF1 or RF2. INx is IN1 or IN2. 3 This value shows the time it takes for 1% of a sample lot to fail.

Table 4. ADGM1002

Table 4. ADGM1002 (Continued)

3570 MHz, and PIN = 30 dBm

1 Typical specifications tested at 25°C with VDD = 3.3 V. 2 RFx is RF1 or RF2. INx is IN1 or IN2. 3 This value shows the time it takes for 1% of a sample lot to fail. Table 5. ADGM1003

Table 5. ADGM1003 (Continued) 1 Typical specifications tested at 25°C with VDD = 3.3 V. 2 RFx is RF1 or RF2. INx is IN1 or IN2. 3 This value shows the time it takes for 1% of a sample lot to fail.

characterization, not production tested. 1 Measured with a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Figure 2. Addressable Mode Timing Diagram

2 This rating is applied when the switch in the on position with no RF signal

3 This rating is with respect to the switch in the off position with no RF signal

4 This rating is with respect to the switch in the on position and terminated into

5 If a device is dropped during handling, do not use the device. ing conditions for extended periods may affect product reliability. Only one absolute maximum rating may be applied at any one time. measured in a one cubic foot sealed enclosure. θJCT is the junction to the top of the case thermal resistance. θJCB is the junction to the bottom of the case thermal resistance. Table 8. Thermal Resistance sitive devices in and ESD-protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 9. ADGM1001/ADGM1002/ADGM1003, 24-Lead LGA

150 V for the RF1, RF2, and RFC pins

1 Take proper precautions during handling as outlined in the Handling Precau-

2 A safe automated handling and assembly process is achieved at this rating

level by implementing industry-standard ESD controls. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 6. Pin Configuration Table 10. Pin Function Descriptions mode, this is the serial data input pin (SDI). mode, this is the chip select pin (CS). 3 AGND/SCLK In parallel logic control mode, the AGND pin must be connected to ground. In SPI mode, this is the serial clock input pin (SCLK). 4 AGND/SDO In parallel logic control mode, the AGND pin must be connected to ground. In SPI mode, this is the serial data output pin (SDO). 5, 8, 22 AGND Analog Ground Connection (Recommended to Connect AGND and RFGND Together). the logic interface pins (IN1 and IN2), but the VCP pin must be driven with 80 V dc from an external voltage supply. RFGND RF Ground Connection (Recommended to Connect AGND and RFGND Together). with a 50 Ω resistor to RFGND. 15 RFC Common RF Port. The RFC pin can be an input or an output. with a 50 Ω resistor to RFGND. are in an indeterminate state. disables, and an 80 V dc voltage must be input into VCP to drive the switches via the logic interface. EP1 Exposed Pad 1. EP1 is internally connected to AGND. Connect EP1 to AGND or to both AGND and RFGND. EP2 Exposed Pad 2. EP2 is internally connected to RFGND. Connect EP2 to RFGND or to both RFGND and AGND.

Figure 53. Addressable Mode Timing Diagram (Mode 3)

Data Sheet ADGM1001/ADGM1002/ADGM1003 THEORY OF OPERATION analog.com Rev. A | 24 of 33 Hardware Reset The digital section of the ADGM1001 goes through an initialization phase during VDD power-up. To hardware reset the device, power cycle the VDD input. After power-up or a hardware reset, ensure that there is a minimum of 10 µs from the power-up or reset time before any SPI command is issued. Ensure that VDD does not drop out during the 10 µs initialization phase because it may result in incorrect operation of the ADGM1001. Internal Error Status When an internal error is detected in the ADGM1001, it is flagged in the internal error status bits (INTERNAL_ERROR, Bits[7:6]) of the SWITCH_DATA register. An internal error results from an error in the configuration of the device at power-up. INTERNAL OSCILLATOR FEEDTHROUGH The ADGM1001 has an internal oscillator running at a nominal 10 MHz. This oscillator drives the charge pump circuitry that pro- vides the actuation voltage for each of the switch gate electrodes. Although this oscillator is low power, the 10 MHz signal is coupled to the switch and can be considered a noise spur on the switch channels. The magnitude of this feedthrough noise spur is specified in Table 2 and is typically −123 dBm when one switch is on. VDD level and temperature changes affect the frequency of the noise spur. For the maximum and minimum frequency range over temperature and voltage supply range, see Table 2. INTERNAL OSCILLATOR FEEDTHROUGH MITIGATION In normal operation, the 80 V actuation voltage is supplied by the driver IC. Setting the EXTD_EN pin (Pin 7) low enables the built-in 10 MHz oscillator. This setting enables the charge pump circuitry to generate the 80 V required for MEMS switch actuation. The internal oscillator is a source of noise, which couples through to the RF ports. The magnitude of this feedthrough noise spur is specified in Table 2 and is typically −123 dBm when one switch is on. The internal oscillator feedthrough can be eliminated by setting the EXTD_EN pin high, which disables the internal oscillator and charge pump circuitry. When the internal oscillator and charge pump circuitry is disabled, the VCP pin (Pin 24) must be driven with

80 V dc (VCPEXT) from an external voltage supply, as outlined in

Table 10, which is required for MEMS switch actuation. The switch can still be controlled via the digital logic interface pins. LOW POWER MODE Setting the EXTD_EN pin high shuts down the internal oscillator. The ADGM1001 enters a low power quiescent state, drawing only 50 µA maximum supply current. TYPICAL OPERATING CIRCUIT Figure 56 shows the typical operating circuit for the ADGM1001 as used in the EV-ADGM1001SDZ evaluation board. VDD is connected to 3.3 V. No decoupling capacitor is required on the VDD pin (Pin 23). The VDD pin has an internal decoupling capacitor connected to ground in the package. RFGND is separated from AGND internally in the device. It is recommended to connect RFGND to AGND using one large pad on the PCB to short together EP1 and EP2. EP1 and EP2 are not connected internally. Figure 56 shows the ADGM1001 configured to use the internal oscillator as the reference clock to the driver IC control circuit. Alternatively, set the EXTD_EN pin (Pin 7) high and apply 80 V dc directly to the VCP pin (Pin 24) to disable the internal oscillator and eliminate all oscillator feedthrough. The switches can then be controlled as normal via the logic control interface, IN1 and IN2 (Pin 1 and Pin 2).

Figure 56. ADGM1001 Typical Operating Circuit in Parallel Digital Interface Mode

The device is fully specified at a 3.3 V analog supply voltage. to meet the requirements of most high performance signal chains. other devices in the signal chain. Figure 57. Unipolar Power Solution ADP7142 can be replaced by the LT1962 or the LT3045-1. Table 12. Recommended Power Management Devices is analyzed to calculate the bit error rate (BER). a dc instrument where the dc measurement of the pin is executed.

34 GHz, which allows the switch to handle both high speed signals

up to 64 Gbps and precision dc signals. Figure 58. ADGM1001 Enabling Both High Speed Digital and DC Testing the quality of an attenuator network. channel is used for a non attenuated route. Figure 59. Switching RF Attenuators Using ADGM1001 MEMS Switches

impact the RF performance of the ADGM1001. Figure 71. Solder Stencil Recommendation for ADGM1001

Table 14. Register Summary

The switch data register controls the status of the two switches of the ADGM1001. Table 15. Bit Descriptions for SWITCH_DATA

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A.

0.70 REF

2.15 BSC

Figure 72. 24-Lead Land Grid Array [LGA]