ADG888BCBZ-REEL

ADG888 AD | Alldatasheet

Document overview

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Technical content

0.4 Ω CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP Packages ADG888 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

1.8 V to 5.5 V operation Ultralow on resistance 0.4 Ω typical 0.6 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion 0.07 Ω typical 0.14 Ω maximum R ON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V Automotive temperature range: −40°C to +125°C Rail-to-rail switching operation Typical power consumption (<0.1 μW)

APPLICATIONS

Audio and video signal routing Communication systems Data switching FUNCTIONAL BLOCK DIAGRAM ADG888 IN1 S2B S2A S1B S1A IN2 S4B S4A S3B S3A 05432-001 SWITCHES SHOWN FOR A LOGIC 1 INPUT Figure 1. GENERAL DESCRIPTION The ADG888 is a low voltage, dual DPDT (double-pole, double-throw) CMOS device optimized for high performance audio switching. With its low power and small physical size, it is ideal for portable devices. This device offers ultralow on resistance of less than 0.8 Ω over the full temperature range, making it an ideal solution for applications requiring minimal distortion through the switch. The ADG888 also has the capability of carrying large amounts of current, typically 400 mA at 5 V operation. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG888 exhibits break-before-make switching action. The ADG888 is available in a 16-ball WLCSP , 16-lead LFCSP , and a 16-lead TSSOP . These packages make the ADG888 the ideal solution for space-constrained applications. PRODUCT HIGHLIGHTS 1. <0.6 Ω over full temperature range of −40°C to +125°C. 2. High current handling capability (400 mA continuous current at 5 V). 3. Low THD + N (0.008% typical). 4. Tiny 16-ball WLCSP , 16-lead LFCSP , and 16-lead TSSOP .

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

12/06—Rev. 0 to Rev. A 7/05—Revision 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS VDD = 4.2 V to 5.5 V , GND = 0 V , unless otherwise noted. Table 1. Parameter +25°C B Version1 Y Version1 Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance (RON) 0.4 Ω typ VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA 0.48 0.55 0.6 Ω max See Figure 16 On Resistance Match Between Channels (∆RON) 0.04 Ω typ VDD = 4.2 V, VS = 2.2 V, IDS = 100 mA 0.06 0.07 0.075 Ω max On Resistance Flatness (RFLAT (ON)) 0.07 Ω typ VDD = 4.2 V, VS = 0 V to VDD 0.11 0.13 0.14 Ω max IDS = 100 mA LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage IS (Off ) ±0.2 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 17 Channel On Leakage ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 4.5 V; see Figure 18 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max CIN, Digital Input Capacitance 2 pF typ DYNAMIC CHARACTERISTICS2 tON 22 ns typ RL = 50 Ω, CL = 35 pF 30 33 35 ns max VS = 3 V/0 V; see Figure 19 tOFF 13 ns typ RL = 50 Ω, CL = 35 pF 17 18 19 ns max VS = 3 V/0 V; see Figure 19 Break-Before-Make Time Delay (tBBM) 9 ns typ RL = 50 Ω, CL = 35 pF 5 ns min VS1 = VS2 = 3 V; see Figure 20 Charge Injection 70 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 21 Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22 Channel-to-Channel Crosstalk −99 dB typ Adjacent channel; RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 −67 dB typ Adjacent switch; RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 23 Total Harmonic Distortion (THD + N) 0.008 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3 V p-p Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 24 −3 dB Bandwidth 29 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24 CS (Off ) 58 pF typ CD, CS (On) 110 pF typ POWER REQUIREMENTS VDD = 5.5 V IDD 0.003 μA typ Digital inputs = 0 V or 5.5 V 1 4 μA max 1 Temperature range for the Y version is −40°C to +125°C for the TSSOP and LFCSP; temperature range for the B version is −40°C to +85°C for the WLCSP. 2 Guaranteed by design, not production tested.

Rev. A | Page 4 of 16 VDD = 2.7 V to 3.6 V , GND = 0 V , unless otherwise noted. Table 2. Parameter +25°C B Version1 Y Version1 Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance (RON) 0.5 Ω typ VDD = 2.7 V, VS = 0 V to VDD 0.7 0.75 0.8 Ω max IS = 100 mA; see Figure 16 On Resistance Match Between Channels (∆RON) 0.045 Ω typ VDD = 2.7 V, VS = 1 V 0.072 0.077 0.083 Ω max IS = 100 mA On Resistance Flatness (RFLAT (ON)) 0.16 Ω typ VDD = 2.7 V, VS = 0 V to VDD 0.262 Ω max IS = 100 mA LEAKAGE CURRENTS VDD = 3.6 V Source Off Leakage IS (Off ) ±0.2 nA typ VS = 1 V/2.6 V, VD = 2.6 V/1 V; see Figure 17 Channel On Leakage ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 2.6 V; see Figure 18 DIGITAL INPUTS Input High Voltage, VINH 1.3 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max CIN, Digital Input Capacitance 2 pF typ DYNAMIC CHARACTERISTICS2 tON 28 ns typ RL = 50 Ω, CL = 35 pF; see Figure 19 43 47 50 ns max VS = 1.5 V/0 V tOFF 13 ns typ RL = 50 Ω, CL = 35 pF; see Figure 19 20 21 22 ns max VS = 1.5 V/0 V Break-Before-Make Time Delay (tBBM) 14 ns typ RL = 50 Ω, CL = 35 pF 5 ns min VS1 = VS2 = 1.5 V; see Figure 20 Charge Injection 50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 21 Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22 Channel-to-Channel Crosstalk −99 dB typ Adjacent channel; RL = 50 V, CL = 5 pF, f = 100 kHz; see Figure 25 −67 dB typ Adjacent switch; RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 23 Total Harmonic Distortion (THD + N) 0.01 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1 V p-p Insertion Loss −0.04 dB typ RL = 50 Ω, CL = 5 pF; see Figure 24 –3 dB Bandwidth 29 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24 CS (Off ) 60 pF typ CD, CS (On) 115 pF typ POWER REQUIREMENTS VDD = 3.6 V IDD 0.003 μA typ Digital inputs = 0 V or 3.6 V 1 2 μA max 1 Temperature range for the Y version is −40°C to +125°C for the TSSOP and LFCSP; temperature range for the B version is −40°C to +85°C for the WLCSP. 2 Guaranteed by design, not production tested.

Rev. A | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND −0.3 V to +6 V Analog Inputs, Digital Inputs1 −0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Peak Current, S or D

5 V operation 600 mA (pulsed at 1 ms,

10% duty cycle max) Continuous Current, S or D

5 V operation 400 mA

Operating Temperature Range Automotive (Y Version) TSSOP and LFCSP packages −40°C to +125°C Industrial (B version) WLCSP package −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP Package θJA Thermal Impedance (4-Layer Board) 112°C/W θJC Thermal Impedance 27.6°C/W 16-Lead WLCSP Package θJA Thermal Impedance (4-Layer Board) 130°C/W 16-Lead LFCSP Package θJA Thermal Impedance (4-Layer Board) 30.4°C/W Reflow Soldering (Pb-Free) Peak Temperature 260(+0/−5)°C Time at Peak Temperature 10 sec to 40 sec 1 Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION

Figure 2. 16-Ball WLCSP

11 S4B

10 S3B

Figure 3. 16-Lead LFCSP Figure 4. 16-Lead TSSOP Table 4. Pin Function Descriptions 2C 15 1 VDD Most Positive Power Supply Potential. 2B 14 16 GND Ground (0 V) Reference. 1A, 1D, 4A, 4D 1, 4, 9, 12 3, 6, 11, 14 D Drain Terminal. Can be an input or output. 3B, 3C 6, 7 8, 9 IN Logic Control Input. Table 5. Truth Table

0 Off On

1 On Off

Rev. A | Page 11 of 16 TERMINOLOGY IDD Positive supply current. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. ΔRON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. This is specified for two conditions:

• Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A to S4A, or S3B to S4B.
• Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A to S3B, or S4A to S4B. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitudes plus signal noise to the fundamental.

Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP] Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP]

1.95 BSC

0.80 SEATING

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.65 BSC

0.60 MAX

Figure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. A | Page 13 of 16 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding1 ADG888YRUZ2 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG888YRUZ-REEL2 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG888YRUZ-REEL72 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG888YCPZ-REEL2 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4 S0D ADG888YCPZ-REEL72 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4 S0D ADG888BCBZ-REEL2 −40°C to +85°C 16-Ball Wafer Level Chip Scale Package [WLCSP] CB-16 S02 ADG888BCBZ-REEL72 −40°C to +85°C 16-Ball Wafer Level Chip Scale Package [WLCSP] CB-16 S02 EVAL-ADG888EB Evaluation Board 1 Branding on these packages is limited to three characters due to space constraints. 2 Z = Pb-free part.

Rev. A | Page 14 of 16 NOTES

Rev. A | Page 15 of 16 NOTES

Rev. A | Page 16 of 16 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05432-0-12/06(A)