ADG884BCBZ-500RL7

ADG884 AD | Alldatasheet

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Technical content

0.5 Ω CMOS, Dual 2:1 MUX/SPDT Audio Switch ADG884 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

FEATURES

1.8 V to 5.5 V operation Ultralow on resistance 0.34 Ω typ 0.38 Ω max at 5 V supply Excellent audio performance, ultralow distortion 0.1 Ω typ 0.15 Ω max RON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V supply Rail-to-rail switching operation Typical power consumption (<0.1 μW)

APPLICATIONS

Audio and video signal routing Communications systems FUNCTIONAL BLOCK DIAGRAM 05028-001 S1A S1B S2A S2B IN2 ADG884 SWITCHES SHOWN FOR A LOGIC 1 INPUT IN1 Figure 1. GENERAL DESCRIPTION The ADG884 is a low voltage CMOS device containing two independently selectable single-pole, double-throw (SPDT) switches. This device offers ultralow on resistance of less than 0.4 Ω over the full temperature range, making the part an ideal solution for applications that require minimal distortion through the switch. The ADG884 also has the capability of carrying large amounts of current, typically 600 mA at 5 V operation. The ADG884 is available in a 10 bump, 2.0 mm × 1.50 mm WLCSP package, a 10-lead LFCSP package, and a 10-lead MSOP package. These tiny packages make the ADG884 the ideal solution for space-constrained applications. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG884 exhibits break-before-make switching action. PRODUCT HIGHLIGHTS 1. Single 1.8 V to 5.5 V operation. 2. High current handling capability (400 mA continuous current at 3.3 V). 3. 1.8 V logic-compatible. 4. Low THD + N (0.01% typ). 5. Tiny 2 mm × 1.5 mm WLCSP package, 3 mm × 3 mm 10-lead LFCSP package, and 10-lead MSOP package. Table 1. ADG884 Truth Table

0 Off On

1 On Off

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

6/05—Rev. 0 to Rev. A 10/04—Revision 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V , unless otherwise noted.1 Table 2. Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 0.28 Ω typ VDD = 4.5 V, VS = 0 V to VDD, IS = 100 mA 0.34 0.38 Ω max See Figure 18 On Resistance Match Between 0.01 Ω typ VDD = 4.5 V, VS = 2 V, IS = 100 mA Channels, ∆RON 0.035 0.05 Ω max On Resistance Flatness, RFLAT (ON) 0.1 Ω typ VDD = 4.5 V, VS = 0 V to VDD 0.13 0.15 Ω max IS = 100 mA LEAKAGE CURRENTS VDD = 5.5 V Channel On Leakage, ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 4.5 V; see Figure 20 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 42 ns typ RL = 50 Ω, CL = 35 pF 50 53 ns max VS = 3 V/0 V; see Figure 21 tOFF 15 ns typ RL = 50 Ω, CL = 35 pF 20 21 ns max VS = 3 V; see Figure 21 Break-Before-Make Time Delay, tBBM 16 ns typ RL = 50 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 1.5 V; see Figure 22 Charge Injection 125 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23 Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 Channel-to-Channel Crosstalk −120 dB typ S1A−S2A/S1B−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 −60 dB typ S1A−S1B/S2A−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Total Harmonic Distortion, THD + N 0.017 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 26 −3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (OFF) 103 pF typ CD, CS (ON) 295 pF typ POWER REQUIREMENTS VDD = 5.5 V IDD 0.003 μA typ Digital inputs = 0 V or 5.5 V 1 μA max 1 Temperature range of the B version is −40°C to +85°C. 2 Guaranteed by design, not subject to production test.

Rev. A | Page 4 of 16 VDD = 3.4 V to 4.2 V; GND = 0 V , unless otherwise noted.1 Table 3. Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 0.33 Ω typ VDD = 3.4 V, VS = 0 V to VDD, IS = 100 mA 0.38 0.45 Ω max See Figure 18 On Resistance Match Between 0.013 Ω typ VDD = 3.4 V, VS = 2 V, IS = 100 mA Channels, ∆RON 0.042 0.065 Ω max On Resistance Flatness, RFLAT (ON) 0.13 Ω typ VDD = 3.4 V, VS = 0 V to VDD 0.155 0.175 Ω max IS = 100 mA LEAKAGE CURRENTS VDD = 4.2 V Channel On Leakage, ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 3.9 V; see Figure 20 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 42 ns typ RL = 50 Ω, CL = 35 pF 50 54 ns max VS = 1.5 V/0 V; see Figure 21 tOFF 15 ns typ RL = 50 Ω, CL = 35 pF 21 24 ns max VS = 1.5 V; see Figure 21 Break-Before-Make Time Delay, tBBM 17 ns typ RL = 50 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 1.5 V; see Figure 22 Charge Injection 100 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23 Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 Channel-to-Channel Crosstalk −120 dB typ S1A−S2A/S1B−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 −60 dB typ S1A−S1B/S2A−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Total Harmonic Distortion, THD + N 0.01 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 26 −3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (OFF) 110 pF typ CD, CS (ON) 300 pF typ POWER REQUIREMENTS VDD = 4.2 V IDD 0.003 μA typ Digital inputs = 0 V or 4.2 V 1 μA max 1 Temperature range of the B version is −40°C to +85°C. 2 Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 16 VDD = 2.7 V to 3.6 V , GND = 0 V , unless otherwise noted.1 Table 4. Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 0.4 Ω typ VDD = 2.7 V, VS = 0 V to VDD 0.5 0.6 Ω max IS = 100 mA; see Figure 18 On Resistance Match Between 0.02 Ω typ VDD = 2.7 V, VS = 0.6 V Channels, ∆RON 0.07 0.1 Ω max IS = 100 mA On Resistance Flatness, RFLAT (ON) 0.18 Ω typ VDD = 2.7 V, VS = 0 V to VDD 0.25 Ω max IS = 100 mA LEAKAGE CURRENTS VDD = 3.6 V Channel On Leakage, ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 3.3 V; see Figure 20 DIGITAL INPUTS Input High Voltage, VINH 1.3 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 42 ns typ RL = 50 Ω, CL = 35 pF 56 62 ns max VS = 1.5 V/0 V; see Figure 21 tOFF 14 ns typ RL = 50 Ω, CL = 35 pF 19 21 ns max VS = 1.5 V; see Figure 21 Break-Before-Make Time Delay, tBBM 24 ns typ RL = 50 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 1.5 V; see Figure 22 Charge Injection 85 pC typ VS = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 23 Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 Channel-to-Channel Crosstalk −120 dB typ S1A−S2A/S1B−S2B, RL = 50 V, CL = 5 pF, f = 100 kHz; see Figure 27 −60 dB typ S1A−S1B/S2A−S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Total Harmonic Distortion, THD + N 0.03 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 26 –3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (OFF) 110 pF typ CD, CS (ON) 300 pF typ POWER REQUIREMENTS VDD = 3.6 V IDD 0.003 μA typ Digital inputs = 0 V or 3.6 V 1 μA max 1 Temperature range of the B version is −40°C to +85°C. 2 Guaranteed by design, not subject to production test.

Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V to +6 V Analog Inputs1 −0.3 V to VDD + 0.3 V Digital Inputs1 −0.3 V to 6 V or 10 mA (whichever occurs first) Peak Current, S or D

5 V Operation 600 mA (pulsed at

1 ms, 10% duty cycle max) Continuous Current, S or D

5 V Operation 400 mA

Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 10-Lead MSOP Package θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/W 10-Lead WLCSP Package (4-Layer Board) θJA Thermal Impedance 120°C/W 10-Lead LFCSP Package (4-Layer Board) θJA Thermal Impedance 76°C/W θJC Thermal Impedance 13.5°C/W IR Reflow, Peak Temperature <20 s 235°C 1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 11 of 16 TERMINOLOGY IDD Positive supply current. VD (VS) Analog voltage on Terminals D, S. RON Ohmic resistance between D and S. RFLAT (ON) The difference between the maximum and minimum values of on resistance as measured on the switch. ΔRON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID (OFF) Drain leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD (OFF) Off switch drain capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection Measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation Measure of unwanted signal coupling through an off switch. Crosstalk Measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. −3 dB Bandwidth Frequency at which the output is attenuated by 3 dB. On Response Frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N Ratio of the harmonics amplitude plus noise of a signal to the fundamental.

0.02 NOM

0.20 REF

0.80 MAX

0.55 TYP

Figure 28. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

1.10 MAX

0.50 BSC

3.00 BSC

4.90 BSC

Figure 29. 10-Lead Mini Small Outline Package [MSOP] Figure 30. 10-Ball Wafer Level Chip Scale Package [WLCSP]

Rev. A | Page 15 of 16 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding1 ADG884BRMZ2 −40°C to +85°C Mini Small Outline Package (MSOP) RM-10 S9C ADG884BRMZ-REEL2 −40°C to +85°C Mini Small Outline Package (MSOP) RM-10 S9C ADG884BRMZ-REEL72 −40°C to +85°C Mini Small Outline Package (MSOP) RM-10 S9C ADG884BCPZ-REEL2 −40°C to +85°C Lead Frame Chip Scale Package (LFCSP_WD) CP-10-9 S9C ADG884BCPZ-REEL72 −40°C to +85°C Lead Frame Chip Scale Package (LFCSP_WD) CP-10-9 S9C ADG884BCBZ-500RL72, 3 −40°C to +85°C Micro Chip Scale Package (WLCSP) CB-10 S0W ADG884BCBZ-REEL2, 3 −40°C to +85°C Micro Chip Scale Package (WLCSP) CB-10 S0W ADG884BCBZ-REEL72, 3 −40°C to +85°C Micro Chip Scale Package (WLCSP) CB-10 S0W 1 Branding on this package is limited to three characters due to space constraints. 2 Z = Pb-free package. 3 Contact Sales for availability; product under development.

Rev. A | Page 16 of 16 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D05028–0–6/05(A)