ADG836 AD | Alldatasheet
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or oth- erwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADG836 0.5 CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUX
FEATURES
0.5 T ypical On Resistance 0.8 Maximum On Resistance at 125°C 1.65 V to 3.6 V Operation Automotive T emperature Range: –40°C to +125°C High Current Carrying Capability: 300 mA Continuous Rail-to-Rail Switching Operation Fast Switching Times <20 ns T ypical Power Consumption (<0.1 W)
APPLICATIONS
Audio and Video Signal Routing Communication Systems GENERAL DESCRIPTION The ADG836 is a low voltage CMOS device containing two independently selectable single-pole, double-throw (SPDT) switches. This device offers ultralow on resistance of less than 0.8 over the full temperature range. The ADG836 is fully specified for 3.3 V, 2.5 V, and 1.8 V supply operation. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG836 exhibits break-before-make switching action. The ADG836 is available in 10-lead MSOP and 3 mm 3 mm 12-lead LFCSP packages. PRODUCT HIGHLIGHTS 1. <0.8 over full temperature range of –40°C to +125°C. 2. Single 1.65 V to 3.6 V operation. 3. Compatible with 1.8 V CMOS logic. 4. High current handling capability (300 mA continuous current at 3.3 V). 5. Low THD + N (0.02% typ). 6. 3 mm 3 mm LFCSP package and 10-lead MSOP package. FUNCTIONAL BLOCK DIAGRAM REV. 0
–2– ADG836–SPECIFICATIONS1 ADG836 –3– –40C –40C Parameter +25C to +85C to +125C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V VDD = 2.7 V On Resistance (RON) 0.5 typ VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA; 0.65 0.75 0.8 max Test Circuit 1 On Resistance Match between 0.04 typ VDD = 2.7 V, VS = 0.65 V, IS = 10 mA Channels ( RON) 0.075 0.08 max On Resistance Flatness (RFLAT (ON)) 0.1 typ VDD = 2.7 V, VS = 0 V to VDD, 0.15 0.16 max IS = 10 mA LEAKAGE CURRENTS VDD = 3.6 V ±1 ±10 ±100 nA max Test Circuit 2 Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 3.3 V; Test Circuit 3 ±1 ±15 ±120 nA max DIGITAL INPUTS Input High Voltage, VINH 2 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max CIN, Digital Input Capacitance 4 pF typ DYNAMIC CHARACTERISTICS2 tON 21 ns typ RL = 50 , CL = 35 pF 26 28 29 ns max VS = 1.5 V/0 V; Test Circuit 4 tOFF 4 ns typ RL = 50 , CL = 35 pF 7 8 9 ns max VS = 1.5 V; Test Circuit 4 Break-before-Make Time Delay (tBBM) 17 ns typ RL = 50 , CL = 35 pF 5 ns min VS1 = VS2 = 1.5 V; Test Circuit 5 Charge Injection 40 pC typ VS = 1.5 V, RS = 0 , CL = 1 nF; Test Circuit 6 Off Isolation –67 dB typ RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 7 Channel-to-Channel Crosstalk –90 dB typ S1A–S2A/S1B–S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 –67 dB typ S1A–S1B/S2A–S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 9 Total Harmonic Distortion (THD + N) 0.02 % RL = 32 , f = 20 Hz to 20 kHz, VS = 2 V p-p Insertion Loss –0.05 dB typ RL = 50 , CL = 5 pF; Test Circuit 8 –3 dB Bandwidth 57 MHz typ RL = 50 , CL = 5 pF; Test Circuit 8 CS (OFF) 25 pF typ CD, CS (ON) 75 pF typ POWER REQUIREMENTS VDD = 3.6 V IDD 0.003 µA typ Digital Inputs = 0 V or 3.6 V 1 4 µA max NOTES 1Temperature range is as follows: Y version: –40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.) REV. 0 REV. 0
–2– ADG836–SPECIFICATIONS1 ADG836 –3– SPECIFICATIONS1 –40C –40C Parameter +25C to +85C to +125C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 0.65 typ VDD = 2.3 V, VS = 0 V to VDD, 0.72 0.8 0.88 max IS = 10 mA; Test Circuit 1 On Resistance Match between 0.04 typ VDD = 2.3 V, VS = 0.7 V; Channels ( RON) 0.08 0.085 max IS = 10 mA On Resistance Flatness (RFLAT (ON)) 0.16 typ VDD = 2.3 V, VS = 0 V to VDD, 0.23 0.24 max IS = 10 mA LEAKAGE CURRENTS VDD = 2.7 V ±0.4 ±4 ±45 nA max Test Circuit 2 Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 2.4 V; Test Circuit 3 ±0.6 ±12 ±90 nA max DIGITAL INPUTS Input High Voltage, VINH 1.7 V min Input Low Voltage, VINL 0.7 V max Input Current IINL or IINH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max CIN, Digital Input Capacitance 4 pF typ DYNAMIC CHARACTERISTICS2 tON 23 ns typ RL = 50 , CL = 35 pF 29 30 31 ns max VS = 1.5 V/0 V; Test Circuit 4 tOFF 5 ns typ RL = 50 , CL = 35 pF 7 8 9 ns max VS = 1.5 V; Test Circuit 4 Break-before-Make Time Delay (tBBM) 17 ns typ RL = 50 , CL = 35 pF 5 ns min VS1 = VS2 = 1.5 V; Test Circuit 5 Charge Injection 30 pC typ VS = 1.25 V, RS = 0 , CL = 1 nF; Test Circuit 6 Off Isolation –67 dB typ RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 7 Channel-to-Channel Crosstalk –90 dB typ S1A–S2A/S1B–S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 –67 dB typ S1A–S1B/S2A–S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 9 Total Harmonic Distortion (THD + N) 0.022 % RL = 32 , f = 20 Hz to 20 kHz, VS = 1.5 V p-p Insertion Loss –0.06 dB typ RL = 50 , CL = 5 pF; Test Circuit 8 –3 dB Bandwidth 57 MHz typ RL = 50 , CL = 5 pF; Test Circuit 8 CS (OFF) 25 pF typ CD, CS (ON) 75 pF typ POWER REQUIREMENTS VDD = 2.7 V IDD 0.003 µA typ Digital Inputs = 0 V or 2.7 V 1.0 4.0 µA max NOTES 1 Temperature range is as follows: Y version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted.) REV. 0 REV. 0
–4– ADG836 ADG836 –5– SPECIFICATIONS1 –40C –40C Parameter +25C to +85C to +125C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 1 typ VDD = 1.8 V, VS = 0 V to VDD, IS = 10 mA; 1.4 2.2 2.2 max Test Circuit 1 2 4 4 max VDD = 1.65 V, VS = 0 V to VDD, IS = 10 mA On Resistance Match between 0.1 typ VDD = 1.65 V, VS = 0.7 V, IS = 10 mA Channels ( RON) LEAKAGE CURRENTS VDD = 1.95 V ±0.4 ±4 ±25 nA max Test Circuit 2 Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 1.65 V; Test Circuit 3 ±0.6 ±10 ±75 nA max DIGITAL INPUTS Input High Voltage, VINH 0.65 VDD V min Input Low Voltage, VINL 0.35 VDD V max Input Current IINL or IINH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max CIN, Digital Input Capacitance 4 pF typ DYNAMIC CHARACTERISTICS2 tON 28 ns typ RL = 50 , CL = 35 pF 37 38 39 ns max VS = 1.5 V/0 V; Test Circuit 4 tOFF 7 ns typ RL = 50 , CL = 35 pF 9 10 11 ns max VS = 1.5 V/0 V; Test Circuit 4 Break-before-Make Time Delay (tBBM) 21 ns typ RL = 50 , CL = 35 pF 5 ns min VS1 = VS2 = 1 V; Test Circuit 5 Charge Injection 20 pC typ VS = 1 V, RS = 0 , CL = 1 nF; Test Circuit 6 Off Isolation –67 dB typ RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 7 Channel-to-Channel Crosstalk –90 dB typ S1A–S2A/S1B–S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 10 –67 dB typ S1A–S1B/S2A–S2B; RL = 50 , CL = 5 pF, f = 100 kHz; Test Circuit 9 Total Harmonic Distortion, THD 0.14 % RL = 32 , f = 20 Hz to 20 kHz, VS = 1.2 V p-p Insertion Loss –0.08 dB typ RL = 50 , CL = 5 pF; Test Circuit 8 –3 dB Bandwidth 57 MHz typ RL = 50 , CL = 5 pF; Test Circuit 8 CS (OFF) 25 pF typ CD, CS (ON) 75 pF typ POWER REQUIREMENTS VDD = 1.95 V IDD 0.003 µA typ Digital Inputs = 0 V or 1.95 V 1.0 4 µA max NOTES 1Temperature range is as follows: Y version: –40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted.) REV. 0 REV. 0
–4– ADG836 ADG836 –5– ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C, unless otherwise noted.) or 10 mA, Whichever Occurs First Peak Current, S or D (Pulsed at 1ms, 10% Duty Cycle Max) Continuous Current, S or D
3.3 V Operation 300 mA
2.5 V Operation 275 mA
1.8 V Operation 250 mA
Operating Temperature Range NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table I. ADG836 Truth Table Logic Switch A Switch B
0 Off On
1 On Off
Model Temperature Range Package Description Package Option Branding* ADG836YRM –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S9A ADG836YRM-REEL –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S9A ADG836YRM-REEL7 –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S9A ADG836YCP –40°C to +125°C Lead Frame Chip Scale Package (LFCSP) CP-12 S9A ADG836YCP-REEL –40°C to +125°C Lead Frame Chip Scale Package (LFCSP) CP-12 S9A ADG836YCP-REEL7 –40°C to +125°C Lead Frame Chip Scale Package (LFCSP) CP-12 S9A *Branding on this package is limited to three characters due to space constraints. REV. 0 REV. 0
–6– –7– Typical Performance Characteristics–ADG836 TERMINOLOGY VDD Most positive power supply potential. IDD Positive supply current. GND Ground (0 V) reference. S Source terminal. May be an input or output. D Drain terminal. May be an input or output. IN Logic control input. VD (VS) Analog voltage on terminals D, S. RON Ohmic resistance between D and S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. RON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID (OFF) Drain leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD (OFF) Off switch drain capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. –3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonics amplitude plus noise of a signal, to the fundamental. 10-Lead MSOP (RM-10) 12-Lead LFCSP (CP-12) PIN CONFIGURATIONS REV. 0 REV. 0
–6– –7– Typical Performance Characteristics–ADG836 0.60 0.55 0.50 0.45ON RESISTANCE () 0.40 0.35 0.30 0.25 0.20 VD, VS (V) VDD = 2.7VVDD = 3V TA = 25C VDD = 3.6V VDD = 3.3V TPC 1. On Resistance vs. VD (VS) VDD = 2.7 V to 3.6 V 0.8 ON RESISTANCE () 0.3 0.4 0.5 0.6 0.7 0.2 VD, VS (V) TA = 25C VDD = 2.5V VDD = 2.3V VDD = 2.7V TPC 2. On Resistance vs. VD (VS) VDD = 2.5 V ± 0.2 V 1.8 ON RESISTANCE () 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 VD, VS (V) TA = 25C VDD = 1.65V VDD = 1.8V VDD = 1.95V TPC 3. On Resistance vs. VD (VS), VDD = 1.8 V ± 0.15 V 1.2 ON RESISTANCE () 0.2 0.4 0.6 0.8 1.0 VD, VS (V) +125C +85C +25C –40C VDD = 3.3V TPC 4. On Resistance vs. V D (VS) for Different Temperatures, 3.3 V 1.2 ON RESISTANCE () 0.2 0.4 0.6 0.8 1.0 VD, VS (V) +125C +25C VDD = 2.5V +85C –40C TPC 5. On Resistance vs. V D (VS) for Different Temperature, 2.5 V 1.4 ON RESISTANCE () 0.2 0.5 0.7 0.8 1.0 1.2 VD, VS (V) +25C –40C +85C +125C VDD = 1.8V TPC 6. On Resistance vs. VD (VS) for Different Temperatures, 1.8 V REV. 0 REV. 0
–8– ADG836 –9– –20 –80 –60 –40 0 20 6040 80 100 120 ID,IS (ON) IS (OFF) VDD =3.3V TPC 7 . Leakage Currents vs. Temperature, 3.3 V CURRENT (nA) –30 –20 –10 –40 0 12010080604020 TEMPERATURE (C) VDD = 2.5V ID, IS (ON) IS (OFF) TPC 8. Leakage Current vs. Temperature, 2.5 V CURRENT (nA) –20 –10 0 12010080604020 TEMPERATURE (C) VDD = 1.8V IS, ID (ON) IS (OFF) TPC 9. Leakage Current vs. Temperature, 1.8 V TA =25ºC VCC =3.3V VCC =2.5V VCC =1.8V TPC 10. Charge Injection vs. Source Voltage TPC 1 1. tON/tOFF Times vs. Temperature ATTENUATION(dB) VCC =3.3V/2.5V/1.8V TA =25ºC TPC 12. Bandwidth REV. 0 REV. 0
–8– ADG836 –9– –80 –70 –60 –50 –40 –30 –20 –10 ATTENUATION(dB) VCC =3.3V/2.5V/1.8V TA =25ºC TPC 13. Off Isolation vs. Frequency –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 ATTENUATION(dB) VCC =3.3V/2.5V/1.8V TA =25ºC TPC 14. Crosstalk vs. Frequency 0.10THD + N (%) 0.02 0.04 0.06 0.08 20 20k10050 200 1k500 2k 10k5k FREQUENCY (Hz) VDD = 2.5V TA = 25C S1A–D1 32 LOAD 1.5V p-p TPC 15. Total Harmonic Distortion + Noise REV. 0 REV. 0
–10– ADG836 ADG836 –11– Test Circuit 4. Switching Times, tON, tOFF Test Circuit 5. Break-before-Make Time Delay, tBBM Test Circuit 6. Charge Injection Test Circuits Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage REV. 0 REV. 0
–10– ADG836 ADG836 –11– Test Circuit 7 . Off Isolation Test Circuit 8. Bandwidth Test Circuit 9. Channel-to-Channel Crosstalk (S1A–S1B) Test Circuit 10. Channel-to-Channel Crosstalk (S1A–S2A) REV. 0 REV. 0
C04308–0–8/03(0) –12– ADG836 OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 0.15 0.00 0.27 0.17 0.95 0.85 0.75 SEATING PLANE
1.10 MAX
0.50 BSC
3.00 BSC
4.90 BSC
0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 12-Lead Lead Frame Chip Scale Package [LFCSP] (CP-12) Dimensions shown in millimeters 0.50 BSC
0.60 MAX PIN 1 INDICATOR
0.75 0.55 0.35
0.25 MIN
0.45 TOP VIEW 12 MAX 0.80 MAX
0.65 TYP
1.00 0.85 0.80 0.30 0.23 0.18
0.05 MAX
0.02 NOM
0.20 REF
1.45 1.30 1.15 BOTTOM VIEW 2.75 BSC SQ 3.00 BSC SQ SQ* COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION REV. 0