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0.5 Ω, CMOS, 1.8 V to 5.5 V, 2:1 Mux/SPDT Switch Data Sheet ADG819 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved.

FEATURES

Low on resistance: 0.8 Ω maximum at 125°C 0.25 Ω maximum on resistance flatness 1.8 V to 5.5 V single supply 200 mA current carrying capability Automotive temperature range: –40°C to +125°C Rail-to-rail operation 6-lead SOT-23, 8-lead MSOP, and 6-ball WLCSP packages Fast switching times Typical power consumption (<0.01 µW) TTL-/CMOS-compatible inputs Pin compatible with the ADG719

APPLICATIONS

Figure 1. GENERAL DESCRIPTION The ADG819 is a monolithic, CMOS, single-pole, double-throw (SPDT) switch. This switch is designed on a submicron process that provides low power dissipation yet gives high switching speed, low on resistance, and low leakage currents. Low power consumption and an operating supply range of 1.8 V to 5.5 V make the ADG819 ideal for battery-powered, portable instruments. Each switch of the ADG819 conducts equally well in both directions when on. The ADG819 exhibits break-before-make switching action, thus preventing momentary shorting when switching channels. The ADG819 is available in a 6-lead SOT-23 package, an 8-lead MSOP package, and in a 6-ball WLCSP package. This chip occupies only a 1.14 mm × 2.18 mm area, making it the ideal candidate for space-constrained applications. PRODUCT HIGHLIGHTS 1. Ver y low on resistance, 0.5 Ω typical. 2. 1.8 V to 5.5 V single-supply operation. 3. High current carrying capability. 4. Tiny 6-lead SOT-23, 8-lead MSOP, and 6-ball, 1.14 mm × 2.18 mm WLCSP packages. D IN ADG819 SWITCHES SHOWN FOR A LOGIC 1 INPUT 02801-001

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

5/12—Rev. 0 to Rev. A Change to WLCSP θJA Thermal Impedance Parameter, 5/02—Revision 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter 25°C −40°C to +85°C –40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 1 0.5 Ω typ VS = 0 V to VDD, IS = 100 mA; see Figure 16 0.6 0.7 0.8 Ω max On Resistance Match Between Channels, ΔRON 0.06 Ω typ VS = 0 V to VDD, IS = 100 mA 0.08 0.1 0.12 Ω max On Resistance Flatness, RFLAT(ON) 1 0.1 Ω typ VS = 0 V to VDD, IS = 100 mA 0.17 0.2 0.25 Ω max LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage, IS (Off) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V; see Figure 17 ±0.25 ±3 ±10 nA max Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = 1 V, or VS = VD = 4.5 V; see Figure 18 ±0.25 ±3 ±25 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS2 tON 35 ns typ RL = 50 Ω, CL = 35 pF, VS = 3 V; see Figure 19 45 50 55 ns max tOFF 10 ns typ RL = 50 Ω, CL = 35 pF, VS = 3 V; see Figure 19 16 18 21 ns max Break-Before-Make Time Delay, tBBM 5 ns typ RL = 50 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 20 1 ns min Charge Injection 20 pC typ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 21 Off Isolation –71 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22 Channel-to-Channel Crosstalk –72 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 Bandwidth, –3 dB 17 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 23 CS (Off) 80 pF typ f = 1 MHz CD, CS (On) 300 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 5.5 V, digital inputs = 0 V or 5.5 V IDD 0.001 μA typ 1.0 2.0 μA max 1 On resistance parameters tested with IS = 10 mA. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 4 of 16 VDD = 2.7 V to 3.6 V , GND = 0 V, unless otherwise noted. Table 2. Parameter 25°C –40°C to +85°C –40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 1 0.7 Ω typ VS = 0 V to VDD, IS = 100 mA; see Figure 16 1.4 1.5 1.6 Ω max On Resistance Match Between Channels, ΔRON 0.06 Ω typ VS = 0 V to VDD, IS = 100 mA 0.13 0.13 Ω max On Resistance Flatness, RFLAT(ON) 1 0.25 Ω typ VS = 0 V to VDD, IS = 100 mA LEAKAGE CURRENTS VDD = 3.6 V Source Off Leakage, IS (Off) ±0.01 nA typ VS = 3.3 V/1 V, VD = 1 V/3.3 V; see Figure 17 ±0.25 ±3 ±10 nA max Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = 1 V, or VS = VD = 3.3 V; see Figure 18 ±0.25 ±3 ±25 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS2 tON 40 ns typ RL = 50 Ω, CL = 35 pF, VS = 1.5 V; see Figure 19 60 65 70 ns max tOFF 10 ns typ RL = 50 Ω, CL = 35 pF, VS = 1.5 V; see Figure 19 16 18 21 ns max Break-Before-Make Time Delay, tBBM 40 ns typ RL = 50 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 20 1 ns min Charge Injection 10 pC typ VS = 1.5 V, RS = 0 Ω,CL = 1 nF; see Figure 21 Off Isolation −71 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22 Channel-to-Channel Crosstalk −72 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 Bandwidth, –3 dB 17 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 23 CS (Off) 80 pF typ f = 1 MHz CD, CS (On) 300 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 3.6 V, digital Inputs = 0 V or 3.6 V IDD 0.001 μA typ 1.0 2.0 μA max 1 On resistance parameters tested with IS = 10 mA. 2 Guaranteed by design; not subject to production test.

be limited to the maximum ratings given. Table 4. Truth Table for the ADG819

0 On Off

1 Off On

Rev. A | Page 11 of 16 TERMINOLOGY RON Ohmic resistance between D and Sx. ΔRON On resistance match between any two channels, that is, RON maximum − RON minimum. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) Source leakage current with the switch off. ID, IS (On) Channel leakage current with the switch on. VD (VS) Analog voltage on Terminal D and Terminal S. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (Off) Off switch source capacitance. CD, CS (On) On switch capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. t BBM Off time or on time measured between the 90% points of both switches when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Channel-to-Channel Crosstalk A measure of unwanted signal coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an off switch. Bandwidth Frequency at which the output is attenuated by −3 dB. On Response Frequency response of the on switch.

Figure 25. 6-Lead Small Outline Transistor Package [SOT-23] Figure 26. 8-Lead mini Small Outline Package [MSOP]

0.95 BSC

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.20 MAX

0.08 MIN

0.50 MAX

0.30 MIN

0.65 BSC

1.10 MAX

Figure 27. 6-Ball Wafer Level Chip Scale Package [WLCSP] 2 Branding on these packages is limited to three characters due to space constraints. 3 Contact factory for availability.

0.32 NOM

0.24 MAX

Rev. A | Page 14 of 16 NOTES

Rev. A | Page 15 of 16 NOTES

Rev. A | Page 16 of 16 NOTES ©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02801-0-5/12(A)