ADG801

ADG801 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

REV. PrE Jan ‘02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADG801/ADG802 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA <0.5 Ω ΩΩ ΩΩ CMOS, Low Voltage, SPST Switches

FEATURES

Low On Resistance < 0.5 Ω ΩΩ ΩΩ max at 5 V supply 0.1 Ω ΩΩ ΩΩ On Resistance Flatness +1.8 V to +5.5 V Single Supply 100pA Leakage Currents 14ns Switching Times Extended Temperature Range -40 oC to +125oC High Current Carrying Capability Tiny 6 lead SOT23 and 8 Lead µ µµ µµSOIC Packages Low Power Consumption TTL/CMOS Compatible Inputs Pin Compatible with ADG701/ADG702

APPLICATIONS

Audio and Video Signal Routing Cellular Phones Modems PCMCIA Cards Hard Drives Data Acquisition Systems Communication Systems Relay replacement Audio and Video Switching Battery Powered Systems GENERAL DESCRIPTION The ADG801/ADG802 are monolithic CMOS SPST (Single Pole, Single Throw) switches with On Resistance of less than 0.5Ω . These switches are designed on an advanced submicron process that provides extremely low on resistance, high switch- ing speed and low leakage currents. The low On Resistance of <0.5 Ω means these parts are ideal for applications where low on resistance switching is critical. The ADG801 is a normally open (NO) switch, while the ADG802 is normally closed (NC). Each switch conducts equally well in both directions when ON. The ADG801 and ADG802 are available in 6-lead SOT-23 and 8 Lead µSOIC packages. PRODUCT HIGHLIGHTS 1. Low On Resistance (0.25 Ω typical). 2. +1.8V to +5.5V Single Supply Operation. 3. Tiny 6 Lead SOT23 and 8 Lead µSOIC Packages. 4. Pin Compatible with ADG701 (ADG801) Pin Compatible with ADG702 (ADG802). FUNCTIONAL BLOCK DIAGRAMS D IN S ADG801 D IN S ADG802 SWITCHES SHOWN FOR A LOGIC "1" INPUT

–2– REV. PrE ADG801/ADG802–SPECIFICATIONS1 PRELIMINARY TECHNICAL DATA (VDD = 5 V ±10%, V SS = GND = 0 V. All specifications –40°C to +125°C unless otherwise noted.) –40oC to –40oC to Parameter +25 oC +85 oC +125 oC Units Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (R ON) 0.25 Ω typ V S = 0 V to V DD, I S = –10 mA; 0.4 0.5 0.75 Ω max Test Circuit 1 On-Resistance Flatness (R FLAT(ON) ) 0.05 Ω typ V S = 0 V to V DD, I S = –10 mA 0.1 0.2 Ω max LEAKAGE CURRENTS V DD = +5.5 V Source OFF Leakage I S (OFF) ±0.01 nA typ V S = 4.5 V/1 V, V D = 1 V/4.5 V; ±0.5 ±1 tbd nA max T est Circuit 2 Drain OFF Leakage I D (OFF) ±0.01 nA typ V S = 4.5 V/1 V, V D = 1 V/4.5 V; ±0.5 ±1 tbd nA max T est Circuit 2 Channel ON Leakage I D, I S (ON) ±0.01 nA typ V S = V D = 1 V, or 4.5 V; ±0.5 ±1 tbd nA max T est Circuit 3 DIGITAL INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max Input Current IINL or I INH 0.005 µA typ V IN = V INL or V INH ±0.1 µA max CIN, Digital Input Capacitance 5 pF typ DYNAMIC CHARACTERISTICS 2 tON 30 ns typ R L = 50 Ω , C L = 35 pF TBD TBD ns max V S = 3 V; Test Circuit 4 tOFF 20 ns typ R L = 50 Ω , C L = 35 pF TBD TBD ns max V S = 3 V; Test Circuit 4 Charge Injection ±20 pC typ V S = 0 V, R S = 0 Ω , C L = 1 nF, Test Circuit 5 Off Isolation –65 dB typ R L = 50 Ω , C L = 5 pF, f = 1 MHz, Test Circuit 6 Bandwidth –3 dB 30 MHz typ R L = 50 Ω , C L = 5 pF, Test Circuit 7 CS (OFF) 55 pF typ f = 1 MHz CD (OFF) 55 pF typ f = 1 MHz CD, C S (ON) 110 pF typ f = 1 MHz POWER REQUIREMENTS V DD = +5.5 V I DD 0.001 µA typ D igital Inputs = 0 V or 5.5 V 1.0 µA max NOTES 1Temperature ranges are as follows: Extended Temperature Range: – 40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice.

–3–REV. PrE ADG801/ADG802 PRELIMINARY TECHNICAL DATA (VDD = 2.7 V to 3.6 V, V SS = GND = 0 V. All specifications –40°C to +125°C unless otherwise noted.) –40oC to –40oC to Parameter +25 oC +85 oC +125 oC Units Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (R ON) 0.3 1 Ω typ V S = 0 V to V DD, I S = –10 mA; 0.7 0.8 Ω max Test Circuit 1 On-Resistance Flatness(R FLAT(ON) ) 0.1 0.3 Ω typ V S = 0 V to V DD, I S = –10 mA LEAKAGE CURRENTS V DD = +3.3 V Source OFF Leakage I S (OFF) ±0.01 nA typ V S = 3 V/1 V, V D = 1 V/3 V; ±0.5 ±0.1 tbd nA max Test C ircuit 2 Drain OFF Leakage I D (OFF) ±0.01 nA typ V S = 3 V/1 V, V D = 1 V/3 V; ±0.5 ±0.1 tbd nA max Test C ircuit 2 Channel ON Leakage I D, I S (ON) ±0.01 nA typ V S = V D = 1 V, or 3 V; ±0.5 ±0.1 tbd nA max Test C ircuit 3 DIGITAL INPUTS Input High Voltage, V INH 2.0 V min Input Low Voltage, V INL 0.4 V max Input Current IINL or I INH 0.005 µA typ V IN = V INL or V INH ±0.1 µA max CIN, Digital Input Capacitance 5 pF typ DYNAMIC CHARACTERISTICS 2 tON 50 ns typ R L = 50 Ω , C L = 35 pF TBD TBD ns max V S = 1.5 V, Test Circuit 4 tOFF 40 ns typ R L = 50 Ω , C L = 35 pF TBD TBD ns max V S = 1.5 V, Test Circuit 4 Charge Injection ±20 pC typ V S = 0 V, R S = 0 Ω , C L = 1 nF, Test Circuit 5 Off Isolation –65 dB typ R L = 50 Ω , C L = 5 pF, f = 1 MHz, Test Circuit 6 Bandwidth –3 dB 30 MHz typ R L = 50 Ω , C L = 5 pF, Test Circuit 7 CS (OFF) 55 pF typ f = 1 MHz CD (OFF) 55 pF typ f = 1 MHz CD, C S (ON) 110 pF typ f = 1 MHz POWER REQUIREMENTS V DD = +3.3 V I DD 0.001 µA typ D igital Inputs = 0 V or 3.3 V 1.0 µA max NOTES 1Temperature ranges are as follows: Extended Temperature Range: –40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. SPECIFICATIONS1

–4– REV. PrE PRELIMINARY TECHNICAL DATA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG801/ADG802 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1 (TA = +25 °C unless otherwise noted) (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range ORDERING GUIDE Model Temperature Range Supply Option 1 Brand1 Package Descriptions Package Options ADG801BRT –40°C to +125 °C 3 V, 5 V SLB SOT-23 (Plastic Surface Mount) RT-6 ADG801BRM –40°C to +125 °C 3 V, 5 V SLB µSOIC (Small Outline) RM-8 ADG802BRT –40°C to +125 °C 3 V, 5 V SMB SOT-23 (Plastic Surface Mount) RT-6 ADG802BRM –40°C to +125 °C 3 V, 5 V SMB µSOIC (Small Outline) RM-8 1Branding on SOT-23 and µSOIC packages is limited to 3 characters due to space constraints. NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. Table I. Truth Table ADG801 In ADG802 In Switch Condition 0 1 OFF

10 O N

6-Lead Plastic Surface Mount (SOT-23) (RT-6) TOP VIEW (Not to Scale) NC = NO CONNECT D S GND V DD NC IN ADG801/ ADG802 8-Lead Small Outline µµµµµSOIC (RM-8) TOP VIEW (Not to Scale) NC = NO CONNECT D NC NC S GND IN NCV DD ADG801/ ADG802

–5–REV. PrE PRELIMINARY TECHNICAL DATA TERMINOLOGY VDD Most positive power supply potential. IDD Positive supply current. GND Ground (0 V) reference. S Source terminal. May be an input or output. D Drain terminal. May be an input or output. IN Logic control input. VD (VS) Analog voltage on terminals D, S RON Ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. IS (OFF) Source leakage current with the switch “OFF.” ID (OFF) Drain leakage current with the switch “OFF.” ID, IS (ON) Channel leakage current with the switch “ON.” VINL Maximum input voltage for logic “0”. VINH Minimum input voltage for logic “1”. IINL(IINH) Input current of the digital input. CS (OFF) “OFF” switch source capacitance. Measured with reference to ground. CD (OFF) “OFF” switch drain capacitance. Measured with reference to ground. CD,CS(ON) “ON” switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay between applying the digital control input and the output switching on. See Test Circuit 4. tOFF Delay between applying the digital control input and the output switching off. Charge A measure of the glitch impulse transferred from the digital input to the analog output during switching. Injection Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3dBs. On Response The Frequency response of the “ON” switch. Insertion The loss due to the ON resistance of the switch. Loss

–8– REV. PrE PRELIMINARY TECHNICAL DATA Test Circuits IDS SD VS R ON = V1/IDS Test Circuit 1. On Resistance SD VS A A VD IS (OFF) I D (OFF) Test Circuit 2. Off Leakage SD A VD ID (ON) NC NC=No Connect Test Circuit 3. On Leakage VS IN SD GND R L 300/H9024 C L 35pF VOUT ADG801 ADG802 VIN VIN VOUT tON tOFF 50% 50% 90% 90% 50% 50% VDD 0.1µ F VDD Test Circuit 4. Switching Times VS IN SD VDD GND C L 1nF VOUTR S ADG801 ADG802 VIN VIN VOUT OFF /H9004VOUT ON Q INJ = CL /H11547 /H9004VOUT VDD Test Circuit 5. Charge Injection VS VOUT 50Ω NETWORK ANALYZER R L 50Ω IN GND VIN S D 50Ω OFF ISOLATION = 20 LOG VOUT VS VDD 0.1µ F VDD Test Circuit 6. Off Isolation VS VOUT 50Ω NETWORK ANALYZER R L 50Ω IN GND VIN S D INSERTION LOSS = 20 LOG VOUT WITH SWITCH VOUT WITHOUT SWITCH VDD 0.1µ F VDD Test Circuit 7. Bandwidth

–9–REV. PrE PRELIMINARY TECHNICAL DATA 8-Lead µµµµµSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.122 (3.10) 0.114 (2.90) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33° 27° 0.120 (3.05) 0.112 (2.84) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead SOT-23 (RT-6) 0.122 (3.10) 0.106 (2.70) PIN 1 0.118 (3.00) BSC 0.037 (0.95) BSC 1 3 4 5 6 0.071 (1.80) 0.059 (1.50) 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10/H11543 0/H115430.020 (0.50) 0.010 (0.25) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) SEATING PLANE 0.057 (1.45) 0.035 (0.90)