ADG708BRUZ

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CMOS, 1.8 V to 5.5 V/±2.5 V, 3 Ω Low Voltage 4-/8-Channel Multiplexers Data Sheet ADG708/ADG709 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700©2000–2013 Analog Devices, Inc. All rights reserved. Techni cal Su pport www.analog.com FEA TURES 1.8 V to 5.5 V single supply ±2.5 V dual supply 3 Ω on resistance 0.75 Ω on resistance flatness 100 pA leakage currents 14 ns switching times Single 8-to-1 multiplexer ADG708 Differential 4-to-1 multiplexer ADG709 16-lead TSSOP package Low power consumption TTL-/CMOS-compatible inputs Qualified for automotive applications

APPLICATIONS

The ADG708/ADG709 are low voltage, CMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG708 switches one of eight inputs (S1 to S8) to a common output, D, as determined by the 3-bit binary address lines A0, A1, and A2. The ADG709 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. Low power consumption and an operating supply range of 1.8 V to 5.5 V make the ADG708/ADG709 ideal for battery- powered, portable instruments. All channels exhibit break- before-make switching action preventing momentary shorting when switching channels. These switches are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance, and leakage currents. On resistance is in the region of a few ohms and is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either multiplexers or demultiplexers and have an input signal range that extends to the supplies. FUNCTIONAL BLOCK DIA GRAMS D A1 A2 ADG708 EN

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Figure 1. S1A DA S4A S1B S4B DB EN ADG709

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Figure 2. PRODUCT HIGHLIGHTS 1. Single-/dual-supply operation. The ADG708/ADG709 are fully specified and guaranteed with 3 V and 5 V single-supply and ±2.5 V dual-supply rails. 2. Low RON (3 Ω typical). 3. Low power consumption (<0.01 μW). 4. Guaranteed break-before-make switching action. 5. Small 16-lead TSSOP package. The ADG708/ADG709 are available in a 16-l e a d T S S O P.

Rev. D | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

1/13−R ev. C to R ev. D 4/09−R ev. B to R ev. C 8/06−Rev. A to Rev. B 4/02—R ev. 0 to R ev. A 10/00—Revision 0: Initial V ersion

Rev. D | Page 3 of 20 SPECIFICATIONS VDD = 5 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 1. B Version C Version Parameter +25°C −40°C to +85°C −40°C to +125°C +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/ Comments ANALOG SWITCH Analog Signal Range 0 V to VDD

0 V to

V DD V DD V On Resistance (RON) 3 3 Ω typ VS = 0 V to VDD, IDS = 10 mA; see Figure 20 4.5 5 7 4.5 5 7 Ω max On Resistance Match Between Channels (ΔRON) 0.4 0.4 Ω typ 0.8 1.5 0.8 1.5 Ω max V S = 0 V to VDD, IDS = 10 mA On Resistance Flatness (RFLAT (ON)) 0.75 0.75 Ω typ V S = 0 V to VDD, IDS = 10 mA 1.2 1.65 1.2 1.65 Ω max LEAKAGE CURRENTS V DD = 5.5 V Source Off Leakage, IS (Off) ±0.01 ±0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V; see Figure 21 Drain Off Leakage, ID (Off ) ±0.01 ±0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V; see Figure 22 ±20 ±20 ±0.1 ±0.75 ±6 nA max Channel On Leakage, ID, IS (On) ±0.01 ±0.01 nA typ VD = VS = 1 V or 4.5 V; see Figure 23 ±20 ±20 ±0.1 ±0.75 ±6 nA max DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Current IINL or IINH 0.005 0.005 μA typ V IN = VINL or VINH ±0.1 ±0.1 μA max Digital Input Capacitance, CIN 2 2 pF typ DYNAMIC CHARACTERISTICS1 tTRANSITION 14 14 ns typ RL = 300 Ω, CL = 35 pF; see Figure 24 25 25 25 25 ns max V S1 = 3 V/0 V, VS8 = 0 V/3 V Break-Before-Make Time Delay, tOPEN 8 8 ns typ R L = 300 Ω, CL = 35 pF 1 1 1 1 ns min V S = 3 V; see Figure 25 tON (EN) 14 14 ns typ R L = 300 Ω, CL = 35 pF 25 25 25 25 ns max V S = 3 V; see Figure 26 tOFF (EN) 7 7 ns typ R L = 300 Ω, CL = 35 pF 12 12 12 12 ns max V S = 3 V; see Figure 26 Charge Injection ±3 ±3 pC typ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; See Figure 27 Off Isolation −60 −60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz −80 −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28

Rev. D | Page 4 of 20 B Version C Version Parameter +25°C −40°C to +85°C −40°C to +125°C +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/ Comments Channel-to-Channel Crosstalk −60 −60 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz −80 −80 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz; see Figure 29 −3 dB Bandwidth 55 55 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30 CS (Off ) 13 13 pF typ f = 1 MHz CD (Off) ADG708 85 85 pF typ f = 1 MHz ADG709 42 42 pF typ f = 1 MHz CD, CS (On) ADG708 96 96 pF typ f = 1 MHz ADG709 48 48 pF typ f = 1 MHz POWER REQUIREMENTS V DD = 5.5 V IDD 0.001 0.001 μA typ Digital inputs = 0 V or 5.5 V 1.0 1.0 1.0 1.0 μA max 1 Guaranteed by design, not subject to production test.

Rev. D | Page 5 of 20 VDD = 3 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. B Version C Version Parameter +25°C −40°C to +85°C −40°C to +125°C +25°C −40°C to +85°C −40°C to +125°C Unit T est Conditions/ Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 8 8 Ω typ VS = 0 V to VDD, IDS = 10 mA; see Figure 20 11 12 14 11 12 14 Ω max On Resistance Match Between Channels (ΔRON) 0.4 0.4 Ω typ VS = 0 V to VDD, IDS = 10 mA 1.2 2 1.2 2 Ω max LEAKAGE CURRENTS VDD = 3.3 V Source Off Leakage, IS (Off ) ±0.01 ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V; see Figure 21 Drain Off Leakage, ID (Off ) ±0.01 ±0.01 nA typ VS = 3 V/1 V , VD = 1 V/3 V; see Figure 22 ±20 ±20 ±0.1 ±0.75 ±6 nA max Channel On Leakage, ID, IS (On) ±0.01 ±0.01 nA typ VS = VD = 1 V or 3 V; see Figure 23 ±20 ±20 ±0.1 ±0.75 ±6 nA max DIGIT AL INPUTS Input High Voltage, VINH 2.0 2.0 V min Input Low Voltage, VINL 0.8 0.8 V max Input Current IINL or IINH 0.005 0.005 μA typ VIN = VINL or VINH ±0.1 ±0.1 μA max Digital Input Capacitance, CIN 2 2 pF typ DYNAMIC CHARACTERISTICS1 tTRA NSITION 18 18 ns typ RL = 300 Ω, CL = 35 pF; see Figure 24 30 30 30 30 ns max VS1 = 2 V/0 V , VS2 = 0 V/2 V Break-Before-Make Time De l ay, tOPEN 8 8 ns typ RL = 300 Ω, CL = 35 pF 1 1 1 1 ns min VS = 2 V; see Figure 25 tON (EN) 18 18 ns typ RL = 300 Ω, CL = 35 pF 30 30 30 30 ns max VS = 2 V; see Figure 26 tOFF (EN) 8 8 ns typ RL = 300 Ω, CL = 35 pF 15 15 15 15 ns max VS = 2 V; see Figure 26 Charge Injection ±3 ±3 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation −60 −60 dB typ RL = 50 Ω, CL = 5 p F, f = 10 MHz −80 −80 dB typ RL = 50 Ω, CL = 5 p F, f = 1 MHz; see Figure 28 Channel-to-Channel Crosstalk −60 −60 dB typ RL = 50 Ω, CL = 5 p F, f = 10 MHz −80 −80 dB typ RL = 50 Ω, CL = 5 p F, f = 1 MHz; see Figure 29 −3 dB Bandwidth 55 55 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30

Rev. D | Page 6 of 20 B Version C Version Parameter +25°C −40°C to +85°C −40°C to +125°C +25°C −40°C to +85°C −40°C to +125°C Unit T est Conditions/ Comments CS (Off ) 13 13 pF typ f = 1 MHz CD (Off ) ADG708 85 85 pF typ f = 1 MHz ADG709 42 42 pF typ f = 1 MHz CD, CS (On) ADG708 96 96 pF typ f = 1 MHz ADG709 48 48 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 3.3 V IDD 0.001 0.001 μA typ Digital inputs = 0 V or 3.3 V 1.0 1.0 1.0 1.0 μA max 1 Guaranteed by design, not subject to production test.

Rev. D | Page 7 of 20 DUAL SUPPLY VDD = 2.5 V ± 10%, VSS = –2.5 V ± 10%, GND = 0 V , unless otherwise noted. Table 3. B Version C Version Parameter +25°C −40°C to +85°C −40°C to +125°C +25°C −40°C to +85°C −40°C to +125°C Unit T est Conditions/ Comments ANALOG SWITCH Analog Signal Range VSS to VDD VSS to VDD V On Resistance (RON) 2.5 2.5 Ω typ VS = VSS to VDD, IDS = 10 mA; see Figure 20 4.5 5 7 4.5 5 7 Ω max On Resistance Match Between Channels (ΔRON) 0.4 0.4 Ω typ 0.8 1.5 0.8 1.5 Ω max VS = VSS to VDD, IDS = 10 mA On Resistance Flatness (RFLAT (ON)) 0.6 0.6 Ω typ VS = VSS to VDD, IDS = 10 mA 1.0 1.65 1.0 1.65 Ω max LEAKAGE CURRENTS VDD = +2.75 V , VSS = −2.75 V Source Off Leakage, IS (Off ) ±0.01 ±0.01 nA typ VS = +2.25 V/−1.25 V , see Figure 21 Drain Off Leakage, ID (Off ) ±0.01 ±0.01 nA typ VS = +2.25 V/−1.25 V , see Figure 22 ±20 ±20 ±0.1 ±0.75 ±6 nA max Channel On Leakage, ID, IS (On) ±0.01 ±0.01 nA typ VS = VD = +2.25 V/−1.25 V; see Figure 23 ±20 ±20 ±0.1 ±0.75 ±6 nA max DIGIT AL INPUTS Input High Voltage, VINH 1.7 1.7 V min Input Low Voltage, VINL 0.7 0.7 V max Input Current IINL or IINH 0.005 0.005 μA typ VIN = VINL or VINH ±0.1 ±0.1 μA max Digital Input Capacitance, CIN 2 2 pF typ DYNAMIC CHARACTERISTICS1 tTRA NSITION 14 14 ns typ RL = 300 Ω, CL = 35 pF; see Figure 24 25 25 25 25 ns max VS = 1.5 V/0 V; see Figure 24 Break-Before-Make Time Delay, tOPEN 8 8 ns typ RL = 300 Ω, CL = 35 pF 1 1 1 1 ns min VS = 1.5 V; see Figure 25 tON (EN) 14 14 ns typ RL = 300 Ω, CL = 35 pF 25 25 25 25 ns max VS = 1.5 V; see Figure 26 tOFF (EN) 8 8 ns typ RL = 300 Ω, CL = 35 pF 15 15 15 15 ns max VS = 1.5 V; see Figure 26 Charge Injection ±3 ±3 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation −60 −60 dB typ RL = 50 Ω, CL = 5 p F, f = 10 MHz −80 −80 dB typ RL = 50 Ω, CL = 5 p F, f = 1 MHz; see Figure 28

Rev. D | Page 8 of 20 B Version C Version Parameter +25°C −40°C to +85°C −40°C to +125°C +25°C −40°C to +85°C −40°C to +125°C Unit T est Conditions/ Comments Channel-to-Channel Crosstalk −60 −60 dB typ RL = 50 Ω, CL = 5 p F, f = 10 MHz −80 −80 dB typ RL = 50 Ω, CL = 5 p F, f = 1 MHz; see Figure 29 −3 dB Bandwidth 55 55 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30 CS (Off ) 13 13 pF typ f = 1 MHz CD (Off ) ADG708 85 85 pF typ f = 1 MHz ADG709 42 42 pF typ f = 1 MHz CD, CS (On) ADG708 96 96 pF typ f = 1 MHz ADG709 48 48 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 2.75 V IDD 0.001 0.001 μA typ Digital inputs = 0 V or 2.75 V 1.0 1.0 1.0 1.0 μA max ISS 0.001 0.001 μA typ VSS = −2.75 V 1 Guaranteed by design not subject to production test.

Rev. D | Page 9 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to VSS 7 V VDD to GND −0.3 V to +7 V VSS to GND +0.3 V to −3.5 V Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Digital Inputs1 −0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) 100 mA Continuous Current, S or D 30 mA Operating T emperature Industrial T emperature Range −40°C to +125°C Storage T emperature Range −65°C to +150°C Junction T emperature 150°C θJA Thermal Impedance 150.4°C/W θJC Thermal Impedance 27.6°C/W Lead T emperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 Overvoltages at A, EN, S, or D are clamped by internal codes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION

Table 7. ADG708 Truth Table Table 8. ADG709 Truth Table

Figure 30. Bandwidth

Rev. D | Page 18 of 20 TERMINOLOGY VDD Most positive power supply potential. VSS Most negative power supply in a dual-supply application. In single-supply applications, tie VSS to ground at the device. GND Ground (0 V) reference. S Source terminal. Can be an input or output. D Drain terminal. Can be an input or output. Ax Logic control input. EN Active high enable. RON Ohmic resistance between D and S. RF L AT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) Source leakage current with the switch off. ID (Off) Drain leakage current with the switch off. ID, IS (On) Channel leakage current with the switch on. VD (VS) Analog voltage on T erminal D and T erminal S. CS (Off) Off switch source capacitance. Measured with reference to ground. CD (Off) Off switch drain capacitance. Measured with reference to ground. CD, CS (On) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tTRANSITION Delay time measured between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t ON (EN) Delay time between the 50% and 90% points of the EN digital input and the switch on condition. t OFF (EN) Delay time between the 50% and 90% points of the EN digital input and the switch off condition. tOPEN Off time measured between the 80% points of both switches when switching from one address state to another. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Charge A measure of the glitch impulse transferred from injection of the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. On Loss The loss due to the on resistance of the switch. V INL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current.

Rev. D | Page 19 of 20 APPLICATIONS INFORMATION POWER SUPPLY SEQUENCING When using CMOS devices, take care to ensure correct power supply sequencing. Incorrect power supply sequencing can result in the device being subjected to stresses beyond the maximum ratings listed in Figure 4. Always apply digital and analog inputs after power supplies and ground. For single-supply operation, tie VSS to GND as close to the device as possible.

Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP] 2 W = Qualified for Automotive Applications. obtain the specific Automotive Reliability reports for these models. registered trademarks are the property of their respective owners.