ADG706BRU

ADG706 AD | Alldatasheet

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Technical content

a REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 CMOS, 2.5 /H9024 Low-Voltage, 8-/16-Channel Multiplexers

FEATURES

1.8 V to 5.5 V Single Supply /H115503 V Dual Supply 2.5 /H9024 On Resistance 0.5 /H9024 On-Resistance Flatness 100 pA Leakage Currents 40 ns Switching Times Single 16-to-1 Multiplexer ADG706 Differential 8-to-1 Multiplexer ADG707 28-Lead TSSOP Package Low-Power Consumption TTL/CMOS-Compatible Inputs

APPLICATIONS

The ADG706 and ADG707 are low-voltage, CMOS analog multiplexers comprising 16 single channels and eight differential channels respectively. The ADG706 switches one of 16 in puts (S1–S16) to a common output, D, as determined by the 4-bit binary address lines A0, A1, A2, and A3. The ADG707 switches one of eight differential inputs to a common differential output as determined by the 3-bit binary address lines A0, A1, and A2. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched OFF. Low-power consumption and operating supply range of 1.8 V to

5.5 V make the ADG706 and ADG707 ideal for battery-powered,

portable instruments. All channels exhibit break-before-make switching action preventing momentary shorting w hen switch- ing channels. These devices are also designed to operate from a dual supply of ±3 V. These multiplexers are designed on an enhanced submicron process that provides low-power dissipation yet gives high- switching speed, very low on resistance and leakage currents. On resistance is in the region of a few ohms and is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either multiplexers or demultiplexers and have an input signal range which extends to the supplies. The ADG706 and ADG707 are available in small 28-lead TSSOP packages. FUNCTIONAL BLOCK DIAGRAMS S16 D A3A1 ADG706 S1A DA S8A S1B S8B DB EN ADG707 EN A2A2 1-OF-16 DECODER 1-OF-8 DECODER PRODUCT HIGHLIGHTS 1. Single/Dual Supply Operation. The ADG706 and ADG707 are fully specified and guaranteed with 3 V and 5 V single supply and ±3 V dual supply rails. 2. Low On Resistance (2.5 Ω typical). 3. Low-Power Consumption (<0.01 µW). 4. Guaranteed Break-Before-Make Switching Action. 5. Small 28-Lead TSSOP Package.

–2– REV. 0 ADG706/ADG707–SPECIFICATIONS1 (VDD = 5 V /H11550 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.) B Version –40/H11543C Parameter 25 /H11543C to +85 /H11543C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (RON) 2.5 Ω typ V S = 0 V to VDD, IDS = 10 mA; 4.5 5 Ω max Test Circuit 1 On Resistance Match Between 0.3 Ω typ V S = 0 V to VDD, IDS = 10 mA Channels (∆RON) 0.8 Ω max On-Resistance Flatness (R FLAT(ON)) 0.5 Ω typ V S = 0 V to VDD, IDS = 10 mA 1.2 Ω max LEAKAGE CURRENTS V DD = 5.5 V Source OFF Leakage I S (OFF) ±0.01 nA typ V D = 4.5 V/1 V, VS = 1 V/4.5 V; ±0.1 ±0.3 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ±0.01 nA typ V D = 4.5 V/1 V, VS = 1 V/4.5 V; ADG706 ±0.4 ±1.5 nA max Test Circuit 3 ADG707 ±0.1 ±1 nA max Channel ON Leakage ID, IS (ON) ±0.01 nA typ V D = VS = 1 V, or 4.5 V; ADG706 ±0.4 ±1.5 nA max Test Circuit 4 ADG707 ±0.1 ±1 nA max DIGITAL INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max Input Current IINL or IINH 0.005 µA typ V IN = VINL or VINH ±0.1 µA max CIN, Digital Input Capacitance 5 pF typ DYNAMIC CHARACTERISTICS 2 tTRANSITION 40 ns typ R L = 300 Ω, CL = 35 pF, Test Circuit 5; 60 ns max V S1 = 3 V/0 V, VS16 = 0 V/3 V Break-Before-Make Time Delay, t D 30 ns typ R L = 300 Ω, CL = 35 pF; 1 ns min V S = 3 V, Test Circuit 6 tON (EN) 32 ns typ R L = 300 Ω, CL = 35 pF; 50 ns max V S = 3 V, Test Circuit 7 tOFF (EN) 10 ns typ R L = 300 Ω, CL = 35 pF; 14 ns max V S = 3 V, Test Circuit 7 Charge Injection ±5 pC typ V S = 1 V, RS = 0 Ω, CL = 1 nF; Test Circuit 8 Off Isolation –60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz; –80 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 9 Channel-to-Channel Crosstalk –60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz; –80 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 10 –3 dB Bandwidth ADG706 25 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 ADG707 36 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 CS (OFF) 13 pF typ CD (OFF) ADG706 180 pF typ ADG707 90 pF typ C D, CS (ON) ADG706 200 pF typ ADG707 100 pF typ POWER REQUIREMENTS V DD = 5.5 V IDD 0.001 µA typ Digital Inputs = 0 V or 5.5 V 1.0 µA max NOTES 1Temperature range is as follows: B Version: –40 °C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice.

–3–REV. 0 ADG706/ADG707 B Version –40/H11543C Parameter 25 /H11543C to +85 /H11543C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (RON)6 Ω typ V S = 0 V to VDD, IDS = 10 mA; 11 12 Ω max Test Circuit 1 On-Resistance Match Between 0.4 Ω typ V S = 0 V to VDD, IDS = 10 mA Channels (∆RON) 1.2 Ω max On-Resistance Flatness (R FLAT(ON))3 Ω typ V S = 0 V to VDD, IDS = 10 mA LEAKAGE CURRENTS V DD = 3.3 V Source OFF Leakage IS (OFF) ±0.01 nA typ V S = 3 V/1 V, VD = 1 V/3 V; ±0.1 ±0.3 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ±0.01 nA typ V S = 3 V/1 V, VD = 1 V/3 V; ADG706 ±0.4 ±1.5 nA max Test Circuit 3 ADG707 ±0.1 ±1 nA max Channel ON Leakage ID, IS (ON) ±0.01 nA typ V S = VD = 1 V or 3 V; ADG706 ±0.4 ±1.5 nA max Test Circuit 4 ADG707 ±0.1 ±1 nA max DIGITAL INPUTS Input High Voltage, V INH 2.0 V min Input Low Voltage, V INL 0.4 V max Input Current IINL or IINH 0.005 µA typ V IN = VINL or VINH ±0.1 µA max CIN, Digital Input Capacitance 5 pF typ DYNAMIC CHARACTERISTICS 2 tTRANSITION 45 ns typ R L = 300 Ω, CL = 35 pF, Test Circuit 5 75 ns max V S1 = 2 V/0 V, VS16 = 0 V/2 V Break-Before-Make Time Delay, t D 30 ns typ R L = 300 Ω, CL = 35 pF; 1 ns min V S = 2 V, Test Circuit 6 tON (EN) 40 ns typ R L = 300 Ω, CL = 35 pF; 70 ns max V S = 2 V, Test Circuit 7 tOFF (EN) 20 ns typ R L = 300 Ω, CL = 35 pF; 28 ns max V S = 2 V, Test Circuit 7 Charge Injection ±5 pC typ V S = 1 V, RS = 0 Ω, CL = 1 nF; Test Circuit 8 Off Isolation –60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz; –80 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 9 Channel-to-Channel Crosstalk –60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz; –80 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 10 –3 dB Bandwidth ADG706 25 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 ADG707 36 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 CS (OFF) 13 pF typ CD (OFF) ADG706 180 pF typ ADG707 90 pF typ C D, CS (ON) ADG706 200 pF typ ADG707 100 pF typ POWER REQUIREMENTS V DD = 3.3 V IDD 0.001 µA typ Digital Inputs = 0 V or 3.3 V 1.0 µA max NOTES 1Temperature ranges are as follows: B Versions: –40 °C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = 3 V /H11550 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)SPECIFICATIONS1

–4– REV. 0 ADG706/ADG707 B Version –40/H11543C Parameter 25 /H11543C to +85 /H11543C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V SS to VDD V On Resistance (RON) 2.5 Ω typ V S = VSS to VDD, IDS = 10 mA; 4.5 5 Ω max Test Circuit 1 On-Resistance Match Between 0.3 Ω typ V S = VSS to VDD, IDS = 10 mA Channels (∆RON) 0.8 Ω max On-Resistance Flatness (R FLAT(ON)) 0.5 Ω typ V S = VSS to VDD, IDS = 10 mA 1.2 Ω max LEAKAGE CURRENTS V DD = +3.3 V, VSS = –3.3 V ±0.1 ±0.3 nA max Test Circuit 2 ADG706 ±0.4 ±1.5 nA max Test Circuit 3 ADG707 ±0.1 ±1 nA max Channel ON Leakage ID, IS (ON) ±0.01 nA typ VS = VD = +2.25 V/–1.25 V, Test Circuit 4 ADG706 ±0.4 ±1.5 nA max ADG707 ±0.1 ±1 nA max DIGITAL INPUTS Input High Voltage, V INH 2.0 V min Input Low Voltage, V INL 0.4 V max Input Current IINL or IINH 0.005 µA typ V IN = VINL or VINH ±0.1 µA max CIN, Digital Input Capacitance 5 pF typ DYNAMIC CHARACTERISTICS 2 tTRANSITION 40 ns typ R L = 300 Ω, CL = 35 pF, Test Circuit 5 60 ns max V S1 = 1.5 V/0 V, VS16 = 0 V/1.5 V Break-Before-Make Time Delay, t D 15 ns typ R L = 300 Ω, CL = 35 pF; 1 ns min V S = 1.5 V, Test Circuit 6 tON (EN) 32 ns typ R L = 300 Ω, CL = 35 pF; 50 ns max V S = 1.5 V, Test Circuit 7 tOFF (EN) 16 ns typ R L = 300 Ω, CL = 35 pF; 26 ns max V S = 1.5 V, Test Circuit 7 Charge Injection ±8 pC typ V S = 0 V, RS = 0 Ω, CL = 1 nF; Test Circuit 8 Off Isolation –60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz; –80 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 9 Channel-to-Channel Crosstalk –60 dB typ R L = 50 Ω, CL = 5 pF, f = 10 MHz; –80 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 10 –3 dB Bandwidth ADG706 25 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 ADG707 36 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 CS (OFF) 13 pF typ CD (OFF) ADG706 180 pF typ ADG707 90 pF typ C D, CS (ON) ADG706 200 pF typ ADG707 100 pF typ POWER REQUIREMENTS IDD 0.001 µA typ V DD = +3.3 V 1.0 µA max Digital Inputs = 0 V or 3.3 V ISS 0.001 µA typ V SS = –3.3 V 1.0 µA max Digital Inputs = 0 V or 3.3 V NOTES 1Temperature range is as follows: B Version: –40 °C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = +3 V /H11550 10%, VSS = –3 V /H11550 10%, GND = 0 V, unless otherwise noted.)Dual Supply1

–5–REV. 0 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted) 30 mA, Whichever Occurs First 30 mA, Whichever Occurs First (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range ORDERING GUIDE Model Temperature Range Package Description Package Option ADG706BRU –40 °C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28 ADG707BRU –40 °C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28 PIN CONFIGURATIONS 28-Lead TSSOP NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG706/ADG707 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE TOP VIEW (Not to Scale) ADG706 NC = NO CONNECT NC GND S10 S11 S12 V DD NC NC S16 S13 S14 S15 EN D V SS TOP VIEW (Not to Scale) ADG707 NC = NO CONNECT NC NC GND S1B S2B S3B S4B V DD DB NC S8B S5B S6B S7B EN S1A S2A S3A DA V SS S8A S7A S4A S5A S6A

–6– REV. 0 ADG706/ADG707 Table I. ADG706 Truth Table A3 A2 A1 A0 EN ON Switch XXXX0 NONE 00001 1 00011 2 00101 3 00111 4 01001 5 01011 6 01101 7 01111 8 10001 9 10011 1 0 10101 1 1 10111 1 2 11001 1 3 11011 1 4 11101 1 5 11111 1 6 X = Don’t Care. Table II. ADG707 Truth Table A2 A1 A0 EN ON Switch Pair XXX0 NONE 00011 00112 01013 01114 10015 10116 11017 11118 X = Don’t Care. TERMINOLOGY VDD Most Positive Power Supply Potential. VSS Most Negative Power Supply in a Dual Sup- ply Application. In single supply applications, this should be tied to ground at the device. I DD Positive Supply Current. ISS Negative Supply Current. GND Ground (0 V) Reference. S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. IN Logic Control Input. V D (VS) Analog Voltage on Terminals D, S. RON Ohmic Resistance Between D and S. ∆RON On Resistance Match Between any Two Chan- nels, i.e., RONmax – RONmin. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. I S (OFF) Source Leakage Current with the Switch “OFF.” ID (OFF) Drain Leakage Current with the Switch “OFF.” ID, IS (ON) Channel Leakage Current with the Switch “ON.” VINL Maximum Input Voltage for Logic “0.” VINH Minimum Input Voltage for Logic “1.” IINL(IINH) Input Current of the Digital Input. CS (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. CD (OFF) “OFF” Switch Drain Capacitance. Measured with reference to ground. CD, CS (ON) “ON” Switch Capacitance. Measured with reference to ground. CIN Digital Input Capacitance. tTRANSITION Delay Time Measured Between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition when Switching from One Address State to Another. t ON (EN) Delay Time Between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition. t OFF (EN) Delay Time Between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition. tOPEN “OFF” Time Measured Between the 80% Points of Both Switches when Switching from One Address State to Another. Charge A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output During Switching. Off Isolation A M easure of Unwanted Signal Coupling through an “OFF” Sw itch. Crosstalk A Measure of Unwanted Signal which is Coupled through from One Channel to Another as a R esult of Parasitic Capacitance. Bandwidth The Frequency at which the Output Is Attenuated by 3 dBs. On Response The Frequency Response of the “ON” Switch. Insertion The Loss Due to the ON Resistance of the Loss Switch.

–9–REV. 0 S D VS IDS RON = V1/VDS Test Circuit 1. On Resistance DVS VDD VSS VD S16 GND 0.8V EN VDD VSS A ISOFF Test Circuit 2. IS (OFF) TEST CIRCUITS D VDD VSS VS S16 GND 0.8V EN VDD VSS A IDOFF VDD Test Circuit 3. ID (OFF) D VDD VSS VS S16 GND 2.4VEN VDD VSS A IDON VD Test Circuit 4. ID (ON) D VIN VDD VSS GND D VDD VSS EN 50/H9024 VS1 S16 VS16 VOUT RL 300/H9024 CL 35pF ADG706* S1 THRU S15 *SIMILAR CONNECTION FOR ADG707 2.4V VS1 VS16 VOUT ADDRESS DRIVE (VIN) tTRANSITION tTRANSITION 50% 50% 90% 90% Test Circuit 5. Switching Time of Multiplexer, tTRANSITION D VIN VDD VSS GND D VDD VSS EN 50/H9024 VS S16 VOUT RL 300/H9024 CL 35pF ADG706* S1 THRU S15 *SIMILAR CONNECTION FOR ADG707 2.4V ADDRESS DRIVE (VIN) VOUT VS 80% 80% tOPEN Test Circuit 6. Break-Before-Make Delay, tOPEN

–10– REV. 0 ADG706/ADG707 VIN VDD VSS GND D VDD VSS EN 50/H9024 VS VOUT RL 300/H9024 CL 35pF ADG706* S2 THRU S16 *SIMILAR CONNECTION FOR ADG707 50% 50% tOFF(EN) 0.9VO VO OUTPUT ENABLE DRIVE (VIN) 0.9VO tON(EN) Test Circuit 7. Enable Delay, tON (EN), tOFF (EN) VIN VDD VSS GND D VDD VSS EN VOUT CL 1nF ADG706* *SIMILAR CONNECTION FOR ADG707 VS RS S VOUT QINJ = CL /H11547 /H9004VOUT /H9004VOUT LOGIC INPUT (VIN) Test Circuit 8. Charge Injection VS VDD GND D VDD VSS EN** VOUT RL 50/H9024 ADG706* S16 *SIMILAR CONNECTION FOR ADG707 **CONNECT TO 2.4V FOR BANDWIDTH MEASUREMENTS OFF ISOLATION = 20LOG 10(VOUT/VS) OFF ISOLATION = 20LOG10 VOUT WITH SWITCH ( ) VOUT WITHOUT SWITCH VSS Test Circuit 9. OFF Isolation and Bandwidth VS VDD GND D VDD VSS VOUT RL 50/H9024 ADG706* S16 *SIMILAR CONNECTION FOR ADG707 CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10(VOUT/VS) VSS EN 2.4V 50/H9024 Test Circuit 10. Channel-to-Channel Crosstalk

–11–REV. 0 28-Lead TSSOP (RU-28) 28 15 141 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PRINTED IN U.S.A.