ADG621BRM

ADG621 AD | Alldatasheet

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Technical content

REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADG621/ADG622/ADG623 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 CMOS /H115505 V/5 V 4 /H9024 Dual SPST Switches FUNCTIONAL BLOCK DIAGRAM ADG621 IN1 IN2 ADG622 IN1 IN2 ADG623 IN1 IN2 SWITCHES SHOWN FOR A LOGIC "0" INPUT

FEATURES

5.5 /H9024 (Max) On Resistance 0.9 /H9024 (Max) On-Resistance Flatness 2.7 V to 5.5 V Single Supply /H115502.7 V to /H115505.5 V Dual Supply Rail-to-Rail Operation 10-Lead /H9262SOIC Package Typical Power Consumption (<0.01 /H9262W) TTL/CMOS Compatible Inputs

APPLICATIONS

The ADG621, ADG622, and the ADG623 are monolithic, CMOS SPST (single-pole, single-throw) switches. Each switch of the ADG621, ADG622, and ADG623 conducts equally well in both directions when on. The ADG621/ADG622/ADG623 contain two independent switches. The ADG621 and ADG622 differ only in that both switches are normally open and normally closed respectively. In the ADG623, Switch 1 is normally open and Switch 2 is normally closed. The ADG623 exhibits break-before-make switching action. The ADG621/ADG622/ADG623 offers low on-resistance of 4 Ω, which is matched to within 0.25 Ω between channels. These switches also provide low power dissipation yet gives high sw itching speeds. The ADG621, ADG622, and ADG623 are available in a 10-lead µSOIC package. PRODUCT HIGHLIGHTS 1. Low On Resistance (R ON) (4 Ω typ) 3. Low Power Dissipation. CMOS construction ensures low power dissipation. 4. Tiny 10-Lead µSOIC Package

REV. 0–2– ADG621/ADG622/ADG623–SPECIFICATIONS B Version –40/H11543C to Parameter +25 /H11543C +85 /H11543C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V SS to VDD V VDD = +4.5 V, VSS = –4.5 V On Resistance (RON)4 Ω typ V S = ±4.5 V, IS = –10 mA, 5.5 7 Ω max Test Circuit 1 On Resistance Match Between Channels (∆RON) 0.25 Ω typ V S = ±4.5 V, IS = –10 mA 0.35 0.4 Ω max On-Resistance Flatness (R FLAT(ON)) 0.9 0.9 Ω typ V S = ±3.3 V, IS = –10 mA 1.5 Ω max LEAKAGE CURRENTS V DD = +5.5 V, VSS = –5.5 V Source OFF Leakage I S (OFF) ± 0.01 nA typ V S = ±4.5 V, VD = /H110074.5 V, ± 0.25 ± 1 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ± 0.01 nA typ V S = ±4.5 V, VD = /H110074.5 V, ± 0.25 ± 1 nA max Test Circuit 2 Channel ON Leakage ID, IS (ON) ± 0.01 nA typ V S = VD = ± 4.5 V, Test Circuit 3 ± 0.25 ± 1 nA max DIGITAL INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max Input Current IINL or IINH 0.005 µA typ V IN = VINL or VINH ± 0.1 µA max CIN, Digital Input Capacitance 2 pF typ DYNAMIC CHARACTERISTICS 2 tON 75 ns typ R L = 300 Ω, CL = 35 pF 120 155 ns max V S = 3.3 V, Test Circuit 4 tOFF 45 ns typ R L = 300 Ω, CL = 35 pF 70 85 ns max V S = 3.3 V, Test Circuit 4 Break-Before-Make Time Delay, t BBM 30 ns typ R L = 300 Ω, CL = 35 pF, (ADG623 Only) 10 ns min V S1 = VS2 = 3.3 V, Test Circuit 5 Charge Injection 110 pC typ V S = 0 V, RS = 0 Ω, CL = 1 nF, Test Circuit 7 Off Isolation –65 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 8 Channel-to-Channel Crosstalk –90 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 10 Bandwidth –3 dB 230 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 9 CS (OFF) 20 pF typ f = 1 MHz CD (OFF) 20 pF typ f = 1 MHz CD, CS (ON) 70 pF typ f = 1 MHz POWER REQUIREMENTS V DD = +5.5 V, VSS = –5.5 V IDD 0.001 µA typ Digital Inputs = 0 V or 5.5 V 1.0 µA max ISS 0.001 µA typ Digital Inputs = 0 V or 5.5 V 1.0 µA max NOTES 1Temperature ranges are as follows: B Version, –40°C to +85 °C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. DUAL SUPPLY1 (VDD = +5 V /H11550 10%, VSS = –5 V /H11550 10%, GND = 0 V. All specifications –40 /H11543C to +85/H11543C unless otherwise noted.)

REV. 0 –3– ADG621/ADG622/ADG623 (VDD = +5 V /H11550 10%, VSS = 0 V, GND = 0 V. All specifications –40 /H11543C to +85/H11543C unless otherwise noted.)SINGLE SUPPLY1 B Version –40/H11543C to Parameter +25 /H11543C +85 /H11543C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V VDD = 4.5 V, VSS = 0 V On Resistance (RON)7 Ω typ V S = 0 V to 4.5 V, IS = –10 mA, 10 12.5 Ω max Test Circuit 1 On Resistance Match Between Channels (∆RON) 0.5 Ω typ V S = 0 V to 4.5 V, IS = –10 mA 0.75 1 Ω max On-Resistance Flatness (R FLAT(ON)) 0.5 0.5 Ω typ V S = 1.5 V to 3.3 V, IS = –10 mA 1 Ω max LEAKAGE CURRENTS V DD = 5.5 V Source OFF Leakage I S (OFF) ± 0.01 nA typ V S = 1 V/4.5 V, VD = 4.5 V/1 V, ± 0.25 ± 1 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ± 0.01 nA typ V S = 1 V/4.5 V, VD = 4.5 V/1 V, ± 0.25 ± 1 nA max Test Circuit 2 Channel ON Leakage ID, IS (ON) ± 0.01 nA typ V S = VD = 1 V/4.5 V, ± 0.25 ± 1 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max Input Current IINL or IINH 0.005 µA typ V IN = VINL or VINH ± 0.1 µA max CIN, Digital Input Capacitance 2 pF typ DYNAMIC CHARACTERISTICS 2 tON 120 ns typ R L = 300 Ω, CL = 35 pF 210 260 ns max V S = 3.3 V, Test Circuit 4 tOFF 50 ns typ R L = 300 Ω, CL = 35 pF 75 100 ns max V S = 3.3 V, Test Circuit 4 Break-Before-Make Time Delay, t BBM 70 ns typ R L = 300 Ω, CL = 35 pF, (ADG623 Only) 10 ns min V S1 = VS2 = 3.3 V, Test Circuit 5 Charge Injection 6 pC typ V S = 0 V; RS = 0 Ω, CL = 1 nF, Test Circuit 6 Off Isolation –65 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 7 Channel-to-Channel Crosstalk –90 dB typ R L = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 9 Bandwidth –3 dB 230 MHz typ R L = 50 Ω, CL = 5 pF, Test Circuit 8 CS (OFF) 20 pF typ f = 1 MHz CD (OFF) 20 pF typ f = 1 MHz CD, CS (ON) 70 pF typ f = 1 MHz POWER REQUIREMENTS V DD = 5.5 V IDD 0.001 µA typ Digital Inputs = 0 V or 5.5 V 1.0 µA max NOTES 1Temperature ranges are as follows: B Version, –40°C to +85 °C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice.

REV. 0 ADG621/ADG622/ADG623 –4– ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) 30 mA, Whichever Occurs First (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range µSOIC Package NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. Table I. Truth Table for the ADG621/ADG622 ADG621 INx ADG622 INx Switch x Condition 0 1 OFF

10 O N

Model Option Temperature Range Description Package Branding Information * ADG621BRM –40°C to +85°C µSOIC (microSmall Outline IC) RM-10 SXB ADG622BRM –40°C to +85°C µSOIC (microSmall Outline IC) RM-10 SYB ADG623BRM –40°C to +85°C µSOIC (microSmall Outline IC) RM-10 SZB *Branding on µSOIC packages is limited to three characters due to space constraints. Table II. Truth Table for the ADG623 IN1 IN2 Switch S1 Switch S2

00 O F F O N

10 O N O N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG621/ADG622/ADG623 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

REV. 0 ADG621/ADG622/ADG623 –5– TERMINOLOGY VDD Most Positive Power Supply Potential. VSS Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to ground at the device. GND Ground (0 V) Reference IDD Positive Supply Current ISS Negative Supply Current S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. IN Logic Control Input R ON Ohmic resistance between D and S. ∆RON On resistance match between any two Channels i.e., R ON max – RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (OFF) Source Leakage Current with the switch “OFF.” ID (OFF) Drain Leakage Current with the switch “OFF.” ID, IS (ON) Channel Leakage Current with the switch “ON.” VD (VS) Analog Voltage on Terminals D, S. VINL Maximum Input Voltage for Logic “0.” VINH Minimum Input Voltage for Logic “1.” IINL(IINH) Input Current of the Digital Input CS (OFF) “OFF” Switch Source Capacitance CD (OFF) “OFF” Switch Drain Capacitance CD, CS (ON) “ON” Switch Capacitance tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tBBM “OFF” time or “ON” time measured between the 90% points of both switches, when switching from one address state to another. Charge Injection A measure of the Glitch Impulse transfered from the Digital input to the Analog output during switching. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Bandwidth The frequency response of the “ON” switch. Insertion Loss The loss due to the ON resistance of the Switch. PIN CONFIGURATION 10-Lead /H9262SOIC (RM-10) TOP VIEW (Not to Scale) NC = NO CONNECT GND S2 IN1 VDD ADG621/ ADG622/ ADG623 VSS NC D2IN2

REV. 0 ADG621/ADG622/ADG623 –6– ON RESISTANCE – /H9024 V D, VS – V – 5 – 4 – 3 – 2 – 1 0123 5 4 VDD, VSS = /H115502.5V TA = 25/H11543C VDD, VSS = /H115503V VDD, VSS = /H115503.3V VDD, VSS = /H115504.5V VDD, VSS = /H115505V TPC 1. On Resistance vs. VD (VS). (Dual Supply) VDD = 2.7V VDD = 3V VDD = 3.3V VDD = 4.5V VDD = 5V TA = 25/H11543C VSS = 0V VD, VS – V ON RESIST ANCE – /H9024 123450 TPC 2. On Resistance vs. VD (VS). (Single Supply) VD, VS – V ON RESISTANCE – /H9024 –3 –11 5 3–4 –2 024 VDD = +5V VSS = –5V TA = +85/H11543C TA = +25/H11543C TA = –40/H11543C TPC 3. On Resistance vs. VD (VS) for Different Temperatures. (Dual Supply) –Typical Performance Characteristics VD, VS – V ON RESISTANCE – /H9024 123 5 4 TA = +85/H11543C TA = +25/H11543C TA = –40/H11543C VDD = 5V VSS = 0V TPC 4. On Resistance vs. VD (VS) for Different Temperature. (Single Supply) TEMPERATURE – /H11543C LEAKAGE CURRENT – nA 0 1 02 03 04 05 0 60 70 80 0.5 –0.5 0.2 0.4 0.3 0.1 –0.1 –0.2 –0.3 –0.4 ID (OFF)ID, IS (ON) IS (OFF) VDD = 5V VSS = 0V VD = /H115504.5V VS = /H115514.5V TPC 5. Leakage Currents vs. Temperature. (Dual Supply) ID (OFF) ID, IS (ON) IS (OFF) TEMPERATURE – /H11543C LEAKAGE CURRENT – nA 0 1 02 03 04 05 06 07 08 0 0.5 –0.5 0.2 0.4 0.3 0.1 –0.1 –0.2 –0.3 –0.4 VDD = 5V VSS = 0V VD = 4.5V/1V VS = 1V/4.5V TPC 6. Leakage Currents vs. Temperature. (Single Supply)

REV. 0 ADG621/ADG622/ADG623 –7– VS CHARGE INJECTION – pC 250 TA = 25/H11543C 200 150 100 VDD = 5V VSS = 0V VDD = +5V VSS = –5V TPC 7. Charge Injection vs. Source Voltage TEMPERA TURE – C –40 –20 02 0 40 60 80 TIME – ns 180 160 140 100 120 tON tOFF VDD /H11549 5V VSS /H11549 0V VDD /H11549 +5V VSS /H11549 –5V VDD /H11549 +5V VSS /H11549 –5VVDD /H11549 5V VSS /H11549 0V TPC 8. tON / tOFF Times vs. Temperature 0.2 1 10 100 FREQUENCY – MHz ALTERNATION – dB –10 –20 –30 –40 –50 –60 –70 –80 VDD = +5V VSS = –5V TA = 25/H11543C TPC 9. OFF Isolation vs. Frequency 0.2 100 101 FREQUENCY – MHz ATTENUATION – dB –10 –20 –30 –40 –50 –60 –70 –80 VDD = +5V VSS = –5V TA = 25/H11543C TPC 10. Crosstalk vs. Frequency 0.2 1000 VDD = +5V VSS = –5V TA = 25/H11543C –10 –12 1 100 FREQUENCY – MHz ATTENUATION – dB TPC 11. On Response vs. Frequency

REV. 0–8– ADG621/ADG622/ADG623 Test Circuits IDS SD VS RON = V1/IDS Test Ciruit 1. On Resistance SD VS A A VD IS (OFF) I D (OFF) Test Ciruit 2. Off Leakage SD A VD ID (ON) NC NC = NO CONNECT Test Ciruit 3. On Leakage 0.1/H9262F VS IN SD VDD GND RL 300/H9024 CL 35pF VOUT VDD VIN VIN VOUT tON tOFF 50% 50% 90% 90% 50% 50% VSS VSS 0.1/H9262F ADG621 ADG622 Test Ciruit 4. Switching Times S1 D1 0.1/H9262F VDD IN1, IN2 VS1 GND RL1 300/H9024 CL1 35pF VOUT1 VS2 VOUT2 RL2 300Ω CL2 35pF VIN VDD tBBM tBBM 50% 50% 90% VIN VOUT1 VOUT2 90% 90%90% 0.1/H9262F VSS VSS Test Ciruit 5. Break-Before-Make Time Delay, tBBM (ADG623 Only) SD VDD IN VS GND CL 1nF VOUT RS VDD SW ON VIN VOUT QINJ = CL ∆VOUT/H11547 SW OFF VSS VSS ∆VOUT Test Ciruit 6. Charge Injection

REV. 0 ADG621/ADG622/ADG623 –9– VS VOUT NETWORK ANALYZER RL IN GND VIN S D 50/H9024 OFF ISOLATION = 20 LOG VOUT VS VDD VDD VSS 0.1/H9262F VSS 50/H9024 50/H9024 0.1/H9262F Test Ciruit 7. Off Isolation CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG GND VDD VDD VSS 0.1/H9262F VSS D2S2 VS VOUT NETWORK ANALYZER RL IN VOUT VS R R50/H9024 50/H9024 50/H9024 50/H9024 0.1/H9262F Test Ciruit 8. Channel-to-Channel Crosstalk VS VOUT NETWORK ANALYZER RL IN GND VIN S D INSERTION LOSS = 20 LOG VOUT WITH SWITCH VOUT WITHOUT SWITCH VDD VDD VSS 0.1/H9262F VSS 50/H9024 50/H9024 0.1/H9262F Test Ciruit 9. Bandwidth

REV. 0 ADG621/ADG622/ADG623 –10– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 10-Lead /H9262SOIC Package (RM-10) 0.120 (3.05) 0.112 (2.85) 6/H11543 0/H115430.028 (0.70) 0.016 (0.40) 0.009 (0.23) 0.005 (0.13) 10 6 0.0197 (0.50) BSC 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) PIN 1 0.122 (3.10) 0.114 (2.90) 0.012 (0.30) 0.006 (0.15) 0.037 (0.94) 0.031 (0.78) SEATING PLANE 0.120 (3.05) 0.112 (2.85) 0.043 (1.10) MAX 0.006 (0.15) 0.002 (0.05)

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