ADG612YRUZ-REEL71

ADG611_09 AD | Alldatasheet

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Technical content

1 pC Charge Injection, 100 pA Leakage, CMOS, ±5 V/+5 V/+3 V, Quad SPST Switches ADG611/ADG612/ADG613 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.

FEATURES

±2.7 V to ±5.5 V dual-supply operation +2.7 V to +5.5 V single-supply operation Automotive temperature range: −40°C to +125°C 100 pA maximum at 25°C leakage currents 85 Ω on resistance Rail-to-rail switching operation Fast switching times 16-lead TSSOP and SOIC packages Typical power consumption: <0.1 μW TTL-/CMOS-compatible inputs

APPLICATIONS

1. SWITCHES SHOWN FOR A LOGIC 1 INPUT. IN1 IN2 IN3 IN4 ADG611 IN1 IN2 IN3 IN4 ADG612 IN1 IN2 IN3 IN4 ADG613 02753-001 Figure 1. GENERAL DESCRIPTION The ADG611/ADG612/ADG613 are monolithic CMOS devices containing four independently selectable switches. These switches offer ultralow charge injection of 1 pC over the full input signal range and typical leakage currents of 10 pA at 25°C. The devices are fully specified for ±5 V , +5 V , and +3 V supplies. Each contains four independent single-pole, single-throw (SPST) switches. The ADG611 and ADG612 differ only in that the digital control logic is inverted. The ADG611 switches are turned on with a logic low on the appropriate control input, whereas a logic high is required to turn on the switches of the ADG612. The ADG613 contains two switches with digital control logic similar to that of the ADG611 and two switches in which the logic is inverted. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG613 exhibits break-before-make switching action. The ADG611/ADG612/ADG613 are available in a small, 16-lead TSSOP package, and the ADG611 is also available in a 16-lead SOIC package. PRODUCT HIGHLIGHTS 1. Ultralow charge injection (1 pC typically). 3. Automotive temperature range: −40°C to +125°C. 4. Small, 16-lead TSSOP and SOIC packages.

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

11/09—Rev. 0 to Rev. A Changes to Analog Signal Range Parameter Change to Digital Input Capacitance, CIN Parameter, Table 2 .... 4 1/02—Revision 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS DUAL-SUPPLY OPERATION VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Parameter +25°C −40°C to +85°C −40°C to +125°C1 Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to VDD V On Resistance, RON 85 Ω typ VS = ±3 V, IS = −1 mA; see Figure 14 115 140 160 Ω max VS = ±3 V, IS = −1 mA; see Figure 14 On-Resistance Match Between Channels, ΔRON 2 Ω typ VS = ±3 V, IS = −1 mA 4 5.5 6.5 Ω max VS = ±3 V, IS = −1 mA On-Resistance Flatness, RFLAT(ON) 25 Ω typ VS = ±3 V, IS = −1 mA 40 55 60 Ω max VS = ±3 V, IS = −1 mA LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS(OFF) ±0.01 nA typ VD = ±4.5 V, VS = +4.5 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VD = ±4.5 V, VS = +4.5 V; see Figure 15 Drain Off Leakage, ID(OFF) ±0.01 nA typ VD = ±4.5 V, VS = + 4.5 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VD = ±4.5 V, VS = + 4.5 V; see Figure 15 Channel On Leakage, ID(ON), IS(ON) ±0.01 nA typ VD = VS = ±4.5 V; see Figure 16 ±0.1 ± 0.25 ± 6 nA max VD = VS = ±4.5 V; see Figure 16 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 45 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 65 75 90 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 tOFF 25 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 40 45 50 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 Break-Before-Make Time Delay, tBBM 15 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 Charge Injection −0.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −65 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 −3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 5 pF typ f = 1 MHz CD(ON), CS(ON) 5 pF typ f = 1 MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V 1.0 μA max Digital inputs = 0 V or 5.5 V ISS 0.001 μA typ Digital inputs = 0 V or 5.5 V 1.0 μA max Digital inputs = 0 V or 5.5 V 1 The temperature range for the Y version is −40°C to +125°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 4 of 16 SINGLE-SUPPLY OPERATION VDD = 5 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Parameter +25°C −40°C to +85°C −40°C to +125°C1 Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 210 Ω typ VS = 3.5 V, IS = −1 mA; see Figure 14 290 350 380 Ω max VS = 3.5 V, IS = −1 mA; see Figure 14 On-Resistance Match Between Channels, ΔRON 3 Ω typ VS = 3.5 V, IS = −1 mA 10 12 13 Ω max VS = 3.5 V, IS = −1 mA LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage, IS(OFF) ±0.01 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 Drain Off Leakage, ID(OFF) ±0.01 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 Channel On Leakage, ID(ON), IS(ON) ±0.01 nA typ VS = VD = 1 V or 4.5 V; see Figure 16 ±0.1 ±0.25 ±6 nA max VS = VD = 1 V or 4.5 V; see Figure 16 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 70 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 100 130 150 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 tOFF 25 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 40 45 50 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 Break-Before-Make Time Delay, tBBM 25 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −62 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 −3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 5 pF typ f = 1 MHz CD(ON), CS(ON) 5 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 5.5 V IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V 1.0 μA max Digital inputs = 0 V or 5.5 V 1 The temperature range for the Y version is −40°C to +125°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 5 of 16 VDD = 3 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 3. Parameter +25°C −40°C to +85°C −40°C to +125°C1 Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 380 420 460 Ω typ VS = 1.5 V, IS = −1 mA; see Figure 14 LEAKAGE CURRENTS VDD = 3.3 V Source Off Leakage, IS(OFF) ±0.01 nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 ±0.1 ±0.25 ± 2 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 Drain Off Leakage, ID(OFF) ±0.01 nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 Channel On Leakage, ID(ON), IS(ON) ±0.01 nA typ VS = VD = 1 V or 3 V; see Figure 16 ±0.1 ±0.25 ±6 nA max VS = VD = 1 V or 3 V; see Figure 16 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 130 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 185 230 260 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 tOFF 40 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 55 60 65 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 Break-Before-Make Time Delay, tBBM 50 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 Charge Injection 1.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −62 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 −3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 5 pF typ f = 1 MHz CD(ON), CS(ON) 5 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 3.3 V IDD 0.001 μA typ Digital inputs = 0 V or 3.3 V 1.0 μA max Digital inputs = 0 V or 3.3 V 1 The temperature range for the Y version is −40°C to +125°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 4. Parameter Rating VDD to VSS 13 V VDD to GND −0.3 V to +6.5 V VSS to GND +0.3 V to −6.5 V Analog Inputs1 V SS − 0.3 V to VDD + 0.3 V Digital Inputs1 GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Peak Current, S or D 20 mA (pulsed at 1 ms, 10% duty cycle maximum) Continuous Current, S or D 10 mA 3 V operation 85°C to 125°C 7.5 mA Operating Temperature Range Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 16-Lead TSSOP 150.4°C/W 16-Lead SOIC, 4-Layer Board 80.6°C/W Lead Soldering Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 220°C (Pb-Free) Soldering Reflow, Peak Temperature 260(+0/−5)°C Time at Peak Temperature 20 sec to 40 sec 1Overvoltages at IN, S, or D are clamped by internal diodes. The current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION

Figure 2. Pin Configuration Table 5. Pin Function Descriptions 1 IN1 Switch 1 Digital Control Input. 2 D1 Drain Terminal of Switch 1. Can be an input or output. 3 S1 Source Terminal of Switch 1. Can be an input or output. 4 V SS Most Negative Power Supply Terminal. Tie this pin to GND when using the device with single-supply voltages. 5 GND Ground (0 V) Reference. 6 S4 Source Terminal of Switch 4. Can be an input or output. 7 D4 Drain Terminal of Switch 4. Can be an input or output. 8 IN4 Switch 4 Digital Control Input. 9 IN3 Switch 3 Digital Control Input. 10 D3 Drain Terminal of Switch 3. Can be an input or output. 11 S3 Source Terminal of Switch 3. Can be an input or output. 12 NC Not Internally Connected. 13 V DD Most Positive Power Supply Terminal. 14 S2 Source Terminal of Switch 2. Can be an input or output. 15 D2 Drain Terminal of Switch 2. Can be an input or output. 16 IN2 Switch 2 Digital Control Input. Table 6. ADG611/ADG612 Truth Table Table 7. ADG613 Truth Table

0 Off On

1 On Off

Rev. A | Page 10 of 16 TERMINOLOGY VDD Most positive power supply potential. VSS Most negative power supply potential. I DD Positive supply current. I SS Negative supply current. GND Ground (0 V) reference. S Source terminal. Can be an input or output. D Drain terminal. Can be an input or output. IN Logic control input. V D (VS) Analog voltage on Terminal D and Terminal S. R ON Ohmic resistance between Terminal D and Terminal S. ΔR ON On-resistance match between any two channels, that is, RONMAX − RONMIN. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS(OFF) Source leakage current with the switch off. I D(OFF) Drain leakage current with the switch off. I D(ON), IS(ON) Channel leakage current with the switch on. V INL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. I INL, IINH Input current of the digital input. C S(OFF) Off switch source capacitance. Measured with reference to ground. CD(OFF) Off switch drain capacitance. Measured with reference to ground. CD(ON), CS(ON) On switch capacitance. Measured with reference to ground. C IN Digital input capacitance. t ON Delay between applying the digital control input and the output switching on (see Figure 17). tOFF Delay between applying the digital control input and the output switching off (see Figure 17). Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. On Response Frequency response of the on switch. Insertion Loss Loss due to the on resistance of the switch.

Rev. A | Page 15 of 16 NOTES

Rev. A | Page 16 of 16 NOTES ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D02753-0-11/09(A)