ADG609BRU

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 3 V/5 V, 4/8 Channel High Performance Analog Multiplexers ADG608/ADG609 © Analog Devices, Inc., 1995 Tel: 617/329-4700 Fax: 617/326-8703 GENERAL DESCRIPTION The ADG608 and ADG609 are monolithic CMOS analog mul- tiplexers comprising eight single channels and four differential channels respectively, fully specified for ± 5 V, +5 V and +3 V power supplies. The ADG608 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1 and A2. The ADG609 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both de- vices is used to enable or disable the device. When disabled, all channels are switched OFF. All the address and enable inputs are TTL compatible over the full specified operating tempera- ture range, making the parts suitable for bus-controlled systems such as data acquisition systems, process controls, avionics and ATEs since the TTL compatible address inputs simplify the digital interface design and reduce the board space requirements. The ADG608/ADG609 are designed on an enhanced LC 2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. Each channel conducts equally well in both directions when ON and has an input signal range which extends to the supplies. In the OFF condition, sig- nal levels up to the supplies are blocked. All channels exhibit break-before-make switching action preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. The ability to operate from single +3 V, +5 V or ± 5 V bipolar supplies makes the ADG608 and ADG609 perfect for use in battery operated instruments and with the new generation of DACs and ADCs from Analog Devices. The use of 5 V sup- plies and reduced operating currents gives much lower power dissipation than devices operating from ± 15 V supplies. PRODUCT HIGHLIGHTS 1. Extended Signal Range The ADG608/ADG609 are fabricated on an enhanced LC2MOS process giving an increased signal range which extends to the supplies. 2. Low Power Dissipation 3. Low R ON 4. Fast Switching Times 5. Break-Before-Make Switching Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. Single/Dual Supply Operation ORDERING GUIDE Model Temperature Range Package Option* ADG608BN –40 °C to +85°C N-16 ADG608BR –40 °C to +85°C R-16A ADG608BRU –40 °C to +85°C RU-16 ADG608TRU –55 °C to +125°C RU-16 ADG609BN –40 °C to +85°C N-16 ADG609BR –40 °C to +85°C R-16A ADG609BRU –40 °C to +85°C RU-16 *N = Plastic DIP; RU = Thin Shrink Small Outline Package (TSSOP); R = 0.15" Small Outline IC (SOIC). FUNCTIONAL BLOCK DIAGRAMS D A1 A2 EN

1 OF 8

1 OF 4

FEATURES

+3 V, +5 V, 65 V Power Supplies VSS to V DD Analog Signal Range Low On Resistance (30 V max) Fast Switching Times tON 75 ns max tOFF 45 ns max Low Power Dissipation (1.5 mW max) Break-Before-Make Construction ESD > 5000 V as per Military Standard 3015.7 TTL and CMOS Compatible Inputs

APPLICATIONS

Avionics and Military Systems Microprocessor Controlled Analog Systems Medical Instrumentation Battery Powered Instruments Remote Powered Equipment Compatible with 65 V DACs and ADCs such as

ADG608/ADG609–SPECIFICATIONS REV. A–2– Parameter B Version T Version +258C –40 °C to +25 8C –55 8C to Test Conditions/ +858C +125 8C Units Comments ANALOG SWITCH Analog Signal Range V SS to VDD VSS to VDD V RON 22 22 Ω typ –3.5 V < VS < +3.5 V, IS = –1 mA; 30 35 30 40 Ω max V DD = +4.5 V, VSS = –4.5 V; Test Circuit 1 ΔRON 56 5 6 Ω max –3 V < VS < +3 V, IDS = –1 mA; VDD = +5 V, VSS = –5 V RON Match 2 3 2 3 Ω max V S = 0 V, IDS = –1 mA; VDD = +5 V, VSS = –5 V LEAKAGE CURRENTS VDD = +5.5 V, VSS = –5.5 V Source OFF Leakage I S (OFF) ± 0.05 ± 0.05 nA typ V D = ± 4.5 V, VS = 74.5 V; ± 0.5 ± 2 ± 0.5 ± 10 nA max Test Circuit 2 Drain OFF Leakage I D (OFF) ± 0.05 ± 0.05 nA typ V D = ± 4.5 V, VS = 74.5 V; ADG608 ± 0.5 ± 2 ± 0.5 ± 10 nA max Test Circuit 3 ADG609 ± 0.5 ± 1 ± 0.5 ± 5 nA max Channel ON Leakage I D, IS (ON) ± 0.05 ± 0.05 nA typ V S = VD = ± 4.5 V; ADG608 ± 0.5 ± 3 ± 0.5 ± 20 nA max Test Circuit 4 ADG609 ± 0.5 ± 1.5 ± 0.5 ± 10 nA max DIGITAL INPUTS Input High Voltage, V INH 2.4 2.4 V min Input Low Voltage, V INL 0.8 0.8 V max Input Current IINL or IINH ± 1 ± 1 µA max V IN = 0 or VDD CIN, Digital Input Capacitance 5 5 pF typ DYNAMIC CHARACTERISTICS 2 tTRANSITION 50 50 ns typ R L = 300 Ω , CL = 35 pF; 75 90 75 100 ns max V S1 = ± 3.5 V, VS8 = 73.5 V; Test Circuit 5 tOPEN 10 10 ns min R L = 300 Ω , CL = 35 pF; VS = +3.5 V; Test Circuit 6 tON (EN) 50 50 ns typ R L = 300 Ω , CL = 35 pF; 75 90 75 100 ns max V S = +3.5 V; Test Circuit 7 tOFF (EN) 30 30 ns typ R L = 300 Ω , CL = 35 pF; 45 60 45 75 ns max V S = +3.5 V; Test Circuit 7 Charge Injection 6 6 pC typ V S = 0 V, RS = 0 Ω , CL = 1 nF; Test Circuit 8 OFF Isolation 85 85 dB typ R L = 1 kΩ , CL = 15 pF, f = 100 kHz; VS = 3 V rms; Test Circuit 9 Channel-to-Channel Crosstalk 85 85 dB typ R L = 1 kΩ , CL = 15 pF, f = 100 kHz; Test Circuit 10 CS (OFF) 9 9 pF typ CD (OFF) ADG608 40 40 pF typ ADG609 20 20 pF typ CD (ON) ADG608 54 54 pF typ ADG609 34 34 pF typ POWER REQUIREMENTS IDD 0.05 0.2 0.05 0.2 µA typ V IN = 0 V or VDD 0.2 2 0.2 2 µA max ISS 0.01 0.1 0.01 0.1 µA typ 0.1 1 0.1 1 µA max NOTES 1Temperature ranges are as follows: B Version: –40 °C to +85°C; T Version: –55 °C to +125 °C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. DUAL SUPPLY1 (VDD = +5 V 6 10%, VSS = –5 V 6 10%, GND = 0 V, unless otherwise noted)

Parameter B Version T Version +258C –40 8C to +25 8C –55 8C to Test Conditions/ +858C +125 8C Units Comments ANALOG SWITCH Analog Signal Range 0 to VDD 0 to VDD V RON 40 40 Ω typ V S = +3.5 V, IS = –1 mA; 50 60 50 70 Ω max V DD = +4.5 V; Test Circuit 1 ΔRON 56 5 6 Ω max +1 V < VS < +3 V, IDS = –1 mA; VDD = +5 V RON Match 2 3 2 3 Ω max V S = 0 V, IDS = –1 mA; VDD = +5 V LEAKAGE CURRENTS VDD = +5.5 V ± 0.5 ± 2 ± 0.5 ± 10 nA max Test Circuit 2 ADG608 ± 0.5 ± 2 ± 0.5 ± 10 nA max Test Circuit 3 ADG609 ± 0.5 ± 1 ± 0.5 ± 5 nA max Channel ON Leakage I D, IS (ON) ± 0.05 ± 0.05 nA typ V S = VD = 4.5 V/0.1 V; ADG608 ± 0.5 ± 3 ± 0.5 ± 20 nA max Test Circuit 4 ADG609 ± 0.5 ± 1.5 ± 0.5 ± 10 nA max DIGITAL INPUTS Input High Voltage, V INH 2.4 2.4 V min Input Low Voltage, V INL 0.8 0.8 V max Input Current IINL or IINH ± 1 ± 1 µA max V IN = 0 or VDD CIN, Digital Input Capacitance 5 5 pF typ DYNAMIC CHARACTERISTICS 2 tTRANSITION 80 80 ns typ R L = 300 Ω , CL = 35 pF; 100 130 100 150 ns max V S1 = 3.5 V/0 V, V S8 = 0 V/3.5 V; Test Circuit 5 tOPEN 10 10 ns min R L = 300 Ω , CL = 35 pF; VS = +3.5 V; Test Circuit 6 tON (EN) 80 80 ns typ R L = 300 Ω , CL = 35 pF; 100 130 100 150 ns max V S = +3.5 V; Test Circuit 7 tOFF (EN) 40 40 ns typ R L = 300 Ω , CL = 35 pF; 50 60 50 75 ns max V S = +3.5 V; Test Circuit 7 Charge Injection 0.5 0.5 pC typ V S = 0 V, RS = 0 Ω , CL = 1 nF; 3 3 pC max Test Circuit 8 OFF Isolation 85 85 dB typ R L = 1 kΩ , CL = 15 pF, f = 100 kHz; VS = 1.5 V rms; Test Circuit 9 Channel-to-Channel Crosstalk 85 85 dB typ R L = 1 kΩ , CL = 15 pF, f = 100 kHz; Test Circuit 10 CS (OFF) 9 9 pF typ CD (OFF) ADG608 40 40 pF typ ADG609 20 20 pF typ CD (ON) ADG608 54 54 pF typ ADG609 34 34 pF typ POWER REQUIREMENTS IDD 0.05 0.2 0.05 0.2 µA typ V IN = 0 V or VDD 0.2 2 0.2 2 µA max NOTES 1Temperature ranges are as follows: B Version: –40 °C to +85°C; T Version: –55 °C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. SINGLE SUPPLY1 (VDD = +5 V 6 10%, VSS = 0 V, GND = 0 V, unless otherwise noted) ADG608/ADG609 REV. A –3–

REV. A–4– (VDD = +3.3 V 6 10%, VSS = 0 V, GND = 0 V, unless otherwise noted) Parameter B Version T Version +258C –40 8C to +25 8C –55 8C to Test Conditions/ +858C +125 8C Units Comments ANALOG SWITCH Analog Signal Range 0 to VDD 0 to VDD V RON 60 60 Ω typ V S = +1.5 V, IS = –1 mA; 90 100 90 120 Ω max V DD = +3 V; Test Circuit 1 RON Match 3 3 3 3 Ω max V S = 0 V, IDS = –1 mA, VDD = +3.3 V LEAKAGE CURRENTS VDD = +3.6 V ± 0.5 ± 2 ± 0.5 ± 10 nA max Test Circuit 2 ADG608 ± 0.5 ± 2 ± 0.5 ± 10 nA max Test Circuit 3 ADG609 ± 0.5 ± 1 ± 0.5 ± 5 nA max Channel ON Leakage I D, IS (ON) ± 0.05 ± 0.05 nA typ V S = VD = 2.6 V/0.1 V; ADG608 ± 0.5 ± 3 ± 0.5 ± 20 nA max Test Circuit 4 ADG609 ± 0.5 ± 1.5 ± 0.5 ± 10 nA max DIGITAL INPUTS Input High Voltage, V INH 2.4 2.4 V min Input Low Voltage, V INL 0.8 0.8 V max Input Current IINL or IINH ± 1 ± 1 µA max V IN = 0 or VDD CIN, Digital Input Capacitance 5 5 pF typ DYNAMIC CHARACTERISTICS 2 tTRANSITION 120 120 ns typ R L = 300 Ω , CL = 35 pF; 170 225 170 250 ns max V S1 = 1.5 V/0 V, V S8 = 0 V/1.5 V; Test Circuit 5 tOPEN 10 10 ns min R L = 300 Ω , CL = 35 pF; VS = +1.5 V; Test Circuit 6 tON (EN) 120 120 ns typ R L = 300 Ω , CL = 35 pF; 170 225 170 250 ns max V S = +1.5 V; Test Circuit 7 tOFF (EN) 40 40 ns typ R L = 300 Ω , CL = 35 pF; 60 75 60 90 ns max V S = +1.5 V; Test Circuit 7 Charge Injection 0.5 0.5 pC typ V S = 0 V, RS = 0 Ω , CL = 1 nF; 3 3 pC max Test Circuit 8 OFF Isolation 85 85 dB typ R L = 1 kΩ , CL = 15 pF, f = 100 kHz; VS = 1 V rms; Test Circuit 9 Channel-to-Channel Crosstalk 85 85 dB typ R L = 1 kΩ , CL = 15 pF, f = 100 kHz; Test Circuit 10 CS (OFF) 9 9 pF typ CD (OFF) ADG608 40 40 pF typ ADG609 20 20 pF typ CD (ON) ADG608 54 54 pF typ ADG609 34 34 pF typ POWER REQUIREMENTS IDD 0.05 0.2 0.05 0.2 µA typ V IN = 0 V or VDD 0.2 2 0.2 2 µA max NOTES 1Temperature ranges are as follows: B Version: –40 °C to +85°C; T Version: –55 °C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. ADG608/ADG609–SPECIFICATIONS

REV. A –5– ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) or 20 mA, Whichever Occurs First Peak Current, S or D Operating Temperature Range Plastic DIP Package Lead Temperature, Soldering Lead Temperature, Soldering NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2Overvoltages at A, S, D or EN will be clamped by internal diodes. Current should be limited to the maximum ratings given. PIN CONFIGURATIONS DIP/SOIC/TSSOP DIP/SOIC/TSSOP EN GND S2A S3A S4A S2B S3B S4B VSS S1A VDD S1B DA DB 8 9 TOP VIEW (Not to Scale) ADG609 EN VSS D 8 9 TOP VIEW (Not to Scale) ADG608 GND VDD Table I. ADG608 Truth Table A2 A1 A0 EN ON SWITCH X X X 0 NONE 00 0 1 1 00 1 1 2 01 0 1 3 01 1 1 4 10 0 1 5 10 1 1 6 11 0 1 7 11 1 1 8 X = Don’t Care Table II. ADG609 Truth Table A1 A0 EN ON SWITCH PAIR X X 0 NONE 00 1 1 01 1 2 10 1 3 11 1 4 X = Don’t Care

REV. A–8– ADG608/ADG609 Test Circuits VD VS VSSVDD ID (OFF) VSSVDD +0.8V D EN A GND Test Circuit 3. I D (OFF) ID (ON) VD VS VSSVDD VSSVDD +2.4V D EN A GND Test Circuit 4. I D (ON) IDS S R ON = V1/IDS VS D Test Circuit 1. On Resistance VS IS (OFF) VD VSSVDD VSSVDD +0.8V D EN A GND Test Circuit 2. I S (OFF) Test Circuit 5. Switching Time of Multiplexer, t TRANSITION 50% VOUT tTRANSITION 90% 90% tTRANSITION ADDRESS DRIVE (VIN) 50%A2 VOUT VSSVDD D VS1 * SIMILAR CONNECTION FOR ADG609 EN GND ADG608* S2 THRU S7 VIN +2.4V 50Ω VS8 R L 300Ω C L 35pF VSSVDD

REV. A –9– VOUT VSSVDD D VS * SIMILAR CONNECTION FOR ADG609 EN GND ADG608 * S2 THRU S7VIN +2.4V 50Ω R L 300Ω C L 35pF VSSVDD ADDRESS DRIVE (VIN) VOUT tOPEN 80% 80% Test Circuit 6. Break-Before-Make Delay, t OPEN 50% OUTPUT 0.9V0 50% tON (EN) 0.9V0 tOFF (EN) ENABLE DRIVE (VIN)A2 VOUT VSSVDD D VS * SIMILAR CONNECTION FOR ADG609 EN GND ADG608 * S2 THRU S8 VIN 50Ω R L 300Ω C L 35pF VSSVDD Test Circuit 7. Enable Delay, t ON (EN), tOFF (EN) Δ VOUT VOUT LOGIC INPUT (VIN) Q INJ = CL x ΔVOUT VOUT VSSVDD D * SIMILAR CONNECTION FOR ADG609 EN GND ADG608 * VIN C L 1nF VSSVDD SR S VS Test Circuit 8. Charge Injection

REV. A–10– ADG608/ADG609 VOUT VSS VDD D EN GND ADG608 R L 1kΩ VSS VDD VS 2.4V 1kΩ Test Circuit 10. Channel-to-Channel Crosstalk VOUT VSS VDD D EN GND ADG608 R L 1kΩ VSS VDD VS Test Circuit 9. OFF Isolation TERMINOLOGY VDD Most positive power supply potential. VSS Most negative power supply potential in dual supplies. In single supply applications, it may be connected to ground. GND Ground (0 V) reference. R ON Ohmic resistance between D and S. ΔRON RON variation due to a change in the analog input voltage with a constant load current. RON Match Difference between the R ON of any two channels. IS (OFF) Source leakage current when the switch is off. ID (OFF) Drain leakage current when the switch is off. ID, IS (ON) Channel leakage current when the switch is on. VD, VS Analog voltage on terminals D, S. CS (OFF) Channel input capacitance for “OFF” condition. CD (OFF) Channel output capacitance for “OFF” condition. CD, CS (ON) “ON” switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch “ON” condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch “OFF” condition. t TRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch “ON” condition when switching from one address state to another. t OPEN “OFF” time measured between the 80% points of both switches when switching from one address state to another. VINL Maximum input voltage for logic “0.” VINH Minimum input voltage for logic “1.” IINL (IINH) Input current of the digital input. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. IDD Positive supply current. ISS Negative supply current.

REV. A –11– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic (N-16) 0.840 (21.33) 0.745 (18.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) PIN 1 0.280 (7.11) 0.240 (6.10) 916 0.210 (5.33) 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) 0.070 (1.77) 0.045 (1.15) 16-Pin SOIC (R-16A) 16 9 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 16-Pin TSSOP (RU-16) 16 9 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50)

C2021a–18–4/96PRINTED IN U.S.A. –12–