ADG406_10 AD | Alldatasheet
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High Performance Analog Multiplexers ADG406/ADG407/ADG426 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.
FEATURES
44 V supply maximum ratings
VSS to VDD analog signal range Low on resistance (80 Ω maximum) Low power Fast switching t ON < 160 ns tOFF < 150 ns Break-before-make switching action
APPLICATIONS
- Extended Signal Range. 2. The ADG406/ADG407/ADG426 are fabricated on an enhanced LC2MOS process giving an increased signal range which extends to the supply rails. 3. Low Power Dissipation. 4. Low RON. 5. Single/Dual Supply Operation. 6. Single Supply Operation. 7. For applications where the analog signal is unipolar, the ADG406/ADG407/ADG426 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and remain functional with single supplies as low as +5 V . FUNCTIONAL BLOCK DIAGRAMS 00026-001 S16 D ADG406 A1 A2 EN
1 OF 16
Figure 1. 00026-002 S1A S8B DA ADG407 S8A S1B DB ENA0 A1 A2
1 OF 8
Figure 2. 00026-003 S16 D ADG426 A1 A2 EN DECODER/ LATCHESWR RS Figure 3.
Rev. B | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
5/10—Rev. A to Rev. B 6/09—Rev. 0 to Rev. A 4/94—Revision 0: Initial Version
Rev. B | Page 3 of 20 GENERAL DESCRIPTION The ADG406, ADG407, and ADG426 are monolithic CMOS analog multiplexers. The ADG406 and ADG426 switch one of sixteen inputs to a common output as determined by the 4-bit binary address lines: A0, A1, A2, and A3. The ADG426 has on-chip address and control latches that facilitate microprocessor interfacing. The ADG407 switches one of eight differential inputs to a common differential output as determined by the 3-bit binary address lines A0, A1 and A2. An EN input on all devices is used to enable or disable the device. When disabled, all channels are switched off. The ADG406/ADG407/ADG426 are designed on an enhanced LC 2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. These features make the parts suitable for high speed data acquisition systems and audio signal switching. Low power dissipation makes the parts suitable for battery powered systems. Each channel conducts equally well in both directions when on and has an input signal range which extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All channels exhibit break- before-make switching action preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
Rev. B | Page 4 of 20 SPECIFICATIONS DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to VDD V RON 50 Ω typ VD = ±10 V, IS = −1 mA 80 125 Ω max VDD = +13.5 V, VSS = −13.5 V RON Match 4 Ω typ VD = 0 V, IS = −1 mA LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage IS (Off) ±0.5 ±20 nA max VD = ±10 V, VS = +10 V, see Figure 26 Drain Off Leakage ID (Off) VD = ±10 V, VS = +10 V; see Figure 27 ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max Channel On Leakage ID, IS (On) VS = VD = ±10 V; see Figure 28 ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH ±1 μA max VIN = 0 or VDD CIN, Digital Input Capacitance 8 pF typ f = 1 MHz DYNAMIC CHARACTERISTICS2 tTRANSITION 120 ns typ RL = 300 Ω, CL = 35 pF; V1 = ±10 V, V2 = +10 V; see Figure 29 150 250 ns max Break Before Make Delay, tOPEN 10 10 ns min RL = 300 Ω, CL = 35 pF; VS = +5 V, see Figure 30 tON (EN, WR) 120 175 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31 160 225 ns max tOFF (EN, RS) 110 130 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31 150 180 ns max ADG426 Only tW, Write Pulse Width 100 ns min tS, Address, Enable Setup Time 100 ns min tH, Address, Enable Hold Time 10 ns min tRS, Reset Pulse Width 100 ns min VS = +5 V Charge Injection 8 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; See Figure 34 Off Isolation −75 dB typ RL = 1 k Ω, f = 100 kHz; VEN = 0 V, see Figure 35 Channel-to-Channel Crosstalk 85 dB typ RL = 1 k Ω, f = 100 kHz, see Figure 36 CS (Off ) 5 pF typ f = 1 MHz CD (Off) f = 1 MHz ADG406, ADG426 50 pF typ ADG407 25 pF typ CD, CS (On) f = 1 MHz ADG406, ADG426 60 pF typ ADG407 40 pF typ
Rev. B | Page 5 of 20 Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 1 μA typ VIN = 0 V, VEN = 0 V 5 μA max ISS 1 μA typ 5 μA max IDD 100 μA typ VIN = 0 V, VEN = 2.4 V 200 500 μA max ISS 1 μA typ 5 μA max 1 Temperature ranges is −40°C to +85°C. 2 Guaranteed by design, not subject to production test.
Rev. B | Page 6 of 20 SINGLE SUPPLY VDD = +12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V RON 90 Ω typ VD = +3 V, +8.5 V, IS = −1 mA; 125 200 Ω max VDD = +10.8 V LEAKAGE CURRENTS VDD = +13.2 V Source Off Leakage IS (Off ) ±0.5 ±20 nA max VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 26 Drain Off Leakage ID (Off) VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 27 ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max Channel On Leakage ID, IS (On) VS = VD = 8 V/0.1 V, see Figure 28 ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH ±1 μA max VIN = 0 or VDD CIN, Digital Input Capacitance 8 pF typ f = 1 MHz DYNAMIC CHARACTERISTICS2 tTRANSITION 180 ns typ RL = 300 Ω, CL = 35 pF; V1 = 8 V/0 V, V2 = 0 V/8 V; see Figure 29 220 350 ns max Break Before Make Delay, tOPEN 10 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 30 tON (EN, WR) 180 ns typ RL = 300 Ω, CL = 35 pF; 240 350 ns max VS = +5 V, see Figure 31 tOFF (EN, RS) 135 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31 180 220 ns max ADG426 Only tW, Write Pulse Width 100 ns min tS, Address, Enable Setup Time 100 ns min tH, Address, Enable Hold Time 10 ns min tRS, Reset Pulse Width 100 ns min VS = +5 V Charge Injection 5 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34 Off Isolation −75 dB typ RL = 1 kΩ, f = 100 kHz; see Figure 35 Channel-to-Channel Crosstalk 85 dB typ RL = 1 kΩ, f = 100 kHz; see Figure 36 CS (Off ) 8 pF typ f = 1 MHz CD (Off) f = 1 MHz ADG406, ADG426 80 pF typ ADG407 40 pF typ f = 1 MHz CD, CS (On) ADG406, ADG426 100 pF typ ADG407 50 pF typ POWER REQUIREMENTS VDD = +13.2 V IDD 1 μA typ VIN = 0 V, VEN = 0 V 5 μA max IDD 100 μA typ VIN = 0 V, VEN = 2.4 V 200 500 μA max 1 Temperature range is −40°C to +85°C. 2 Guaranteed by design, not subject to production test.
Rev. B | Page 8 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 3. Parameter Rating VDD to VSS 44 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog, Digital Inputs1 VSS − 2 V to VDD + 2 V or 20 mA, whichever occurs first Continuous Current, S or D 20 mA Peak Current, S or D 40 mA (Pulsed at 1 ms, 10% duty cycle max) Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Plastic Package θJA, Thermal Impedance 75°C/W Lead Temperature, Soldering (10 sec) 260°C θJA, Thermal Impedance 80°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C θJA, Thermal Impedance 122°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 Overvoltages at A, S, D, WR, or RS will be clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
Figure 10. 28-Lead PDIP/SSOP Table 8. Pin Function Descriptions 1 V DD Most Positive Power Supply Potential. 4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. 12 GND Ground (0 V) Reference. 13 WR The rising edge of the WR signal latches the state of the address control lines and the enable line. 14 to 17 A3 to A0 Logic Control Input. is high, the Ax logic inputs determine which switch is turned on. 19 to 26 S1 to S8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. 27 V SS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 D Drain Terminal. This pin can be an input or an output. Table 9. Truth Table (ADG426)
Rev. B | Page 18 of 20 TERMINOLOGY VDD Most positive power supply potential. VSS Most negative power supply potential in dual supplies. In single supply applications, it may be connected to ground. GND Ground (0 V) reference. RON Ohmic resistance between the D and S terminals. RON Match Difference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. I D, IS (On) Channel leakage current when the switch is on. V D (VS) Analog voltage on Terminal D, Terminal S. C S (Off) Channel input capacitance for off condition. C D (Off) Channel output capacitance for off condition. C D, CS (ON) On switch capacitance. C IN Digital input capacitance. t ON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. t TRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t OPEN Off time measured between 80% points of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. V INH Minimum input voltage for Logic 1. I INL (IINH) Input current of the digital input. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. I DD Positive supply current. ISS Negative supply current.
0.05 MIN
0.65 BSC
2.00 MAX
Figure 39. 28-Lead Shrink Small Outline Package [SSOP] 2 N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small Outline Package (SSOP). registered trademarks are the prop erty of their respective owners.