ADG3304WBRUZ-REEL

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Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator Data Sheet ADG3304 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current < 5 µA No direction pin Qualified for automotive applications

APPLICATIONS

SPI®, MICROWIRE™ level translation Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces FUNCTIONAL BLOCK DIAGRAM A1 Y1 GND VCCYVCCA EN A4 Y4 A3 Y3 A2 Y2 04860-001 Figure 1. GENERAL DESCRIPTION The ADG3304 is a bidirectional logic level translator that con- tains four bidirectional channels. It can be used in multivoltage digital system applications, such as data transfer, between a low voltage digital signal processing controller and a higher voltage device using SPI and MICROWIRE interfaces. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to V CCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-com- patible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCA- compatible logic levels on the A side. The enable pin (EN) provides three-state operation on both the A side and the Y side pins. When the EN pin is pulled low, the terminals on both sides of the device are in the high impedance state. The EN pin is referred to the VCCA supply voltage and driven high for normal operation. The ADG3304 is available in compact 14-lead TSSOP , 12-ball WLCSP , and 20-lead LFCSP . It is guaranteed to operate over the 1.15 V to 5.5 V supply voltage range. PRODUCT HIGHLIGHTS 1. Bidirectional level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. Available in 14-lead TSSOP , 12-ball WLCSP , and 20-lead LFCSP .

Rev. D | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

4/13—Rev. C to Rev. D 12/12—Rev. B to Rev. C 12/05—Rev. A to Rev. B 6/05—Rev. 0 to Rev. A 1/05—Revision 0: Initial Version

Rev. D | Page 3 of 20 SPECIFICATIONS Table 1. B Version1 Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS/OUTPUTS A Side Input High Voltage2 VIHA VCCA = 1.2 V + 0.1 V/−0.05 V VCCA × 0.88 V VCCA = 1.8 V ± 0.15 V VCCA × 0.72 V VCCA = 2.5 V ± 0.2 V 1.7 V VCCA = 3.3 V ± 0.3 V 2.2 V VCCA = 5 V ± 0.5 V VCCA × 0.7 V Input Low Voltage2 VILA VCCA = 1.2 V + 0.1 V/−0.05 V VCCA × 0.35 V VCCA = 1.8 V ± 0.15 V VCCA × 0.35 V VCCA = 2.5 V ± 0.2 V 0.7 V VCCA = 3.3 V ± 0.3 V 0.8 V VCCA = 5 V ± 0.5 V VCCA × 0.3 V Output High Voltage VOHA VY = VCCY, IOH = 20 µA, see Figure 29 VCCA − 0.4 V Output Low Voltage VOLA VY = 0 V, IOL = 20 µA, see Figure 29 0.4 V Capacitance2 CA f = 1 MHz, EN = 0, see Figure 34 9 pF Leakage Current ILA, Hi-Z VA = 0 V/VCCA, EN = 0, see Figure 31 ±1 µA Y Side Input High Voltage2 VIHY VCCY = 1.8 V ± 0.15 V VCCY × 0.67 V VCCY = 2.5 V ± 0.2 V 1.7 V VCCY = 3.3 V ± 0.3 V 2 V VCCY = 5 V ± 0.5 V VCCY × 0.7 V Input Low Voltage2 VILY VCCY = 1.8 V ± 0.15 V VCCY × 0.35 V VCCY = 2.5 V ± 0.2 V 0.7 V VCCY = 3.3 V ± 0.3 V 0.8 V VCCY = 5 V ± 0.5 V VCCY × 0.25 V Output High Voltage VOHY VA = VCCA, IOH = 20 µA, see Figure 30 VCCY − 0.4 V Output Low Voltage VOLY VA = 0 V, IOL = 20 µA, see Figure 30 0.4 V Capacitance2 CY f = 1 MHz, EN = 0, see Figure 35 6 pF Leakage Current ILY, Hi-Z VY = 0 V/VCCY, EN = 0, see Figure 32 ±1 µA Enable (EN) Input High Voltage2 VIHEN VCCA = 1.2 V + 0.1 V/−0.05 V VCCA × 0.88 V VCCA = 1.8 V ± 0.15 V VCCA × 0.72 V VCCA = 2.5 V ± 0.2 V 1.7 V VCCA = 3.3 V ± 0.3 V 2.2 V VCCA = 5 V ± 0.5 V VCCA × 0.7 V Input Low Voltage2 VILEN VCCA = 1.2 V + 0.1 V/−0.05 V VCCA × 0.35 V VCCA = 1.8 V ± 0.15 V VCCA × 0.35 V VCCA = 2.5 V ± 0.2 V 0.7 V VCCA = 3.3 V ± 0.3 V 0.8 V VCCA = 5 V ± 0.5 V VCCA × 0.3 V Leakage Current ILEN VEN = 0 V/VCCA, VA = 0 V, see Figure 33 ±1 µA Capacitance2 CEN 3 pF Enable Time2 tEN RS = RT = 50 Ω, VA = 0 V/VCCA (A→Y), VY = 0 V/VCCY (Y→A), see Figure 36 1 1.8 µs

Rev. D | Page 4 of 20 B Version1 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SWITCHING CHARACTERISTICS2 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation RS = RT = 50 Ω, CL = 50 pF, see Figure 37 Propagation Delay tP, A→Y 6 10 ns Rise Time tR, A→Y 2 3.5 ns Fall Time tF, A→Y 2 3.5 ns Maximum Data Rate DMAX, A→Y 50 Mbps Channel-to-Channel Skew tSKEW, A→Y 2 4 ns Part-to-Part Skew tPPSKEW, A→Y 3 ns Y→A Level Translation RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Propagation Delay tP, Y→A 4 7 ns Rise Time tR, Y→A 1 3 ns Fall Time tF, Y→A 3 7 ns Maximum Data Rate DMAX, Y→A 50 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 3.5 ns Part-to-Part Skew tPPSKEW, Y→A 2 ns 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation RS = RT = 50 Ω, CL = 50 pF, see Figure 37 Propagation Delay tP, A→Y 8 11 ns Rise Time tR, A→Y 2 5 ns Fall Time tF, A→Y 2 5 ns Maximum Data Rate DMAX, A→Y 50 Mbps Channel-to-Channel Skew tSKEW, A→Y 2 4 ns Part-to-Part Skew tPPSKEW, A→Y 4 ns Y→A Translation RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Propagation Delay tP, Y→A 5 8 ns Rise Time tR, Y→A 2 3.5 ns Fall Time tF, Y→A 2 3.5 ns Maximum Data Rate DMAX, Y→A 50 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 3 ns Part-to-Part Skew tPPSKEW, Y→A 3 ns 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation RS = RT = 50 Ω, CL = 50 pF, see Figure 37 Propagation Delay tP, A→Y 9 18 ns Rise Time tR, A→Y 3 5 ns Fall Time tF, A→Y 2 5 ns Maximum Data Rate DMAX, A→Y 40 Mbps Channel-to-Channel Skew tSKEW, A→Y 2 5 ns Part-to-Part Skew tPPSKEW, A→Y 10 ns Y→A Translation RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Propagation Delay tP, Y→A 5 9 ns Rise Time tR, Y→A 2 4 ns Fall Time tF, Y→A 2 4 ns Maximum Data Rate DMAX, Y→A 40 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 4 ns Part-to-Part Skew tPPSKEW, Y→A 4 ns

Rev. D | Page 5 of 20 B Version1 Parameter Symbol Test Conditions/Comments Min Typ Max Unit 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Translation RS = RT = 50 Ω, CL = 50 pF, see Figure 37 Propagation Delay tP, A→Y 12 25 ns Rise Time tR, A→Y 7 12 ns Fall Time tF, A→Y 3 5 ns Maximum Data Rate DMAX, A→Y 25 Mbps Channel-to-Channel Skew tSKEW, A→Y 2 5 ns Part-to-Part Skew tPPSKEW, A→Y 15 ns Y→A Translation RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Propagation Delay tP, Y→A 14 35 ns Rise Time tR, Y→A 5 16 ns Fall Time tF, Y→A 2.5 6.5 ns Maximum Data Rate DMAX, Y→A 25 Mbps Channel-to-Channel Skew tSKEW, Y→A 3 6.5 ns Part-to-Part Skew tPPSKEW, Y→A 23.5 ns 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation RS = RT = 50 Ω, CL = 50 pF, see Figure 37 Propagation Delay tP, A→Y 7 10 ns Rise Time tR, A→Y 2.5 4 ns Fall Time tF, A→Y 2 5 ns Maximum Data Rate DMAX, A→Y 60 Mbps Channel-to-Channel Skew tSKEW, A→Y 1.5 2 ns Part-to-Part Skew tPPSKEW, A→Y 4 ns Y→A Translation RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Propagation Delay tP, Y→A 5 8 ns Rise Time tR, Y→A 1 4 ns Fall Time tF, Y→A 3 5 ns Maximum Data Rate DMAX, Y→A 60 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 3 ns Part-to-Part Skew tPPSKEW, Y→A 3 ns POWER REQUIREMENTS Power Supply Voltages VCCA VCCA ≤ VCCY 1.15 5.5 V VCCY 1.65 5.5 V Quiescent Power Supply Current ICCA VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 0.17 5 µA ICCY VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 0.27 5 µA Three-State Mode Power Supply Current IHi-Z, A VCCA = VCCY = 5.5 V, EN = 0 0.1 5 µA IHi-Z, Y VCCA = VCCY = 5.5 V, EN = 0 0.1 5 µA 1 TA for typical specifications is 25°C. 2 Guaranteed by design, not production tested.

Rev. D | Page 6 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter Rating VCCA to GND −0.3 V to +7 V VCCY to GND VCCA to +7 V Digital Inputs (A) −0.3 V to (VCCA + 0.3 V) Digital Inputs (Y) −0.3 V to (VCCY + 0.3 V) EN to GND −0.3 V to +7 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (4-Layer Board) 14-Lead TSSOP 89.21°C/W 12-Ball WLCSP 120°C/W 20-Lead LFCSP 30.4°C/W Lead Temperature, Soldering As per JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION

1 CHANNEL

Figure 5. ICCA vs. Data Rate (A→Y Level Translation) Figure 6. ICCY vs. Data Rate (A→Y Level Translation) Figure 7. ICCA vs. Data Rate (Y→A Level Translation) Figure 8. ICCY vs. Data Rate (Y→A Level Translation) Figure 9. ICCY vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V) Figure 10. ICCA vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V)

Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V) Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V) Figure 13. ICCY vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V) Figure 14. ICCA vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V) Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation) Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 19. Propagation Delay (tPLH) vs. Figure 20. Propagation Delay (tPHL) vs. Figure 21. Propagation Delay (tPLH) vs. Figure 22. Propagation Delay (tPHL) vs.

Figure 23. Eye Diagram at Y Output Figure 24. Eye Diagram at A Output Figure 25. Eye Diagram at Y Output Figure 26. Eye Diagram at A Output Figure 27. Eye Diagram at Y Output Figure 28. Eye Diagram at A Output

Rev. D | Page 15 of 20 TERMINOLOGY VIHA Logic input high voltage at Pin A1 to Pin A4. VILA Logic input low voltage at Pin A1 to Pin A4. VOHA Logic output high voltage at Pin A1 to Pin A4. VOLA Logic output low voltage at Pin A1 to Pin A4. CA Capacitance measured at Pin A1 to Pin A4 (EN = 0). ILA, Hi-Z Leakage current at Pin A1 to Pin A4 when EN = 0 (high impedance state at Pin A1 to Pin A4). VIHY Logic input high voltage at Pin Y1 to Pin Y4. VILY Logic input low voltage at Pin Y1 to Pin Y4. VOHY Logic output high voltage at Pin Y1 to Pin Y4. VOLY Logic output low voltage at Pin Y1 to Pin Y4. CY Capacitance measured at Pin Y1 to Pin Y4 (EN = 0). ILY, Hi-Z Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high impedance state at Pin Y1 to Pin Y4). V IHEN Logic input high voltage at the EN pin. VILEN Logic input low voltage at the EN pin. CEN Capacitance measured at EN pin. ILEN Enable (EN) pin leakage current. tEN Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to Pin Y4. tP, A→Y Propagation delay when translating logic levels in the A→Y direction. tR, A→Y Rise time when translating logic levels in the A→Y direction. TF, A→Y Fall time when translating logic levels in the A→Y direction. DMAX, A→Y Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1. T S K E W, A→Y Difference between propagation delays on any two channels when translating logic levels in the A→Y direction. tPPSKEW , A→Y Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the A→Y direction. tP, Y → A Propagation delay when translating logic levels in the Y→A direction. tR, Y→A Rise time when translating logic levels in the Y→A direction. tF, Y → A Fall time when translating logic levels in the Y→A direction. DMAX, Y→A Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions specified in Table 1. tS K E W, Y → A Difference between propagation delays on any two channels when translating logic levels in the Y→A direction. t PPSKEW , Y→A Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the Y→A direction. VCCA VCCA supply voltage. VCCY VCCY supply voltage. ICCA VCCA supply current. ICCY VCCY supply current. IHi-Z, A VCCA supply current during three-state mode (EN = 0). IHi-Z, Y VCCY supply current during three-state mode (EN = 0).

Figure 39. Simplified Block Diagram of an ADG3304 Channel capacitive load faster, which results in faster rise and fall times. CC rail (VCCA or VCCY) or to GND. minimum peak current driving capability of 36 mA. I/O pins by using the enable pin (EN), as shown in Table 5. Table 5. Truth Table

0 Hi-Z1 Hi-Z1

1 Normal operation2 Normal operation2

2 In normal operation, the ADG3304 performs level translation. the VCCA must be less than or equal to the voltage applied to VCCY. decoupled to GND as close as possible to the device.

and VCCY supply combinations. Table 6. Guaranteed Data Rate (Mbps)1 1 The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.

0.65 BSC

Figure 42. 14-Lead Thin Shrink Small Outline Package [TSSOP] Figure 43. 12-Ball Wafer Level Chip Scale Package [WLCSP]

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.60 MAX

0.25 MIN

Figure 44. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 2 W = Qualified for Automotive Applications. 3 Branding on these packages is limited to three characters due to space constraints. obtain the specific Automotive Reliability reports for these models. registered trademarks are the property of their respective ow ners.