ADG3257BRQ-REEL

ADG3257BRQ-REEL AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch ADG3257 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. 02914-001

FEATURES

100 ps propagation delay through the switch 2 Ω switches connect inputs to outputs Data rates up to 933 Mbps Single 3.3 V/5 V supply operation Level translation operation Ultralow quiescent supply current (1 nA typical) 3.5 ns switching Switches remain in the off state when power is off Standard 3257 type pinout

APPLICATIONS

Memory switching/interleaving FUNCTIONAL BLOCK DIAGRAM S LOGIC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 BE Figure 1. GENERAL DESCRIPTION The ADG3257 is a CMOS bus switch comprised of four 2:1 multiplexers/demultiplexers with high impedance outputs. The device is manufactured on a CMOS process. This provides low power dissipation yet high switching speed and very low on resistance, allowing the inputs to be connected to the outputs without adding propagation delay or generating additional ground bounce noise. The ADG3257 operates from a single 3.3 V/5 V supply. The control logic for each switch is shown in Table 1. These switches are bidirectional when on. In the off state, signal levels are blocked up to the supplies. When the power supply is off, the switches remain in the off state, isolating Port A and Port B. This bus switch is suited to both switching and level translation applications. It can be used in applications requiring level trans- lation from 3.3 V to 2.5 V when powered from 3.3 V . Additionally, with a diode connected in series with 5 V V DD, the ADG3257 may also be used in applications requiring 5 V to 3.3 V level translation. Table 1. Truth Table

1. 0.1 ns propagation delay through switch.
2. 2 Ω switches connect inputs to outputs.
3. Ultralow power dissipation.

Rev. E | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

03/08—Rev. D to Rev. E 11/04—Rev. C to Rev. D 04/03—Rev. A to Rev. B 06/02—Rev. 0 to Rev. A

Rev. E | Page 3 of 12 SPECIFICATIONS VCC = 5.0 V ± 10%, GND = 0 V . All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 Symbol Conditions2 B Version Unit Min Typ 3 Max DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH 2.4 V Input Low Voltage VINL −0.3 +0.8 V Input Leakage Current II 0 ≤ VIN ≤ 5.5 V ±0.01 ±1 μA Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA On State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA Maximum Pass Voltage4 VP VIN = VCC = 5 V, IO = −5 μA 3.9 4.2 4.4 V CAPACITANCE4 A Port Off Capacitance CA OFF f = 1 MHz 7 pF B Port Off Capacitance CB OFF f = 1 MHz 5 pF A, B Port On Capacitance CA, CB ON f = 1 MHz 11 pF Control Input Capacitance CIN f = 1 MHz 4 pF SWITCHING CHARACTERISTICS4 Propagation Delay A to B or B to A, tPD tPHL, tPLH5 VA = 0 V, CL = 50 pF 0.10 ns Propagation Delay Matching6 VA = 0 V, CL = 50 pF 0.0075 0.035 ns Bus Enable Time BE to A or B tPZH, tPZL CL = 50 pF, RL = 500 Ω 1 5 7.5 ns Bus Disable Time BE to A or B tPHZ, tPLZ C L = 50 pF, RL = 500 Ω 1 3.5 7 ns Bus Select Time S to A or B Enable tSEL_EN CL = 50 pF, RL = 500 Ω 8 12 ns Disable tSEL_DIS C L = 50 pF, RL = 500 Ω 5 8 ns Maximum Data Rate VA = 2 V p-p 933 Mbps DIGITAL SWITCH On Resistance RON VA = 0 V IO = 48 mA, 15 mA, 8 mA, TA = 25°C 2 4 Ω IO = 48 mA, 15 mA, 8 mA 5 Ω VA = 2.4 V IO = 48 mA, 15 mA, 8 mA, TA = 25°C 3 6 Ω IO = 48 mA, 15 mA, 8 mA 7 Ω On-Resistance Matching ΔRON VA = 0 V, IO = 48 mA, 15 mA, 8 mA 0.15 Ω POWER REQUIREMENTS VCC 3.0 5.5 V Quiescent Power Supply Current ICC Digital inputs = 0 V or VCC 0.001 1 μA Increase in ICC per Input4, 7 ΔICC V CC = 5.5 V, one input at 3.0 V; others at VCC or GND 200 μA 1 Temperature range is: Version B: –40°C to +85°C. 2 See Test Circuits section. 3 All typical values are at TA = 25°C, unless otherwise noted. 4 Guaranteed by design, not subject to production test. 5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance. 7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute no significant ac or dc currents as they transition.

Rev. E | Page 4 of 12 VCC = 3.3 V ± 10%, GND = 0 V . All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1 Symbol Conditions2 B Version Unit Min Typ 3 Max DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH 2.0 V Input Low Voltage VINL −0.3 +0.8 V Input Leakage Current II 0 ≤ VIN ≤ 3.6 V ±0.01 ±1 μA Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA On State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA Maximum Pass Voltage4 VP VIN = VCC = 3.3 V, IO = −5 μA 2.3 2.6 2.8 V CAPACITANCE4 A Port Off Capacitance CA OFF f = 1 MHz 7 pF B Port Off Capacitance CB OFF f = 1 MHz 5 pF A, B Port On Capacitance CA, CB ON f = 1 MHz 11 pF Control Input Capacitance CIN f = 1 MHz 4 pF SWITCHING CHARACTERISTICS4 Propagation Delay A to B or B to A, tPD tPHL, tPLH5 VA = 0 V, CL = 50 pF 0.10 ns Propagation Delay Matching6 VA = 0 V, CL = 50 pF 0.01 0.04 ns Bus Enable Time BE to A or B tPZH, tPZL CL = 50 pF, RL = 500 Ω 1 5.5 9 ns Bus Disable Time BE to A or B tPHZ, tPLZ CL = 50 pF, RL = 500 Ω 1 4.5 8.5 ns Bus Select Time S to A or B Enable tSEL_EN CL = 50 pF, RL = 500 Ω 8 12 ns Disable tSEL_DIS CL = 50 pF, RL = 500 Ω 6 9 ns Maximum Data Rate VA = 2 V p-p 933 Mbps DIGITAL SWITCH On Resistance RON V A = 0 V, IO = 15 mA, 8 mA, TA = 25°C 2 4 Ω VA= 0 V, Io = 15 mA, 8 mA 5 Ω VA = 1 V, IO = 15 mA, 8 mA, TA = 25°C 4 7 Ω VA= 1 V, Io = 15 mA, 8 mA 8 Ω On-Resistance Matching ΔRON V A = 0 V, IO = 15 mA, 8 mA 0.2 Ω POWER REQUIREMENTS VCC 3.0 5.5 V Quiescent Power Supply Current ICC Digital inputs = 0 V or VCC 0.001 1 μA Increase in ICC per Input4, 7 ΔICC V CC = 3.3 V, one input at 3.0 V; others at VCC or GND 200 μA 1 Temperature range is: Version B: −40°C to +85°C. 2 See Test Circuits section. 3 All typical values are at TA = 25°C, unless otherwise noted. 4 Guaranteed by design, not subject to production test. 5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance. 7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute no significant ac or dc currents as they transition.

Rev. E | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VCC to GND −0.3 V to +6 V Digital Inputs to GND −0.3 V to +6 V DC Input Voltage −0.3 V to +6 V DC Output Current 100 mA Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 149.97°C/W Lead Soldering Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 220°C Soldering (Pb-Free) Reflow, Peak Temperature 260(+0/−5)°C Time at Peak Temperature 20 sec to 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sec- tion of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. Pin Configuration Table 5. Pin Function Descriptions 4, 7, 9, 12 1A, 2A, 3A, 4A Port A, Inputs or Outputs. 8 GND Negative Power Supply. 15 BE Output Enable (Active Low). 16 V CC Positive Power Supply.

Figure 19. 16-Lead Shrink Small Outline Package [QSOP]

Rev. E | Page 12 of 12 NOTES ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D02914-0-3/08(E)