ADG3246BCP

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REV. 0 ADG3246 2.5 V/3.3 V, 10-Bit, 2-Port Level Translating, Bus Switch Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

FEATURES

225 ps Propagation Delay through the Switch 4.5 /H9024 Switch Connection between Ports Data Rate 1.244 Gbps 2.5 V/3.3 V Supply Operation Selectable Level Shifting/Translation Small Signal Bandwidth 610 MHz Level Translation 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V 24-Lead TSSOP and LFCSP Packages

APPLICATIONS

3.3 V to 1.8 V Voltage Translation 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Bus Switching Bus Isolation Hot Swap Hot Plug Analog Signal Switching FUNCTIONAL BLOCK DIAGRAM A9 B9 A0 B0 BE GENERAL DESCRIPTION The ADG3246 is a 2.5 V or 3.3 V, 10-bit, 2-port digital switch. It is designed on Analog Devices’ low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance, allowing inputs to be connected to outputs without additional propagation delay or generating additional ground bounce noise. The switches are enabled by means of the bus enable ( BE) input signal. These digital switches allow bidirectional signals to be switched when ON. In the OFF condition, signal levels up to the supplies are blocked. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs occurs. Similarly, if the device is oper- ated from a 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition to this, the ADG3246 has a level translating select pin (SEL). When SEL is low, V CC is reduced internally, allowing for level translation between 3.3 V inputs and 1.8 V outputs. This makes the device suited to appli- cations requiring level translation between different supplies, such as converter to DSP/microcontroller interfacing. PRODUCT HIGHLIGHTS 1. 3.3 V or 2.5 V supply operation 2. Extremely low propagation delay through switch 3. 4.5 W switches connect inputs to outputs 4. Level/voltage translation 5. 24-lead 4 mm ¥ 4 mm LFCSP and 24-lead TSSOP packages

REV. 0–2– ADG3246–SPECIFICATIONS1 (VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T MIN to TMAX, unless otherwise noted.) B Version Parameter Symbol Conditions Min Typ 2 Max Unit DC ELECTRICAL CHARACTERISTICS Input High Voltage V INH VCC = 2.7 V to 3.6 V 2.0 V VINH VCC = 2.3 V to 2.7 V 1.7 V Input Low Voltage V INL VCC = 2.7 V to 3.6 V 0.8 V VINL VCC = 2.3 V to 2.7 V 0.7 V Input Leakage Current I I ± 0.01 ± 1 mA OFF State Leakage Current I OZ 0 £ A, B £ VCC ± 0.01 ± 1 mA ON State Leakage Current 0 £ A, B £ VCC ± 0.01 ± 1 mA Maximum Pass Voltage V P VA/VB = VCC = SEL = 3.3 V, IO = –5 mA 2.0 2.5 2.9 V VA/VB = VCC = SEL = 2.5 V, IO = –5 mA 1.5 1.8 2.1 V VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 mA 1.5 1.8 2.1 V CAPACITANCE3 A Port Off Capacitance C A OFF f = 1 MHz 5 pF B Port Off Capacitance C B OFF f = 1 MHz 5 pF A, B Port On Capacitance C A, CB ON f = 1 MHz 10 pF Control Input Capacitance C IN f = 1 MHz 6 pF SWITCHING CHARACTERISTICS 3 Propagation Delay A to B or B to A, t PD 4 tPHL, tPLH CL = 50 pF, VCC = SEL = 3 V 0.225 ns Propagation Delay Matching 5 22.5 ps Bus Enable Time BE to A or B6 tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = VCC 1 3.2 4.8 ns Bus Disable Time BE to A or B6 tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = VCC 1 3.2 4.8 ns Bus Enable Time BE to A or B6 tPZH, tPZL VCC = 2.3 V to 2.7 V; SEL = VCC 0.5 2.2 3 ns Maximum Data Rate V CC = SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps Channel Jitter V CC = SEL = 3.3 V; VA/VB = 2 V 50 ps p-p Operating Frequency—Bus Enable f BE 10 MHz DIGITAL SWITCH On Resistance R ON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 W VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 15 28 W VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 W VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 11 18 W VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA 5 8 W VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 14 W On Resistance Matching /H9004RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 0.45 W VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 0.65 W POWER REQUIREMENTS VCC 2.3 3.6 V Quiescent Power Supply Current I CC Digital Inputs = 0 V or V CC; SEL = VCC 0.001 1 mA ICC Digital Inputs = 0 V or V CC; SEL = 0 V 0.65 1.2 mA Increase in I CC per Input7 /H9004ICC VCC = 3.6 V, BE = 3.0 V; SEL = VCC 130 mA NOTES 1Temperature range is as follows: B Version: –40 ∞C to +85∞C. 2Typical values are at 25 ∞C, unless otherwise stated. 3Guaranteed by design, not subject to production test. 4The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propag ation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its inte raction with the load on the driven side. 5Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. 6See Timing Measurement Information section. 7This current applies to the control pin ( BE) only. The A and B ports contribute no significant ac or dc currents as they transition. Specifications subject to change without notice.

REV. 0 ADG3246 –3– ABSOLUTE MAXIMUM RATINGS * (TA = 25°C, unless otherwise noted.) Operating Temperature Range /H9258 *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Table I. Pin Description Mnemonic Description BE Bus Enable (Active Low) SEL Level Translation Select Ax Port A, Inputs or Outputs Bx Port B, Inputs or Outputs PIN CONFIGURATION 24-Lead LFCSP and TSSOP PIN 1 INDICATOR TOP VIEW 18 BE 17 B0 16 B1 15 B2 SEL 1 A5 2 A6 3 24 A4 14 B3 13 B4 GND 7 B9 8 B8 9 B7 10 B6 11 B5 12 A7 4 A8 5 A9 6 23 A3 22 A2 21 A1 20 A0 19 V CC ADG3246 GND BE SEL V CC TOP VIEW (Not to Scale) ADG3246 Table II. Truth Table BE SEL * Function LL A = B, 3.3 V to 1.8 V Level Shifting LH A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting HX Disconnect *SEL = 0 only when V DD = 3.3 V ± 10% CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3246 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Range Package Description Package Option ADG3246BCP –40 °C to +85°CL ead Frame Chip Scale Package (LFCSP) CP-24 ADG3246BCP-REEL7 –40 °C to +85°CL ead Frame Chip Scale Package (LFCSP) CP-24 ADG3246BRU –40 °C to +85°CT hin Shrink Small Outline Package (TSSOP) RU-24 ADG3246BRU-REEL7 –40 °C to +85°CT hin Shrink Small Outline Package (TSSOP) RU-24

REV. 0–4– ADG3246 TERMINOLOGY VCC Positive Power Supply Voltage. GND Ground (0 V) Reference. VINH Minimum Input Voltage for Logic 1. VINL Maximum Input Voltage for Logic 0. II Input Leakage Current at the Control Inputs. IOZ OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state. IOL ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state. VP Maximum Pass Voltage. The maximum pass voltage relates to the clipped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. RON Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch. /H9004R ON On Resistance Match between Any Two Channels, i.e., R ON Max – RON Min. CX OFF OFF Switch Capacitance. CX ON ON Switch Capacitance. CIN Control Input Capacitance. This consists of BE and SEL. ICC Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF. /H9004ICC Extra power supply current component for the BE control input when the input is not criven at the supplies. tPLH, tPHL Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON ¥ CL, where CL is the load capacitance. tPZH, tPZL Bus Enable Times. These are times taken to cross the V T voltage at the switch output when the switch turns on in response to the control signal, BE. tPHZ, tPLZ Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control signal. It is measured as the time taken for the output voltage to change by V /H9004 from the original quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.) Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch. Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel. fBE Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable ( BE) can be toggled.

REV. 0 Typical Performance Characteristics–ADG3246 –5– VA/VB – V RON – /H9024 00 0.5 TA = 25/H11543C SEL = VCC 1.5 2.5 3.5 VCC = 3V VCC = 3.3V VCC = 3.6V 3.02.01.0 TPC 1. On Resistance vs. Input Voltage VA/VB – V RON – /H9024 00 0.5 1.5 2.01.0 /H1154525/H11543C /H1154585/H11543C /H1154640/H11543C = 3.3V SEL = VCC VCC TPC 4. On Resistance vs. Input Voltage for Different Temperatures VCC – V VOUT – V 00 0.5 0.5 1.5 2.5 1.5 2.5 VCC = 2.7V VCC = 2.5V VCC = 2.3V TA = 25/H11543C SEL = VCC IO = –5/H9262A2.0 1.0 1.0 2.0 3.0 TPC 7. Pass Voltage vs. V CC VA/VB – V RON – /H9024 00 0.5 1.5 2.5 VCC = 2.3V VCC = 2.5V VCC = 2.7V TA = 25/H11543C SEL = VCC 3.02.01.0 TPC 2. On Resistance vs. Input Voltage VA/VB – V RON – /H9024 00 0.5 /H1154585/H11543C /H1154525/H11543C 1.0 /H1154640/H11543C = 2.5V SEL = VCC VCC 1.2 TPC 5. On Resistance vs. Input Voltage for Different Temperatures VCC – V VOUT – V 00 0.5 0.5 1.5 2.5 1.5 2.5 VCC = 3.6V VCC = 3.3V VCC = 3V 3.5 TA = 25/H11543C SEL = 0V IO = –5/H9262A2.0 1.0 1.0 2.0 3.0 TPC 8. Pass Voltage vs. V CC VA/VB – V RON – /H9024 00 0.5 1.5 2.5 VCC = 3V VCC = 3.3V VCC = 3.6V 3.5 TA = 25/H11543C SEL = 0V 1.0 2.0 3.0 TPC 3. On Resistance vs. Input Voltage VCC – V VOUT – V 00 0.5 0.5 1.5 2.5 1.5 2.5 3.5 VCC = 3.6V VCC = 3.3V VCC = 3V 3.0 2.0 1.0 1.0 2.0 3.0 TA = 25/H11543C SEL = VCC IO = –5/H9262A TPC 6. Pass Voltage vs. V CC ENABLE FREQUENCY – MHz ICC – /H9262A 002 4 200 68 1 0 TA = 25/H11543C VCC = 3.3V, SEL = 0V 14 16 18 20 400 600 800 1000 1200 1400 1600 1800 VCC = SEL = 3.3V VCC = SEL = 2.5V TPC 9. I CC vs. Enable Frequency

REV. 0–6– ADG3246 IO – A VOUT – V 0.5 1.0 1.5 2.0 2.5 3.0 VCC = 3.3V; SEL = 0V VCC = SEL = 3.3V VCC = SEL = 2.5V TA = 25/H11543C VA = 0V BE = 0 TPC 10. Output Low Characteristic FREQUENCY – MHz ATTENUA TION – dB 0.03 0.1 1000 11 0 100 –10 –12 TA = 25/H11543C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER : RL = RS = 50/H9024 –14 TPC 13. Bandwidth vs. Frequency TEMPERATURE – /H11543C –40 0.5 1.5 2.5 3.5 –20 0 20 40 60 80 100 ENABLE DISABLE ENABLE DISABLE VCC = SEL = 3.3V VCC = 3.3V, SEL = 0V 3.0 2.0

1.0 TIME – ns

TPC 16. Enable/Disable Time vs. Temperature IO – A VOUT – V –0.10 0.5 1.0 1.5 2.0 2.5 3.0 TA = 25/H11543C VA = VCC BE = 0 VCC = SEL = 2.5V VCC = 3.3V; SEL = 0V VCC = SEL = 3.3V TPC 11. Output High Characteristic FREQUENCY – MHz ATTENUA TION – dB 0.03 0.1 1000 11 0 100 –80 –90 –70 –60 –50 –40 –30 –20 –100 TA = 25/H11543C VCC = 3.3V/2.5V SEL = VCC ADJACENT CHANNELS VIN = 0dBm N/W ANALYZER : RL = RS = 50/H9024 TPC 14. Crosstalk vs. Frequency TEMPERATURE – /H11543C TIME – ns –40 0.5 1.5 2.5 –20 0 20 40 60 80 100 ENABLE DISABLE VCC = SEL = 2.5V 2.0 1.0 TPC 17. Enable/Disable Time vs. Temperature VA/VB – V QINJ – pC –2.0 0 0.5 –1.0 –0.2 1.5 2.5 –0.4 –0.6 –0.8 –1.2 –1.4 –1.8 1.0 2.0 3.0 –1.6 VCC = 3.3V VCC = 2.5V TA = 25/H11543C SEL = VCC ON OFF CL = InF TPC 12. Charge Injection vs. Source Voltage FREQUENCY – MHz ATTENUA TION – dB 0.03 0.1 1000 11 0 100 –80 –90 –70 –60 –50 –40 –30 –20 TA = 25/H11543C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER : RL = RS = 50/H9024 –100 TPC 15. Off Isolation vs. Frequency DATA RATE – Gbps JITTER – ps 0.5 0.6 100 VCC = SEL = 3.3V VIN = 2V p-p 20dB ATTENUATION TPC 18. Jitter vs. Data Rate; PRBS 31

REV. 0 ADG3246 –7– DATA RATE – Gbps EYE WIDTH – % 0.5 0.6 100 % EYE WIDTH = ((CLOCK PERIOD – JITTER p-p)/CLOCK PERIOD) /H11547 100% VCC = SEL = 3.3V VIN = 2V p-p 20dB ATTENUATION TPC 19. Eye Width vs. Data Rate; PRBS 31 50.1mV/DIV 50ps/DIV TA = 25/H11543C 20dB ATTENUA TION VCC = 3.3V SEL = 3.3V VIN = 2V p-p TPC 22. Jitter @ 1.244 Gbps, PRBS 31 VCC = 3.3V SEL = 3.3V VIN = 2V p-p 20dB ATTENUA TION TA = 25/H11543C 35mV/DIV 100ps/DIV TPC 20. Eye Pattern; 1.244 Gbps, VCC = 3.3 V, PRBS 31 37mV/DIV 200ps/DIV VCC = 2.5V SEL = 2.5V VIN = 2V p-p 20dB ATTENUA TION TA = 25/H11543C TPC 21. Eye Pattern; 1 Gbps, VCC = 2.5 V, PRBS 31

REV. 0 ADG3246 –11– OUTLINE DIMENSIONS 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm /H11547 4 mm Body (CP-24) Dimensions shown in millimeters 124 713 BOTTOM VIEW 2.25 1.70 0.75

0.60 MAX

0.50 0.40 0.30 0.30 0.23 0.18 2.50 REF 0.50 BSC 12/H11543 MAX

0.80 MAX

0.65 NOM

0.05 MAX

0.02 NOM

1.00 0.90 0.85 SEA TING PLANE PIN 1 INDICA TOR TOP VIEW 3.75 BSC SQ 4.0 BSC SQ 0.25 MIN PIN 1 INDICA TOR 0.25 REF COMPLIANT TO JEDEC ST ANDARDS MO-220-VGGD-2 0.08 SQ

0.20 REF

24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 24 13 121

6.40 BSC

4.50 4.40 4.30 PIN 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 BSC 1.20 MAX 0.20 0.09 0.75 0.60 0.45 8/H11543 0/H11543SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-153AD

0.10 COPLANARITY

C03012–0–5/03(0) –12–