ADG3241

ADG3241_15 AD | Alldatasheet

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2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG3241 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FUNCTIONAL BLOCK DIAGRAM FEATURES 225 ps propagation delay through the switch BE A B 04221-001 4.5 Ω switch connection between ports Data rate 1.5 Gbps 2.5 V/3.3 V supply operation Selectable level shifting/translation Level translation Figure 1. 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V Small signal bandwidth 770 MHz Tiny 6-lead SC70 package and 6-lead SOT-66 package

APPLICATIONS

3.3 V to 1.8 V voltage translation 3.3 V to 2.5 V voltage translation 2.5 V to 1.8 V voltage translation Bus switching Bus isolation Hot swap Hot plug Analog switch applications GENERAL DESCRIPTION The ADG3241 is a 2.5 V or 3.3 V single digital switch. It is designed on a low voltage CMOS process that provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. The switch is enabled by means of the bus enable (BE) input signal. This digital switch allows a bidirectional signal to be switched when on. In the off condition, signal levels up to the supplies are blocked. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device translates the outputs to 1.8 V . In addition to this, a level translating select pin (SEL SEL) is included. When is low, VCC is reduced internally, allowing for level translation between 3.3 V inputs and 1.8 V outputs. This makes the device suited to applications requiring level translation between different supplies, such as converter to DSP/microcontroller interfacing. PRODUCT HIGHLIGHTS 1. 3.3 V or 2.5 V supply operation. 2. Extremely low propagation delay through switch. 3. 4.5 Ω switches connect inputs to outputs. 4. Level and voltage translation. 5. Tiny, SC70 package and SOT-66 package.

Rev. B | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

5/06 — Rev. A to Rev. B 10/04 — Rev. 0 to Rev. A. 7/03—Revision 0: Initial Version

Rev. B | Page 3 of 16 SPECIFICATIONS VCC = 2.3 V to 3.6 V , GND = 0 V , all specifications TMIN to TMAX, unless otherwise noted.1 Table 1. B Version Parameter Symbol Conditions Min Typ2 Max Unit DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH VCC = 2.7 V to 3.6 V 2.0 V VINH VCC = 2.3 V to 2.7 V 1.7 V Input Low Voltage VINL VCC = 2.7 V to 3.6 V 0.8 V VINL VCC = 2.3 V to 2.7 V 0.7 V Input Leakage Current II ±0.01 ±1 μA Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA On State Leakage Current 0 ≤ A, B ≤ VCC ±0.01 ±1 μA Maximum Pass Voltage VP VA/VB = VCC = SEL = 3.3 V, IO = −5 μA 2.2 2.5 2.7 V VA/VB = VCC = SEL = 2.5 V, IO = −5 μA 1.5 1.8 2.1 V VA/VB = VCC = 3.3 V, SEL = 0 V, IO = −5 μA 1.5 1.8 2.1 V CAPACITANCE3 A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF B Port Off Capacitance CB OFF f = 1 MHz 3.5 pF A, B Port On Capacitance CA, CB ON f = 1 MHz 7 pF Control Input Capacitance CIN f = 1 MHz 4 pF SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 tPHL, tPLH CL = 50 pF, VCC = SEL = 3 V 0.225 ns Bus Enable Time BE to A or B5 tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = VCC 1 3.2 4.6 ns Bus Disable Time BE to A or B5 tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = VCC 1 3 4 ns Bus Enable Time BE to A or B5 tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = 0 V 1 3 4 ns Bus Disable Time BE to A or B5 tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = 0 V 1 2.5 3.8 ns Bus Enable Time BE to A or B5 tPZH, tPZL VCC = 2.3 V to 2.7 V; SEL = VCC 1 3 4 ns Bus Disable Time BE to A or B5 tPHZ, tPLZ VCC = 2.3 V to 2.7 V; SEL = VCC 1 2.5 3.4 ns Maximum Data Rate VCC = SEL = 3.3 V; VA/VB = 2 V 1.5 Gbps Channel Jitter VCC = SEL = 3.3 V; VA/VB = 2 V 45 ps p-p DIGITAL SWITCH On Resistance RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 Ω VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 12 28 Ω VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 Ω VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 9 18 Ω VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA 5 8 Ω VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 12 Ω POWER REQUIREMENTS VCC 2.3 3.6 V Quiescent Power Supply Current ICC Digital Inputs = 0 V or VCC; SEL = VCC 0.01 1 μA Digital Inputs = 0 V or VCC; SEL = 0 V 0.1 0.2 mA Increase in ICC per Input6 ∆ICC VCC = 3.6 V, BE = 3.0 V; SEL = VCC 0.15 8 μA 1 Temperature range is as follows: B Version: −40°C to +85°C. 2 Typical values are at 25°C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 See Timing Measurement Information section. 6 This current applies to the Control Pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.

Rev. B | Page 4 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VCC to GND −0.5 V to +4.6 V Digital Inputs to GND −0.5 V to +4.6 V DC Input Voltage −0.5 V to +4.6 V DC Output Current 25 mA per channel Operating Temperature Range Only one absolute maximum rating can be applied at any one time. Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 332°C/W θJA Thermal Impedance 191°C/W (4-layer board) Lead Temperature, Soldering (10 sec) 300°C 235°C IR Reflow, Peak Temperature (<20 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. 6-Lead SOT-66 Figure 2. 6-Lead SC70 Table 3. Pin Function Descriptions Table 4. Truth Table

Figure 4. On Resistance vs. Input Voltage Figure 7. On Resistance vs. Input Voltage for Different Temperatures Figure 5. On Resistance vs. Input Voltage Figure 8. On Resistance vs. Input Voltage for Different Temperatures

1.0 VOUT (V)

Figure 9. Pass Voltage vs. VCC Figure 6. On Resistance vs. Input Voltage

Figure 10. Pass Voltage vs. VCC Figure 13. Output Low Characteristic

Rev. B | Page 10 of 16 TERMINOLOGY VCC Positive power supply voltage. GND Ground (0 V) reference. VINH Minimum input voltage for Logic 1. V INL Maximum input voltage for Logic 0. I I Input leakage current at the control inputs. IOZ Off state leakage current. It is the maximum leakage current at the switch pin in the off state. IOL On state leakage current. It is the maximum leakage current at the switch pin in the on state. VP Maximum pass voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. RON Ohmic resistance offered by a switch in the on state. It is measured at a given voltage by forcing a specified amount of current through the switch. CX OFF Off switch capacitance. C X ON On switch capacitance. CIN Control input capacitance. This consists of BE and SEL. ICC Quiescent power supply current. This current represents the leakage current between the VCC and ground pins. It is measured when all control inputs are at a logic high or low level and the switches are off. ΔI CC Extra power supply current component for the BE control input when the input is not driven at the supplies. tPLH, tPHL Data propagation delay through the switch in the on state. Propagation delay is related to the RC time constant RON × CL, where CL is the load capacitance. tPZH, tPZL Bus enable times. These are the times taken to cross the VT voltage at the switch output when the switch turns on in response to the control signal, BE. tPHZ, tPLZ Bus disable times. These are the times taken to place the switch in the high impedance off state in response to the control signal. It is measured as the time taken for the output voltage to change by V Δ from the original quiescent level, with reference to the logic level transition at the control input. Refer to Figure 26 for enable and disable times. Max Data Rate Maximum rate at which data can be passed through the switch. Channel Jitter Peak-to-peak value of the sum of the deterministic and random jitter of the switch channel.

minimal propagation delay, timing skew, or noise. Figure 27. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor

0 V to VCC, the maximum output signal will be clamped to

within a voltage threshold below the VCC supply. Figure 28. 3.3 V to 2.5 V Voltage Translation, SEL = VCC In this case, the output is limited to 2.5 V , as shown in Figure 29. devices and also between two 3.3 V devices. Figure 29. 3.3 V to 2.5 V Voltage Translation, SEL = VCC

0 V to VCC, the maximum output signal is, as before, clamped to

output is limited to approximately 1.8 V , as shown in Figure 31. Figure 30. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC Figure 31. 2.5 V to 1.8 V Voltage Translation, SEL = VCC translation between 3.3 V devices and 1.8 V devices. Figure 32. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V Figure 32. To do this, the SEL pin must be tied to Logic 0. If SEL is unused, it should be tied directly to VCC.

0.65 BSC

1.30 BSC

0.10 MAX

0.10 COPLANARITY

Figure 36. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

0.34 MAX

0.27 NOM

0.10 NOM

0.05 MIN

0.20 MIN

0.25 MAX

0.17 MIN

Figure 37. 6-Lead Small Outline Transistor Package [SOT-66]

Rev. B | Page 15 of 16 NOTES

Rev. B | Page 16 of 16 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04221-0-4/06(B)