ADG3123

ADG3123 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 12

Technical content

High Voltage Level Translator Data Sheet ADG3123 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

2.3 V to 5.5 V input voltage range Output voltage levels (VDDA and VDDB to VSS ≤ 35 V) Low output voltage levels: down to −24.2 V High output voltage levels: up to +35 V Rise/fall time: 12 ns/19.5 ns typical Propagation delay: 80 ns typical Operating frequency: 100 kHz typical Ultralow quiescent current: 65 μA typical 20-lead, Pb-free, TSSOP package

APPLICATIONS

Low voltage to high voltage translation TFT-LCD panels Piezoelectric motor drivers FUNCTIONAL BLOCK DIAGRAM 05655-001 VDDA ADG3123 VDDB CHANNELS VSS GND CHANNELS Figure 1. GENERAL DESCRIPTION The ADG3123 is an 8-channel, noninverting CMOS to high voltage level translator. Fabricated on an enhanced LC2MOS process, the device is capable of operating at high supply voltages while maintaining ultralow power consumption. The internal architecture of the device ensures compatibility with logic circuits running from supply voltages within the 2.3 V to 5.5 V range. The voltages applied to Pin VDDA, Pin VDDB, and Pin VSS set the logic levels available at the outputs on the Y side of the device. Pin VDDA and Pin VDDB set the high output level for Pin Y1 to Pin Y6 and for Pin Y7 to Pin Y8, respectively. The VSS pin sets the low output level for all channels. The ADG3123 can provide output voltages levels down to −24.2 V for a low input level and up to +35 V for a high input logic level. For proper operation, VDDB must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. The low output impedance of the channels guarantees fast rise and fall times even for significant capacitive loads. This feature, combined with low propagation delay and low power consumption, makes the ADG3123 an ideal driver for TFT-LCD panel applications. The ADG3123 is guaranteed to operate over the −40°C to +85°C temperature range and is available in a compact, 20-lead TSSOP, Pb-free package. PRODUCT HIGHLIGHTS 1. Compatible with a wide range of CMOS logic levels. 2. High output voltage levels. 3. Fast rise and fall times coupled with low propagation delay. 4. Ultralow power consumption. 5. Compact, 20-lead TSSOP, RoHS-compliant package.

Rev. B | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

1/13—Rev. A to Rev. B 5/06—Rev. 0 to Rev. A Changes to Features Section, General Description Section, and Changes to Theory of Operations Section and Power Supplies 9/05—Revision 0: Initial Version

VDDA = VDDB = 27 V, VSS = −7 V, GND = 0 V, unless otherwise noted. Temperature range for B version is −40°C to +85°C. 1 Typical values are specified at 25°C. 2 Guaranteed by design; not subject to production testing. Figure 2. Switching Characteristics Test Circuit

Rev. B | Page 4 of 12 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter Rating VDDA/VDDB to VSS 44 V VDDB to GND −0.3 V to +32 V VDDA to GND −0.3 V to VDDB VSS to GND +0.3 V to −32 V Digital Inputs1 VSS − 0.3 V to VDDB + 0.3 V or 20 mA, whichever occurs first Load Current Per Device Average 15 mA at 25°C 8 mA at 85°C Peak Current2 150 mA at 25°C 80 mA at 85°C Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Junction Temperature 150°C Thermal Impedance, θJA 78°C/W3 Reflow Soldering (Pb-Free) Peak Temperature 260 (+0/−5)°C Time at Peak Temperature 10 seconds to 40 seconds 1 Overvoltage at Pin A1 to Pin A8 is clamped by internal diodes. Limit the current to the maximum ratings given. 2 Pulsed at 100 kHz; 10% duty cycle maximum with the load shown in Figure 2. 3 Guaranteed when the device is soldered on a 4-layer board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION

Figure 3. Pin Configuration Table 3. Pin Function Descriptions 1 GND Ground Reference (0 V). 2 to 9 A1 to A8 Level Translator CMOS Inputs. 10 VSS Most Negative Power Supply. Use the VSS pin to generate the output low level for Output Y1 to Output Y8. 11 VDDB Positive Power Supply. Use the VDDB pin to generate the output high level for Output Y7 and Output Y8. 12 to 19 Y8 to Y1 Level Translator High Voltage Outputs. 20 VDDA Analog Input. Use the VDDA pin to generate the output high level for Output Y1 to Output Y6 (VDDA ≤ VDDB).

1 CHANNEL

Figure 4. Supply Current (IDDB) vs. Frequency Figure 5. Supply Current (IDDA) vs. Frequency Figure 6. Supply Current (ISS) vs. Frequency Figure 7. Supply Current (IDDB) vs. Capacitive Load Figure 8. Supply Current (IDDA) vs. Capacitive Load Figure 9. Supply Current (ISS) vs. Capacitive Load

Figure 10. Rise Time vs. Capacitive Load Figure 11. Fall Time vs. Capacitive Load Figure 12. Propagation Delay (tPLH) vs. Capacitive Load Figure 13. Propagation Delay (tPHL) vs. Capacitive Load Figure 14. Maximum Operating Frequency vs. Capacitive Load

8 CHANNELS

Figure 15. Maximum Operating Frequency vs. Capacitive Load

Figure 16. Output Voltage (VOL) vs. Load Current Figure 17. Output Voltage (VOH) vs. Load Current

Rev. B | Page 9 of 12 TERMINOLOGY VIH Logic input high voltage at Pin A1 to Pin A8. VIL Logic input low voltage at Pin A1 to Pin A8. IIL Leakage current at Pin A1 to Pin A8. CI Capacitance measured at Pin A1 to Pin A8. VOH Logic output high voltage at Pin Y1 to Pin Y8. VOL Logic output low voltage at Pin Y1 to Pin Y8. Ro Output impedance. tPLH Propagation delay through the part measured between the input signal applied to any one channel and its corresponding output for a low-to-high transition (see Figure 2). tPHL Propagation delay through the part measured between the input signal applied to any one channel and its corresponding output for a high-to-low transition (see Figure 2). t R Rise time of the output signal at Pin Y1 to Pin Y8 (see Figure 2). tF Fall time of the output signal at the Pin Y1 to Pin Y8 (see Figure 2). FO Frequency of the signal applied to the A1 to A8 input pins. VDDA Input voltage used to generate the high logic levels for Y1 to Y6 outputs. VDDB Positive power supply voltage. Also used to generate the high logic levels for Y7 to Y8 outputs. VSS Negative power supply voltage. It is used to generate the low logic level for Y1 to Y8 outputs. GND Ground (0 V) reference. IDDA Supply current at the VDDA pin. IDDB Supply current at the VDDB pin. ISS Supply current at the VSS pin.

Rev. B | Page 10 of 12 THEORY OF OPERATION The ADG3123 is an 8-channel, noninverting CMOS to high voltage level translator. Fabricated on an enhanced LC2MOS process, the device is capable of operating at high supply voltages while maintaining ultralow power consumption. The device requires a dual-supply voltage, VDDB and VSS, which sets the low logic levels for all outputs and the high logic levels for the Y7 and Y8 outputs. The VDDA pin acts as an analog input. The voltage applied to the VDDA pin sets the output high logic level for the Y1 to Y6 outputs. The device translates the CMOS logic levels applied to the A1 to A8 inputs into high voltage bipolar levels available on the Y side of the device at Pin Y1 to Pin Y8. To ensure proper operation, VDDB must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. INPUT DRIVING REQUIREMENTS The ADG3123 design ensures low input capacitance and leakage current thereby reducing the loading of the circuit that drives the input pins (Pin A1 to Pin A8) to a minimum. Its input threshold levels are compliant with JEDEC standards for drivers operated from supply voltages between 2.3 V and 5.5 V. It is recommended that the inputs of any unused channel be tied to a stable logic level (low or high). OUTPUT LOAD REQUIREMENTS The low output impedance of the ADG3123 allows each channel to drive both resistive and capacitive loads. The maximum load current is limited by the current carrying capability of any given channel. If more channels are used, the maximum load current per channel is reduced accordingly. Note that the sum of the load currents on all channels should never exceed the absolute maximum ratings specifications. The average load current on each channel, I CHANNEL, can be determined using the formulas shown in the Capacitive Loads and the Resistive Loads sections. Capacitive Loads ICHANNEL (A) = FO × CL × (VDDX + |VSS|) where: FO is the frequency of the signal applied to the channel in Hz. CL is the load capacitance in farads. VSS is the voltage applied to the VSS pin. VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs. Resistive Loads L SSDDX CHANNEL R VDVDAI ×−+×= )1()( where: D is the duty cycle of the input signal. D is defined as the ratio between the high state duration of the signal and its period. RL is the load resistor in Ω. VSS is the voltage applied to the VSS pin. VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs. POWER SUPPLIES The ADG3123 operates from a dual-supply voltage. As good design practice for all CMOS devices dictates, power up the ADG3123 first (VDDB and VSS) before applying the signals to its inputs (A1 to A8 and VDDA). To ensure correct operation of the ADG3123, the voltage applied to the VDDB pin must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. To ensure optimum performance, use decoupling capacitors on all power supply pins. Furthermore, good engineering and layout practice suggests placing these capacitors as close as possible to the package supply pins.

ADG3123, make the device ideal for LCD-TFT panel applications. inside the panel are usually low voltage CMOS devices. Figure 18. Typical Application Circuit

6.40 BSC

Figure 19. 20-Lead Thin Shrink Small Outline Package [TSSOP] registered trademarks are the property of their respective owners.