ADG2128BCPZ-HS-RL7

ADG2128 AD | Alldatasheet

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I2C® CMOS 8 × 12 Unbuffered Analog Switch Array With Dual/Single Supplies ADG2128 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

3.4 MHz high speed I2C option

32-lead LFCSP_VQ (5 mm × 5 mm) Double-buffered input logic Simultaneous update of multiple switches Up to 300 MHz bandwidth Fully specified at dual ±5 V/single +12 V operation On resistance 35 Ω maximum Low quiescent current < 20 μA

APPLICATIONS

Test equipment/instrumentation PBX systems GENERAL DESCRIPTION The ADG2128 is an analog cross point switch with an array size of 8 × 12. The switch array is arranged so that there are eight columns by 12 rows, for a total of 96 switch channels. The array is bidirectional, and the rows and columns can be configured as either inputs or outputs. Each of the 96 switches can be addressed and configured through the I 2C- compatible interface. Standard, full speed, and high speed (3.4 MHz) I2C interfaces are supported. Any simultaneous switch combination is allowed. An additional feature of the ADG2128 is that switches can be updated simultaneously, using the LDSW command. In addition, a RESET option allows all of the switch channels to be reset/off. At power-on, all switches are in the off condition. The device is packaged in a 32-lead, 5 mm × 5 mm LFCSP_VQ. FUNCTIONAL BLOCK DIAGRAM ADG2128 VDD VSS VL SCL SDA X0 TO X11 (I/O)8 × 12 SWITCH ARRAY LDSW 1INPUT REGISTER AND

7 TO 96

GNDA0 A1 A2 Y0 TO Y7 (I/O) 05464-001 Figure 1.

Rev. A | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

5/06—Rev. 0 to Rev. A 1/06—Revision 0: Initial Version

Rev. A | Page 3 of 28 SPECIFICATIONS VDD = 12 V ± 10%, VSS = 0 V , VL = 5 V , GND = 0 V , all specifications TMIN to TMAX, unless otherwise noted.1 Table 1. B Version Y Version Parameter +25°C −40°C to +85°C +25°C −40°C to +125°C Unit Conditions ANALOG SWITCH Analog Signal Range VDD − 2 V VDD − 2 V V max On Resistance, RON 30 30 Ω typ VDD = +10.8 V, VIN = 0 V, IS = −10 mA 35 40 35 42 Ω max 32 32 Ω typ VDD = +10.8 V, VIN = +1.4 V, IS = −10 mA 37 42 37 47 Ω max 45 45 Ω typ VDD = +10.8 V, VIN = +5.4 V, IS = −10 mA 50 57 50 62 Ω max On Resistance Matching 4.5 4.5 Ω typ VDD = +10.8 V, VIN = 0 V, IS = −10 mA Between Channels, ∆RON 8 9 8 10 Ω max On Resistance Flatness, RFLAT(ON) 2.3 2.3 Ω typ VDD = 10.8 V, VIN = 0 V to +1.4 V, IS = −10 mA 3.5 4 3.5 5 Ω max 14.5 14.5 Ω typ VDD = 10.8 V, VIN = 0 V to +5.4 V, IS = −10 mA 18 20 18 22 Ω max LEAKAGE CURRENTS VDD = 13.2 V Channel Off Leakage, IOFF ±0.03 ±0.03 μA typ VX = 7 V/1 V, VY = 1 V/7 V Channel On Leakage, ION ±0.03 ±0.03 μA typ VX = VY = 1 V or 7 V DYNAMIC CHARACTERISTICS2 COFF 11 11 pF typ CON 18.5 18.5 pF typ tON 170 170 ns typ RL = 300 Ω, CL = 35 pF 185 190 185 195 ns max tOFF 210 210 ns typ RL = 300 Ω, CL = 35 pF 250 255 250 260 ns max THD + N 0.04 0.04 % typ RL = 10 kΩ, f = 20 Hz to 20 kHz, VS = 1 V p-p PSRR 90 dB typ f = 20 kHz; without decoupling; see Figure 24 −3 dB Bandwidth 210 210 MHz typ Individual inputs to outputs 16.5 16.5 MHz typ 8 inputs to 1 output Off Isolation −69 −69 dB typ RL = 75 Ω, CL = 5 pF, f = 5 MHz Channel-to-Channel Crosstalk RL = 75 Ω, CL = 5 pF, f = 5 MHz Adjacent Channels −63 −63 dB typ Nonadjacent Channels −76 −76 dB typ Differential Gain 0.4 0.4 % typ RL = 75 Ω, CL = 5 pF, f = 5 MHz Differential Phase 0.6 0.6 ° typ RL = 75 Ω, CL = 5 pF, f = 5 MHz Charge Injection −3.5 −3.5 pC typ VS = 4 V, RS = 0 Ω, CL = 1 nF LOGIC INPUTS (Ax, RESET)2 Input High Voltage, VINH 2.0 2.0 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current, IIN 0.005 0.005 μA typ ±1 ±1 μA max Input Capacitance, CIN 7 7 pF typ

Rev. A | Page 4 of 28 B Version Y Version Parameter +25°C −40°C to +85°C +25°C −40°C to +125°C Unit Conditions LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH 0.7 VL 0.7 VL V min VL + 0.3 VL + 0.3 V max Input Low Voltage, VINL −0.3 −0.3 V min 0.3 VL 0.3 VL V max Input Leakage Current, IIN 0.005 0.005 μA typ VIN = 0 V to VL ±1 ±1 μA max Input Hysteresis 0.05 VL 0.05 VL V min Input Capacitance, CIN 7 7 pF typ LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL 0.4 0.4 V max ISINK = 3 mA 0.6 0.6 V max ISINK = 6 mA Floating State Leakage Current ±1 ±1 μA max POWER REQUIREMENTS IDD 0.05 0.05 μA typ Digital inputs = 0 V or VL 1 1 μA max ISS 0.05 0.05 μA typ Digital inputs = 0 V or VL 1 1 μA max IL Digital inputs = 0 V or VL Interface Inactive 0.3 0.3 μA typ 2 2 μA max Interface Active: 400 kHz fSCL 0.1 0.1 mA typ 0.2 0.2 mA max Interface Active: 3.4 MHz fSCL 0.4 0.4 mA typ -HS model only 1.2 1.7 mA max 1 Temperature range is as follows: B version: −40°C to +85°C; Y version: −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 28 VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 5 V , GND = 0 V , all specifications TMIN to TMAX, unless otherwise noted.1 Table 2. B Version Y Version Parameter +25°C −40°C to +125°C +25°C −40°C to +125°C Unit Conditions ANALOG SWITCH Analog Signal Range VDD − 2 V V max On Resistance, RON 34 34 Ω typ VDD = +4.5 V, VSS = −4.5 V, VIN = VSS, IS = −10 mA 40 45 40 50 Ω max 50 50 Ω typ VDD = +4.5 V, VSS = −4.5 V, VIN = 0 V, IS = −10 mA 55 65 55 70 Ω max 66 66 Ω typ VDD = +4.5 V, VSS = −4.5 V, VIN = +1.4 V, IS = −10 mA 75 85 75 95 Ω max On Resistance Matching 4.5 4.5 Ω typ VDD = +4.5 V, VSS = −4.5 V, VIN = VSS, IS = −10 mA Between Channels, ∆RON 8 9 8 10 Ω max On Resistance Flatness, RFLAT(ON) 17 17 Ω typ VDD = +4.5 V, VSS = −4.5 V, VIN = VSS to 0 V, IS = −10 mA 20 23 20 25 Ω max 34 34 Ω typ VDD = +4.5 V, VSS = −4.5 V, VIN = VSS to +1.4 V, IS = −10 mA 42 45 42 48 Ω max LEAKAGE CURRENTS VDD = 5.5 V, VSS = 5.5 V Channel Off Leakage, IOFF ±0.03 ±0.03 μA typ VX = +4.5 V/−2 V, VY = −2 V/+4.5 V Channel On Leakage, ION ±0.03 ±0.03 μA typ VX = VY = −2 V or +4.5 V DYNAMIC CHARACTERISTICS2 COFF 6 6 pF typ CON 9.5 9.5 pF typ tON 170 170 ns typ RL = 300 Ω, CL = 35 pF 200 215 200 220 ns max tOFF 210 210 ns typ RL = 300 Ω, CL = 35 pF 250 255 250 260 ns max THD + N 0.04 0.04 % typ RL = 10 kΩ, f = 20 Hz to 20 kHz, VS = 1 V p-p PSRR 90 dB typ f = 20 kHz; without decoupling; see Figure 24 −3 dB Bandwidth 300 300 MHz typ Individual inputs to outputs 18 18 MHz typ 8 inputs to 1 output Off Isolation −66 −64 dB typ RL = 75 Ω, CL = 5 pF, f = 5 MHz Channel-to-Channel Crosstalk RL = 75 Ω, CL = 5 pF, f = 5 MHz Adjacent Channels −62 −62 dB typ Nonadjacent Channels −79 −79 dB typ Differential Gain 1.5 1.5 % typ RL = 75 Ω, CL = 5 pF, f = 5 MHz Differential Phase 1.8 1.8 ° typ RL = 75 Ω, CL = 5 pF, f = 5 MHz Charge Injection −3 −3 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF LOGIC INPUTS (Ax, RESET)2 Input High Voltage, VINH 2.0 2.0 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current, IIN 0.005 0.005 μA typ ±1 ±1 μA max Input Capacitance, CIN 7 7 pF typ LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH 0.7 VL 0.7 VL V min VL + 0.3 VL + 0.3 V max Input Low Voltage, VINL −0.3 −0.3 V min 0.3 VL 0.3 VL V max

Rev. A | Page 6 of 28 B Version Y Version Parameter +25°C −40°C to +125°C +25°C −40°C to +125°C Unit Conditions Input Leakage Current, IIN 0.005 0.005 μA typ VIN = 0 V to VL ±1 ±1 μA max Input Hysteresis 0.05 VL 0.05 VL V min Input Capacitance, CIN 7 7 pF typ LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL 0.4 0.4 V max ISINK = 3 mA 0.6 0.6 V max ISINK = 6 mA Floating State Leakage Current ±1 ±1 μA max POWER REQUIREMENTS IDD 0.05 0.005 μA typ Digital inputs = 0 V or VL 1 1 μA max ISS 0.05 0.005 μA typ Digital inputs = 0 V or VL 1 1 μA max IL Digital inputs = 0 V or VL Interface Inactive 0.3 0.3 μA typ 2 2 μA max Interface Active: 400 kHz fSCL 0.1 0.1 mA typ 0.1 0.1 mA max Interface Active: 3.4 MHz fSCL 0.4 0.4 mA typ -HS model only 0.3 0.3 mA max 1 Temperature range is as follows: B version: –40°C to +85°C; Y version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. A | Page 7 of 28 I2C TIMING SPECIFICATIONS VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2). Table 3. ADG2108 Limit at TMIN, TMAX Parameter1 Conditions Min Max Unit Description fSCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz High speed mode2 CB = 100 pF maximum 3.4 MHz CB = 400 pF maximum 1.7 MHz t1 Standard mode 4 μs tHIGH, SCL high time Fast mode 0.6 μs High speed mode2 CB = 100 pF maximum 60 ns CB = 400 pF maximum 120 ns t2 Standard mode 4.7 μs tLOW, SCL low time Fast mode 1.3 μs High speed mode2 CB = 100 pF maximum 160 ns CB = 400 pF maximum 320 ns t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns High speed mode2 10 ns t43 Standard mode 0 3.45 μs tHD;DAT, data hold time Fast mode 0 0.9 μs High speed mode2 CB = 100 pF maximum 0 70 ns CB = 400 pF maximum 0 150 ns t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition Fast mode 0.6 μs High speed mode2 160 ns t6 Standard mode 4 μs tHD;STA, hold time for a repeated start condition Fast mode 0.6 μs High speed mode2 160 ns t7 Standard mode 4.7 μs tBUF, bus free time between a stop and a start condition Fast mode 1.3 μs t8 Standard mode 4 μs tSU;STO, setup time for a stop condition Fast mode 0.6 μs High speed mode2 160 ns t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CB B 300 ns High speed mode2 CB = 100 pF maximum 10 80 ns CB = 400 pF maximum 20 160 ns t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CBB 300 ns High speed mode2 CB = 100 pF maximum 10 80 ns CB = 400 pF maximum 20 160 ns

2 High speed I2C is available only in -HS models. 3 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge. Figure 2. Timing Diagram for 2-Wire Serial Interface

Rev. A | Page 9 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to VSS 15 V VDD to GND −0.3 V to +15 V VSS to GND +0.3 V to −7 V VL to GND −0.3 V to +7 V Analog Inputs VSS − 0.3 V to VDD + 0.3 V Digital Inputs −0.3 V to VL + 0.3 V or 30 mA, whichever occurs first Continuous Current

10 V on Input; Single Input

Connected to Single Output 65 mA

1 V on Input; Single Input

Connected to Single Output 90 mA

10 V on Input; Eight Inputs

Connected to Eight Outputs 25 mA Operating Temperature Range Industrial (B Version) –40°C to +85°C Automotive (Y Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 32-Lead LFCSP_VQ θJA Thermal Impedance 108.2°C/W Reflow Soldering (Pb Free) Peak Temperature 260°C (+0/–5) Time at Peak Temperature 10 sec to 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 5. Pin Function Descriptions1 1 VSS Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin should be tied to GND. X0 to X11 Can be inputs or outputs. 9 to 16 Y0 to Y7 Can be inputs or outputs. 24 VDD Positive Power Supply Input. 25 VL Logic Power Supply Input. 26 SDA Digital I/O. Bidirectional open drain data line. External pull-up resistor required. device. External pull-up resistor required. 28 A0 Logic Input. Address pin that sets the least significant bit of the 7-bit slave address. 29 A1 Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address. 30 A2 Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address. 31 RESET Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0. 32 GND Ground Reference Point for All Circuitry on the ADG2128. 1 It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.

Figure 16. TON/TOFF Times vs. Temperature Figure 17. Individual Inputs to Individual Outputs Bandwidth, Figure 18. Individual Inputs to Individual Outputs Bandwidth,

12 V Single Supply

Figure 19. One Input to Eight Outputs Bandwidth, 5 V Dual Supply Figure 20. Off Isolation vs. Frequency Figure 21. Crosstalk vs. Frequency

Figure 32. Channel-to-Channel Crosstalk

Rev. A | Page 17 of 28 TERMINOLOGY On Resistance (RON) The series on-channel resistance measured between the X input/output and the Y input/output. On Resistance Match (ΔRON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. On Resistance Flatness (RFLAT(ON)) The variation of on resistance over the specified range produced by the specified analog input voltage change with a constant load current. Channel Off Leakage (IOFF) The sum of leakage currents into or out of an off channel input. Channel On Leakage (ION) The current loss/gain through an on-channel resistance, creating a voltage offset across the device. Input Leakage Current (IIN) The current flowing into a digital input when a specified low level or high level voltage is applied to that input. Input Off Capacitance (COFF) The capacitance between an analog input and ground when the switch channel is off. Input/Output On Capacitance (CON) The capacitance between the inputs or outputs and ground when the switch channel is on. Digital Input Capacitance (CIN) The capacitance between a digital input and ground. Output On Switching Time (tON) The time required for the switch channel to close. The time is measured from 50% of the logic input change to the time the output reaches 10% of the final value. Output Off Switching Time (tOFF) The time required for the switch to open. This time is measured from 50% of the logic input change to the time the output reaches 90% of the switch off condition. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. Off Isolation The measure of unwanted signal coupling through an off switch. Crosstalk The measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Differential Gain The measure of how much color saturation shift occurs when the luminance level changes. Both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified and is expressed as a percentage of the largest chrominance amplitude. Differential Phase The measure of how much hue shift occurs when the luminance level changes. It can be a negative or positive value and is expressed in degrees of subcarrier phase. Charge Injection The measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Input High Voltage (VINH) The minimum input voltage for Logic 1. Input Low Voltage (VINL) The maximum input voltage for Logic 0. Output Low Voltage (VOL) The minimum input voltage for Logic 1. Input Low Voltage (VINL) The maximum output voltage for Logic 0. IDD Positive supply current. ISS Negative supply current.

Rev. A | Page 18 of 28 THEORY OF OPERATION The ADG2128 is an analog cross point switch with an array size of 8 × 12. The 12 rows are referred to as the X input/output lines, while the eight columns are referred to as the Y input/output lines. The device is fully flexible in that it connects any X line or number of X lines with any Y line when turned on. Similarly, it connects any X line with any number of Y lines when turned on. Control of the ADG2128 is carried out via an I2C interface. The device can be operated from single supplies of up to 13.2 V or from dual ±5 V supplies. The ADG2128 has many attractive features, such as the ability to reset all the switches, the ability to update many switches at the same time, and the option of reading back the status of any switch. All of these features are described in more detail here in the Theory of Operation section. RESET/POWER-ON RESET The ADG2128 offers the ability to reset all of the 96 switches to the off state. This is done through the RESET pin. When the RESET pin is low, all switches are open (off), and appropriate registers are cleared. Note that the ADG2128 also has a power- on reset block. This ensures that all switches are in the off condition on power-up of the device. In addition, all internal registers are filled with 0s and remain so until a valid write to the ADG2128 takes place. LOAD SWITCH (LDSW) LDSW is an active high command that allows a number of switches to be simultaneously updated. This is useful in applications where it is important to have synchronous transmission of signals. There are two LDSW modes: the transparent mode and the latched mode. Transparent Mode In this mode, the switch position changes after the new word is written in. LDSW is set to 1. Latched Mode In this mode, the switch positions are not updated at the same time that the input registers are written to. This is achieved by setting LDSW to 0 for each word (apart from the last word) written to the device. Then, setting LDSW to 1 for the last word allows all of the switches in that sequence to be simultaneously updated. READBACK Readback of the switch array conditions is also offered when in standard mode and fast mode. Readback enables the user to check the status of the switches of the ADG2128. This is very useful when debugging a system.

Rev. A | Page 19 of 28 SERIAL INTERFACE The ADG2128 is controlled via an I2C-compatible serial bus. The parts are connected to this bus as a slave device (no clock is generated by the switch). HIGH SPEED I2C INTERFACE In addition to standard and full speed I2C, the ADG2188 also supports the high speed (3.4 MHz) I2C interface. Only the -HS models provide this added performance. See the Ordering Guide for details. SERIAL BUS ADDRESS The ADG2128 has a 7-bit slave address. The four MSBs are hard coded to 1110, and the three LSBs are determined by the state of Pin A0, Pin A1, and Pin A2. By offering the facility to hardware configure Pin A0, Pin A1, and Pin A2, up to eight of these devices can be connected to a single serial bus. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as when a high-to-low transition on the SDA line occurs while SCL is high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. 2. The peripheral whose address corresponds to the trans- mitted address responds by pulling the SDA line low during the ninth clock pulse, known as the acknowledge bit. At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/ W bit is 1 (high), the master reads from the slave device. If the R/W bit is 0 (low), the master writes to the slave device. 3. Data is transmitted over the serial bus in sequences of nine clock pulses: eight data bits followed by an acknowl- edge bit from the receiver of the data. Transitions on the SDA line must occur during the low period of the clock signal, SCL, and remain stable during the high period of SCL, because a low-to-high transition when the clock is high can be interpreted as a stop signal. 4. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. Refer to Figure 33 and Figure 34 for a graphical explanation of the serial data transfer protocol.

clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6. Figure 33. Data-Words Table 6. Input Shift Register Bit Function Descriptions of the three address pins, Pin A0, Pin A1, and Pin A2. DB16 R/W Controls whether the ADG2128 slave device is read from or written to. If R/W = 1, the ADG2128 is being read from. If R/W = 0, the ADG2128 is being written to. DB15 Data Controls whether the switch is to be open (off ) or closed (on). If Data = 0, the switch is open/off. If Data = 1, the switch is closed/on. DB14 to DB11 AX3 to AX0 Controls I/Os X0 to X11. See Table 7 for the decode truth table. DB10 to DB8 AY2 to AY0 Controls I/Os Y0 to Y7. See Table 7 for the decode truth table. DB0 LDSW This bit is useful when a number of switches need to be simultaneously updated. If LDSW = 1, the switch position changes after the new word is read. If LDSW = 0, the input data is latched, but the switch position is not changed. As shown in Table 6, Bit DB11 to Bit DB14 control the X input/output lines, while Bit DB8 to Bit DB10 control the Y input/output lines. follow a similar pattern. Note also that the RESET pin must be high when writing to the device. Table 7. Address Decode Truth Table

Rev. A | Page 21 of 28 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0 Switch Configuration 1 1 0 1 1 0 0 0 X9 to Y0 (on) 0 1 0 1 1 0 0 0 X9 to Y0 (off ) 1 1 1 0 0 0 0 0 X10 to Y0 (on) 0 1 1 0 0 0 0 0 X10 to Y0 (off ) 1 1 1 0 1 0 0 0 X11 to Y0 (on) 0 1 1 0 1 0 0 0 X11 to Y0 (off ) X 1 1 1 0 0 0 0 Reserved X 1 1 1 1 0 0 0 Reserved 1 0 0 0 0 0 0 1 X0 to Y1 (on) 0 0 0 0 0 0 0 1 X0 to Y1 (off ) 1 1 1 0 1 0 0 1 X11 to Y1 (on) 1 0 0 0 0 0 1 0 X0 to Y2 (on) 0 0 0 0 0 0 1 0 X0 to Y2 (off ) 1 1 1 0 1 0 1 0 X11 to Y2 (on) 1 0 0 0 0 0 1 1 X0 to Y3 (on) 0 0 0 0 0 0 1 1 X0 to Y3 (off ) 1 1 1 0 1 0 1 1 X11 to Y3 (on) 1 0 0 0 0 1 0 0 X0 to Y4 (on) 0 0 0 0 0 1 0 0 X0 to Y4 (off ) 1 1 1 0 1 1 0 0 X11 to Y4 (on) 1 0 0 0 0 1 0 1 X0 to Y5 (on) 0 0 0 0 0 1 0 1 X0 to Y5 (off ) 1 1 1 0 1 1 0 1 X11 to Y5 (on) 1 0 0 0 0 1 1 0 X0 to Y6 (on) 0 0 0 0 0 1 1 0 X0 to Y6 (off ) 1 1 1 0 1 1 1 0 X11 to Y6 (on) 1 0 0 0 0 1 1 1 X0 to Y7 (on) 0 0 0 0 0 1 1 1 X0 to Y7 (off ) 1 1 1 0 1 1 1 1 X11 to Y7 (on)

Figure 35. Read Operation

Rev. A | Page 24 of 28 EVALUATION BOARD The ADG2128 evaluation board allows designers to evaluate the high performance ADG2128 8 × 12 switch array with minimum effort. The evaluation kit includes a populated, tested ADG2128 printed circuit board. The evaluation board interfaces to the USB port of a PC, or it can be used as a standalone evaluation board. Software is available with the evaluation board that allows the user to easily program the ADG2128 through the USB port. Schematics of the evaluation board are shown in Figure 36 and Figure 37. The software runs on any PC that has Microsoft® Windows® 2000 or Windows XP installed. USING THE ADG2128 EVALUATION BOARD The ADG2128 evaluation kit is a test system designed to simplify the evaluation of the ADG2128. Each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. An application note is also available with the evaluation board and gives full information on operating the evaluation board. POWER SUPPLY The ADG2128 evaluation board can be operated with both single and dual supplies. VDD and VSS are supplied externally by the user. The VL supply can be applied externally, or the USB port can be used to power the digital circuitry.

Figure 36. EVAL-ADG2128EB Schematic, USB Controller Section

Figure 37. EVAL-ADG2128EB Schematic, Chip Section

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.80 SEATING

3.50 REF

0.60 MAX

0.25 MIN

Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. A | Page 28 of 28 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05464-0-5/06(0)