ADG201A AD | Alldatasheet
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ANALOG LC’MOS > DEVICES Quad SPST Switches FEATURES FUNCTIONAL BLOCK DIAGRAMS 44V Supply Maximum Rating +15V Analog Signal Range ADG201A ADG202A Low Ron (600) ost ost Low Leakage (0.5nA) INt © [> INTO > 7 | Break Before Make Switching opt opt Extended Plastic Temperature Range ote os2 (40°C to +85°C) Ine 0 > ; nz > y | Low Power Dissipation (33mW) © D2 op2 Available in 16-Lead DIP/SOIC and os3 ose 20-Lead PLCC/LCCC Packages nso ee nso > 7 | Superior Second Source: 003 008 ADG201A Replaces DG201A, HI-201 ; 3 os os ADG202A Replaces DG202 m > ou > i | ops ‘SWITCHES SHOWN FOR A Logic “1” INPUT GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG201A and ADG202A are monolithic CMOS devices 1. Extended Signal Range: comprising four independently selectable switches. They are These switches are fabricated on an enhanced LC7MOS designed on an enhanced LC’MOS process which gives an in- process, resulting in high breakdown and an increased analog creased signal handling capability of + 15V. These switches also signal range of + 15V. feature high switching speeds and low Ron. 2, Single Supply Operation: The ADG201A and ADG202A consist of four SPST switches. For applications where the analog signal is unipolar (OV to They differ only in that the digital control logic is inverted. All 15V), the switches can be operated from a single + 15V devices exhibit break before make switching action. Inherent in supply. the design is low charge injection for minimum transients when 3, Low Leakage: switching the digital inputs. Leakage currents in the range of S00pA make these switches suitable for high precision circuits. The added feature of Break before Make allows for multiple outputs to be tied together for multiplexer applications while keeping leakage errors to a minimum. ADG201A SWITCH IN CONDITION 0 ON
1 OFF
Table. Truth Table REV. A Information furnished by Analog Devices is believed to be accurate for its use; nor for any infringements ef parents or otRer ghey of ica ONe Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A, parties which may result from its use. No license is granted by implica. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 tion or otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS,
ADG201 A/ADG202A— SPECIFICATIONS (Woo = +15V, Vs = —15V, unless otherwise specified) K Version BVersion T Version -40°Cto —40°C to -55°Cto Parameter 25°C +85°C | 25°C 85°C | 25°C —-+125°C_| Units | TestConditions ‘ANALOG SWITCH Analog Signal Range #15 415 #15 £15 +15 +15 Volts Ron 60 60 60 Qyp = 10V<Vs< +10V 90 145 0 145 90 145 Qmax | Ips=1.0mA Test Circuit 1 Ron vs. Vp (Vs) 20 20 20 op Row Drift 05 05 05 %PCtyp Row Match 5 5 3 Y%typ | Vs=0V,Ips=1mA 1,(OFF) 05 05 05 nAtyp. | Vp==14V; Vs =14V; TestCircuit2 OFF Input Leakage 2 100 2 100 1 100 nAmax Ip (OFF) 05 0s os nAtyp | Vp=+14V;Vs=14V; Test Circuit2 OFF Output Leakage 2 100 2 100 1 100 nAmax Ip(ON) 0s os os nAtyp | Vp = + 14V5TestCircuit3 ON Channel Leakage 2 200 2 200 1 200 nA max DIGITAL CONTROL Vine Input High Voltage 24 24 24 Vmin Vix» Input Low Voltage 0.8 0.8 0.8 Vmax Insc orlneet 1 1 1 pAmax DYNAMIC CHARACTERISTICS toren 30 30 30 nstyp | ton! 300 300 300 nsmax | Test Circuit4 torr! 250 250 250 nsmax | TestCircuit4 OFF Isolation 80 80 80 dBtyp | Vs=10V(p-p);f= 100kHz Ri. =750; Test Circuit 6 Channel-to-Channel Crosstalk | 80 80 80 dBtyp | Test Circuit7 Cs(OFF) 5 5 5 pF typ Cp (OFF) 5 5 5 pFtyp Cp, Cs(ON) 16 16 16 pF typ Cry: Digital Input Capacitance | 5 5 5 pF typ Quxy Charge Injection 20 20 20 pCtyp | Rs=00;C,=1000pF; Vs=0V Test Circuit POWER SUPPLY Ipp 0.6 0.6 06 mAtyp | Digital Inputs=ViytorVinw Ipp 2 2 2 mA max Iss Ol Ol 0.1 mAtyp Iss 0.2 0.2 0.2 mA max Power Dissipation 33 33 33 mW max NOTES ‘Sample tested at25°C to ensure compliance. Specifications subject to change without notice, ABSOLUTE MAXIMUM RATINGS* (Ta = +25°C unless otherwise stated) VoptoVgy ccc c cece eevee eee eevee. 44V Power Dissipation (Any Package) Upto +78... eee ee ee ee ee ee 470mW VpptoGND 2.0... cee eee ee eee es SV 5 ~ Analog Inputs! Operating Temperature Pulsed Current $ or D Lead T: Soldering 10: + 300°C Digital Inputs! Voltage atIN 6.22. eee eee ee es Ves -2V00 Nore Vpp +2Vor —'Overvoltageat IN, $ or D will be clamped by diodes. Current should be 20mA, Whichever Occurs First limited to the Maximum Rating above. *COMMENT: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. -2- REV. A
CAUTION _ ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- WARNING! A ed; however, permanent damage may occur on unconnected devices subject to high energy — electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective As foam should be discharged to the destination socket before devices are removed. ESD SENSITIVE DEVICE ORDERING GUIDE ‘Temperature Package Model? Range Option? ADG201AKN ~ 40°C to + 85°C N-16 ADG201AKR —40°C to + 85°C R-16A ADG2O1AKP_ | —40°Ct0 + 85°C | P-20A "Yo onder MIL-STD-86, Cle B proceed parts, ald/883B o T rad - * ’0 order MIL-STD-883, Class B p: parts, a to T grade part ADG201ABQ 40°C to + 85°C | QB numbers. See Analog Devices Military Products Databook (1990) for ADG201ATQ: | -55°Cto +125°C | Q-16 ullitary data sheet. ADG201ATE =55°Cto +125°C | E-20A 7E = Lendless Ceramic Chip Carrier (LCCC); N = Plastic DIP; R — 0.15" ADG2O2AKN | ~40-Cwa8sc | NA6 Saal! Outine IC (SOIC); P = Plastic Leaded Chip Carrier (PLCC); ADG202AKR_ | -40°Cto +85°C | R-16A ADG202AKP —40°C to +85°C P-20A ADG202ABQ —40°C to + 85°C Q-16 ADG202ATQ —55°Cto +125°C | Q-16 ADG202ATE —55°Cto + 125°C | E-20A PIN CONFIGURATIONS DIP, SOIC LCCC PLCC 52228 s2z228 PIRI el fs} m DJs [as] m2 SZ 20 18 a oo o 2] [as] v2 + so Gl fra] sz si 4 u 18 s2 sB] [4] s ves [I ADG201A fF) Veo ADG2018 Ves § ‘ADG201A 17 Voo ‘ADG2024 Ves [2] fapezoza [13] Voo nee ‘ADG202A we Ne ne [6] ‘Tor VIEW [yg] No AOP wiew Tor view (Not to Seale) sno [5] orto seas [2] Ne ono 7 {Wot to Seal) 1 Ne sno fis) nc «Gl [3] s= sae 483 = E] [es] $2 ba [20] v3 Sa ma [ol [fo] mo on 2 8 ||| | 32228 $2228 NC = NO CONNECT Nc = NO CONNECT Nc = No CONNECT ADG201A4/ADG202A FUNCTIONAL DIAGRAM. Yoo. +15V Voo sv a SHIFTER V TOLEVEL os SHIFTER Iwo " ano V a 1 Yoo V op Vss ow Figure 1. Typical Digital Input Cell REV. A -3-
ADG201A/ADG202A—Typical Performance Characteristics The switches are guaranteed functional with reduced single or dual supplies down to 4.5V. 1 0 3” jo lea - /* é Z aN Ee hee i . yeza™ im meer a aaa ; Py : Va Vel~ Vote Vp Va Vote Ron as a Function of Vp (Vs): Dual Supply Voltage Ron as a Function of Vp (Vs): Single Supply Voltage 1 2s : Ae hegre : 8 CLI LILA i apa | ° Ne PTT TEMPERATURE" Leakage Current as a Function of Temperature (Note: Trigger Level vs. Power Supply Voltage: Dual or Single Leakage Currents Reduce as the Supply Voltages Reduce) Supply Voltage 00 wo ; : NY a i 00 ” ee es a ee Le SUPPLY VOLTAGE - Volts surrey VOLTAGE Vote Switching Time vs. Supply Voltage (Dual Supply) Switching Time vs. Supply Voltage (Single Supply) ~4- REV. A
Test Circuits—ADG201A/ADG202A bos CD © = ® TT i = av suv = a “E y v Ron=VMlos Test Circuit 1 Test Circuit 2 Test Circuit 3 +18v wv ADG201A s D ' ! Nv IN ! mf 50% 60% Aa {>° 4 330 sae ‘Apazoza — \\ V i @) | ono Ves H 90% 1 {90% vo if 1 of Vo OV oassv V Ty ton be mel tone Test Circuit 4 +15V [tetneieien Voo ' Rs! 8 Ap711 wv ' 1 1 ©, OVo “ \\ / ives ! . Vm @t) |_GND Vos ow Vo QINJ=C, x AVo V V ~15V Test Circuit 5. Charge Injection Voo si v vwott>o v V pocsm-n--4s gp, ob----- =p, “u@ '[pa-peeee T sap sa o Be 5 ottove f Vw © So J Re a Vo gf aaa? tg Seon ? ee v TFL Se RL y, Vow a ADG201A Viy=5V OFFISOLATION = V Vo =v ADG20ZA Vin=0V 20xLOGIVSVol ADGIOIA Y= Ov CCHANNEL-TO.CHANNEL CROSSTALK = ‘abazaea Va BV Soetogveve) Test Circuit 6. Off Isolation Test Circuit 7. Channel-to-Channel Crosstalk REV.A -5-
TERMINOLOGY ton Delay time between the 50% and 90% points of a . the digital input and switch “ON” condition Ron Ohmic resistance between terminals OUT andS Delay time between the 50% and 90% points of Row Match Difference between the Row of any two channels the digital input and switch “OFF” condition Is (OFF) Source terminal leakage current when the switch “OFF” time measured between 50% points of Ip (OFF) Drain terminal leakage current when the switch both switches, which are connected as a multi- is off pl exer when switching from one address state to 4 . another Tp (ON) Leakage curent that flows from the closed switch y,. Maximum Input Voltage for a Logic Low Vp (Vs) ‘Analog voltage on terminal D, § Vinn Minimum Input Voltage for a Logic High Ce (OFF) Switch input capacitance “OFF” condition Tnx Gna) Input current of the digital input Cp (OFF) Switch output capacitance “OFF” condition yr Most positive voltage supply Cin Digital input capacitance ke Positi ia fh Be SUPPIY Cp; Cs (ON) Input or output capacitance when the switch pp ositive supply current is on Iss Negative supply current MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic (N-16) 16-Pin Cerdip (Q-16) ors com oamom EE ‘7a8 00.95) ‘oaeeen 0788 (193941 Sue : ms omaae cwsond uml x8 373 SP elem eT TTL Soe sas Sowa Laps ane SOLDER OR THERA KOVAR OR ALLOY 42 (R-16A) PAP AA AAD Semen l | ozaee san i, esse asm a VUUUToTE | 2871020 vam be a Fos 1.75 ‘—" ome 025) TET osm 92s soo Sass satan 20-Terminal Leadless Ceramic Chip Carrier 20-Terminal Plastic Leaded Chip Carrier (E-20A) (P-20A) bin, ame |g = Sean waked | (a ==) q q p c> 7 = d — Te Sees ~6- REV. A