ADG1402BRMZ

ADG1401 AD | Alldatasheet

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1 Ω On Resistance, ±15 V/+12 V/±5 V iCMOS SPST Switches ADG1401/ADG1402 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

FEATURES

1 Ω on resistance 0.2 Ω on resistance flatness Up to 430 mA continuous current Fully specified at +12 V, ±15 V, ±5 V No V L supply required

3 V logic-compatible inputs

8-lead MSOP and 8-lead, 3 mm × 2 mm LFCSP packages

APPLICATIONS

D IN S ADG1401 SWITCHES SHOWN FOR A LOGIC 1 INPUT 08486-001 Figure 1. ADG1401 Functional Block Diagram Figure 2. ADG1402 Functional Block Diagram the off condition, signal levels up to the supplies are blocked. power consumption, and a reduced package size. portable and battery-powered instruments.

1. 1.3 Ω maximum on resistance at 25°C.
2. 3 V logic-compatible digital inputs: VINH = 2.0 V , VINL = 0.8 V .
3. No VL logic power supply required.
4. 8-lead MSOP and 8-lead, 3 mm × 2 mm LFCSP packages.

Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 3 of 16 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 1 Ω typ VS = ±10 V, IS = −10 mA; see Figure 20 On Resistance Flatness, RFLAT (ON) 0.2 Ω typ VS = ±10 V; IS = −10 mA 0.23 0.26 0.3 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage, IS (Off ) ±0.05 nA typ VS = ±10 V, VD = ±10 V; see Figure 21 ±0.4 ±3 ±150 nA max Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = ±10 V, VD = ±10 V; see Figure 21 ±0.4 ±3 ±150 nA max Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±10 V; see Figure 22 ±1 ±3 ±150 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 tON 120 ns typ RL = 300 Ω, CL = 35 pF 150 185 215 ns max VS = 10 V; see Figure 23 tOFF 120 ns typ RL = 300 Ω, CL = 35 pF 150 175 200 ns max VS = 10 V; see Figure 23 Charge Injection −12 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 24 Off Isolation −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 Total Harmonic Distortion + Noise 0.008 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz; see Figure 27 −3 dB Bandwidth 120 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 Insertion Loss 0.08 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz; see Figure 26 CS (Off ) 36 pF typ f = 1 MHz, VS = 0 V CD (Off ) 41 pF typ f = 1 MHz, VS = 0 V CD, CS (On) 187 pF typ f = 1 MHz, VS = 0 V POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 60 μA typ Digital inputs = 5 V 95 μA max ISS 0.002 μA typ Digital inputs = 0 V, 5 V, or VDD 1.0 μA max VDD/VSS ±4.5/±16.5 V min/max Ground = 0 V 1 Guaranteed by design, not subject to production test.

Rev. 0 | Page 4 of 16 +12 V SINGLE SUPPLY VDD = +12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 2 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 20 2.4 2.9 3.2 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Flatness, RFLAT (ON) 0.6 Ω typ VS = 0 V to 10 V, IS = −10 mA 0.68 0.8 0.85 Ω max LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off ) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21 ±0.4 ±3 ±150 nA max Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21 ±0.4 ±3 ±150 nA max Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 22 ±1 ±3 ±150 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 tON 180 ns typ RL = 300 Ω, CL = 35 pF 235 295 335 ns max VS = 8 V; see Figure 23 tOFF 140 ns typ RL = 300 Ω, CL = 35 pF 185 215 260 ns max VS = 8 V; see Figure 23 Charge Injection 57 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 24 Off Isolation −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 −3 dB Bandwidth 82 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 Insertion Loss 0.15 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz; see Figure 26 CS (Off ) 61 pF typ f = 1 MHz, VS = 6 V CD (Off ) 68 pF typ f = 1 MHz, VS = 6 V CD, CS (On) 181 pF typ f = 1 MHz, VS = 6 V POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 60 μA typ Digital inputs = 5 V 95 μA max VDD 5/16.5 V min/max Ground = 0 V, VSS = 0 V 1 Guaranteed by design, not subject to production test.

Rev. 0 | Page 5 of 16 ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V , unless otherwise noted. Table 3. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 2.3 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 20 On Resistance Flatness, RFLAT (ON) 0.65 Ω typ VS = ±4.5 V, IS = −10 mA 0.72 0.85 0.9 Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS (Off ) ±0.02 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 21 ±0.4 ±3 ±150 nA max Drain Off Leakage, ID (Off ) ±0.02 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 21 ±0.4 ±3 ±150 nA max Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±4.5 V; see Figure 22 ±1 ±3 ±150 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 tON 290 ns typ RL = 300 Ω, CL = 35 pF 375 460 520 ns max VS = 3 V; see Figure 23 tOFF 235 ns typ RL = 300 Ω, CL = 35 pF 305 365 405 ns max VS = 3 V; see Figure 23 Charge Injection 145 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 24 Off Isolation −58 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 Total Harmonic Distortion + Noise 0.02 % typ RL = 10 kΩ, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 27 −3 dB Bandwidth 79 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 Insertion Loss 0.14 dB typ RL = 50 Ω, CL = 5 pF , f = 1 MHz; see Figure 26 CS (Off ) 52 pF typ VS = 0 V, f = 1 MHz CD (Off ) 58 pF typ VS = 0 V, f = 1 MHz CD, CS (On) 198 pF typ VS = 0 V, f = 1 MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V IDD 0.001 μA typ Digital inputs = 0 V or VDD 1.0 μA max ISS 0.001 μA typ Digital inputs = 0 V or VDD 1.0 μA max VDD/VSS ±4.5/±16.5 V min/max Ground = 0 V 1 Guaranteed by design, not subject to production test.

Rev. 0 | Page 6 of 16 CONTINUOUS CURRENT PER CHANNEL, S OR D Table 4. Parameter 25°C 85°C 125°C Unit Test Conditions/Comments CONTINUOUS CURRENT, S or D1 ±15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V 8-Lead MSOP (θJA = 206°C/W) 275 190 125 mA maximum 8-Lead LFCSP (θJA = 50.8°C/W) 430 275 160 mA maximum +12 V Single Supply VDD = 10.8 V, VSS = 0 V 8-Lead MSOP (θJA = 206°C/W) 255 180 120 mA maximum 8-Lead LFCSP (θJA = 50.8°C/W) 355 235 145 mA maximum ±5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V 8-Lead MSOP (θJA = 206°C/W) 250 175 120 mA maximum 8-Lead LFCSP (θJA = 50.8°C/W) 340 225 140 mA maximum 1 Guaranteed by design, not subject to production test.

TA = 25°C, unless otherwise noted. be limited to the maximum ratings given. Table 6. Thermal Resistance

1. EXPOSED PAD TIED TO SUBSTRATE, VSS.

4 VDD

Figure 3. ADG1401/ADG1402 Pin Configuration Table 7. ADG1401/ADG1402 Pin Function Descriptions 1 S Source Terminal. This pin can be an input or output. 3 GND Ground (0 V) Reference. 4 V DD Most Positive Power Supply Potential. 7 V SS Most Negative Power Supply Potential. 8 D Drain Terminal. This pin can be an input or output. EPAD Exposed pad tied to substrate, VSS, for LFCSP package. Table 8. ADG1401/ADG1402 Truth Table

Rev. 0 | Page 14 of 16 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. V D (VS) The analog voltage on Terminal D and Terminal S. R ON The ohmic resistance between Terminal D and Terminal S. R FLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. I S (Off) The source leakage current with the switch off. I D (Off) The drain leakage current with the switch off. I D, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. V INH The minimum input voltage for Logic 1. I INL (IINH) The input current of the digital input. C S (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. t ON Delay time between the 50% and 90% points of the digital input and switch on condition. See Figure 23. tOFF Delay time between the 50% and 90% points of the digital input and switch off condition. See Figure 23. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 24. Off Isolation A measure of unwanted signal coupling through an off switch. See Figure 25. Bandwidth The frequency at which the output is attenuated by 3 dB. See Figure 26. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. See Figure 26. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 27. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR. See Figure 19.

0.65 BSC

1.10 MAX

Figure 28. 8-Lead Mini Small Outline Package [MSOP]

0.20 MIN

0.05 MAX

0.02 NOM

0.15 REF

3.00 BSC

2.00 BSC

Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

Rev. 0 | Page 16 of 16 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D08486-0-10/09(0)