ADG1308

ADG1308/ADG1309 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

±15 V/+12 V Multiplexers ADG1308/ADG1309 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.

FEATURES

33 V supply range

130 Ω on resistance Fully specified at ±15 V/+12 V

3 V logic-compatible inputs

Break-before-make switching action 16-lead TSSOP and 16-lead SOIC_N Upgrade for the ADG508A/ADG509A

APPLICATIONS

D ADG1309 S1A S4B DA DB S4A S1B 1-OF-4 DECODER 1-OF-8 DECODER A0 A1 ENA0 A1 A2 EN 06009-001 Figure 1. GENERAL DESCRIPTION The ADG1308 and ADG1309 are monolithic analog multi- plexers consisting of eight single channels and four differential channels, respectively. The ADG1308 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1, and A2. The ADG1309 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When the switches are on, each switch conducts equally well in both directions and has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is the low charge injection for minimum transients when switching the digital inputs. Fast switching speed coupled with high signal bandwidth makes the parts suitable for video signal switching. CMOS construction ensures ultra low power dissipation, making the parts ideally suited for portable and battery-powered instruments. PRODUCT HIGHLIGHTS 1. 16-lead TSSOP and 16-lead SOIC_N available. 2. Pin compatible with the ADG508AKR and the ADG509AKR devices. 3. 3 V , logic-compatible digital input where: V IH = 2.0 V and VIL = 0.8 V . 4. VL logic power supply not required. 5. Low power consumption.

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

1/09—Rev. 0 to Rev. A 4/06—Revision 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V , unless otherwise noted.1 Table 1. Parameter +25ºC −40ºC to +105ºC Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to VDD V On Resistance, RON 130 Ω typ VS = ±10 V, IS = −1 mA; see Figure 13 210 300 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between Channels, ∆RON 5 Ω typ VS = ±10 V, IS = −1 mA 10 Ω max On Resistance Flatness, RFLAT (On) 25 Ω typ VS = −5 V, 0 V, +5 V, IS = −1 mA 70 Ω max LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±1 nA typ VD = ±10 V, VS = −10 V; see Figure 14 ±50 nA max Drain Off Leakage, ID (Off ) ±1 nA typ VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 14 ±50 nA max Channel On Leakage, ID, IS (On) ±1 nA typ VS = VD = ±10 V; see Figure 15 ±50 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±0.005 μA max VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION 80 ns typ RL = 300 Ω, CL = 35 pF 130 190 ns max VS = 10 V; see Figure 16 tON (EN) 80 ns typ RL = 300 Ω, CL = 35 pF 100 120 ns max VS = 10 V; see Figure 18 tOFF (EN) 85 ns typ RL = 300 Ω, CL = 35 pF 100 150 ns max VS = 10 V; see Figure 18 Break-Before-Make Time Delay, tBBM 25 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 10 V; see Figure 17 Charge Injection 2 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20 Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21 −3 dB Bandwidth 500 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS (Off ) 5 pF typ f = 1 MHz, VS = 0 V CD (Off) ADG1308 15 pF typ f = 1 MHz, VS = 0 V ADG1309 10 pF typ f = 1 MHz, VS = 0 V CD, CS (On) ADG1308 20 pF typ f = 1 MHz, VS = 0 V ADG1309 15 pF typ f = 1 MHz, VS = 0 V

Rev. A | Page 4 of 16 Parameter +25ºC −40ºC to +105ºC Unit Test Conditions/Comments POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 220 μA typ Digital inputs = 5 V 380 μA max ISS 0.002 μA typ Digital inputs = 0 V or VDD or 5 V 1.0 μA max VDD/VSS ±5/±16.5 V min/V max |VDD| = |VSS| 1 Temperature range for B version is –40°C to +105°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 5 of 16 SINGLE SUPPLY VDD = 12 V , V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted.1 Table 2. Parameter +25ºC −40ºC to +105ºC Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 325 Ω typ VS = 0 V to 10 V, IS = −1 mA; see Figure 13 500 660 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels, ∆RON 10 Ω typ VS = 0 V to 10 V, IS = −1 mA 20 Ω max On Resistance Flatness, RFLAT (On) 65 Ω typ VS = 3 V, 6 V, 9 V, IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V Source Off Leakage, IS (Off ) ±1 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 14 ±50 nA max Drain Off Leakage, ID (Off ) ±1 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 14 ±50 nA max Channel On Leakage, ID, IS (On) ±1 nA typ VS = VD = 1 V or 10 V; see Figure 15 ±50 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±0.001 ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION 100 ns typ RL = 300 Ω, CL = 35 pF 170 240 VS = 8 V; see Figure 16 tON (EN) 90 ns typ RL = 300 Ω, CL = 35 pF 110 170 VS = 8 V; see Figure 18 tOFF (EN) 105 ns typ RL = 300 Ω, CL = 35 pF 130 180 VS = 8 V; see Figure 18 Break-Before-Make Time Delay, tBBM 45 ns typ RL = 300 Ω, CL = 35 pF 20 ns min VS1 = VS2 = 8 V; see Figure 17 Charge Injection 2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20 Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21 −3 dB Bandwidth 500 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS (Off ) 5 pF typ f = 1 MHz, VS = 6 V CD (Off) ADG1308 10 pF typ f = 1 MHz, VS = 6 V ADG1309 15 pF typ f = 1 MHz, VS = 6 V CD, CS (On) ADG1308 20 pF typ f = 1 MHz, VS = 6 V ADG1309 15 pF typ f = 1 MHz, VS = 6 V POWER REQUIREMENTS VDD = 13.2 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 220 μA typ Digital inputs = 5 380 μA max VDD 5/16.5 V min/V max VSS = 0 V, GND = 0 V 1 Temperature range for the B version is –40°C to +105°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog, Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) Continuous Current, S or D pins 30 mA Peak Current, S or D pins (Pulsed at 1 ms, 10% Duty Cycle Maximum) 100 mA Operating Temperature Range Industrial (B Version) –40°C to +105°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C TSSOP , θJA, Thermal Impedance 112°C/W 16-Lead SOIC, θJA, Thermal Impedance 77°C/W Reflow Soldering Peak Temperature (Pb-free) 260 (+0/−5)°C 1 Overvoltages at A, EN, S, or D pins are clamped by internal diodes. Current should be limited to the maximum ratings provided. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. ADG1308 Pin Configuration (TSSOP and SOIC_N) Table 4. ADG1308 Pin Function Descriptions 1 A0 Logic Control Input A0. 2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 4 S1 Source Terminal 1. Can be an input or an output. 5 S2 Source Terminal 2. Can be an input or an output. 6 S3 Source Terminal 3. Can be an input or an output. 7 S4 Source Terminal 4. Can be an input or an output. 8 D Drain Terminal. Can be an input or an output. 9 S8 Source Terminal 8. Can be an input or an output. 10 S7 Source Terminal 7. Can be an input or an output. 11 S6 Source Terminal 6. Can be an input or an output. 12 S5 Source Terminal 5. Can be an input or an output. 13 V DD Most Positive Power Supply Potential. 14 GND Ground (0 V) Reference. 15 A2 Logic Control Input A2. 16 A1 Logic Control Input A1.

Figure 3. ADG1309 Pin Configuration (TSSOP and SOIC_N) Table 6. ADG1309 Pin Function Descriptions 1 A0 Logic Control Input A0. 2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 4 S1A Source Terminal 1A. Can be an input or an output. 5 S2A Source Terminal 2A. Can be an input or an output. 6 S3A Source Terminal 3A. Can be an input or an output. 7 S4A Source Terminal 4A. Can be an input or an output. 8 DA Drain Terminal A. Can be an input or an output. 9 DB Drain Terminal B. Can be an input or an output. 10 S4B Source Terminal 4B. Can be an input or an output. 11 S3B Source Terminal 3B. Can be an input or an output. 12 S2B Source Terminal 2B. Can be an input or an output. 13 S1B Source Terminal 1B. Can be an input or an output. 14 V DD Most Positive Power Supply Potential. 15 GND Ground (0 V) Reference. 16 A1 Logic Control Input A1.

Rev. A | Page 13 of 16 TERMINOLOGY RON Ohmic resistance between D and S. ΔRON Difference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. I D (Off) Drain leakage current when the switch is off. I D, IS (On) Channel leakage current when the switch is on. V D (VS) Analog voltage on Terminal D and Terminal S. C S (Off) Channel input capacitance for off condition. CD (Off) Channel output capacitance for off condition. CD, CS (On) On switch capacitance. C IN Digital input capacitance. t ON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. T BBM Off time measured between the 80% point of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. V INH Minimum input voltage for Logic 1. I INL (IINH) Input current of the digital input. I DD Positive supply current. I SS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch.

Rev. A | Page 15 of 16 NOTES

Rev. A | Page 16 of 16 NOTES ©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06009-0-1/09(A)