ADG1236

ADG1236 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch Data Sheet ADG1236 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

1.3 pF off capacitance 3.5 pF on capacitance 1 pC charge injection

33 V supply range

120 Ω on resistance Fully specified at +12 V, ±15 V No VL supply required

3 V logic-compatible inputs

16-lead TSSOP and 12-lead LFCSP packages Typical power consumption: <0.03 µW

APPLICATIONS

Audio/video signal routing Communication systems FUNCTIONAL BLOCK DIAGRAM ADG1236 S2B S2A IN2 IN1 S1B S1A SWITCHES SHOWN FOR A LOGIC 1 INPUT 04776-001 Figure 1. GENERAL DESCRIPTION The ADG1236 is a monolithic CMOS device containing two independently selectable SPDT switches. It is designed on an iCMOS® process. iCMOS (industrial CMOS) is a modular manufacturing process combining high voltage complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of the device make it an ideal solution for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth makes the device suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the device ideally suited for portable and battery-powered instruments. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. PRODUCT HIGHLIGHTS 1. 1.3 pF off capacitance (±15 V supply). 2. 1 pC charge injection. 3. 3 V logic-compatible digital inputs: VIH = 2.0 V , VIL = 0.8 V . 4. No VL logic power supply required. 5. Ultralow power dissipation: <0.03 µW. 6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP packages.

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

3/16—Rev. 0 to Rev. A 9/05—Revision 0: Initial Version

Rev. A | Page 4 of 16 Y Version1 Parameters 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments1 POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 170 µA typ Digital inputs = 5 V 230 µA max ISS 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max ISS 0.001 µA typ Digital inputs = 5 V 1.0 µA max 1 Temperature range for Y version is −40°C to +125°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 5 of 16 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, G N D = 0 V , unless otherwise noted. Table 2. Y Version1 Parameters 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA; Figure 20 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels (∆RON) 4.5 Ω typ VS = 0 V to 10 V, IS = −1 mA 16 26 27 Ω max On Resistance Flatness (RFLAT(ON)) 60 Ω typ VS = 3 V, 6 V, 9 V, IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V Source Off Leakage, IS (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 21 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 21 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V, Figure 22 ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.001 µA typ VIN = VINL or VINH ±0.1 µA max Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS BOFF AON 105 ns typ RL = 300 Ω, CL = 35 pF 140 175 ns max VS = 8 V; Figure 23 Transition Time, tTRANS AOFF BON 155 ns typ RL = 300 Ω, CL = 35 pF 190 255 ns max VS = 8 V; Figure 23 Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 8 V; Figure 24 Charge Injection −0.8 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 25 Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26; Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27 −3 dB Bandwidth 800 MHz typ RL = 50 Ω, CL = 5 pF; Figure 28 CS (Off ) 1.6 pF typ f = 1 MHz; VS = 6 V 1.9 pF max f = 1 MHz; VS = 6 V CD, CS (On) 4 pF typ f = 1 MHz; VS = 6 V 4.9 pF max f = 1 MHz; VS = 6 V POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 170 µA typ Digital inputs = 5 V 230 µA max 1 Temperature range for Y version is −40°C to +125°C. 2 Guaranteed by design; not subject to production test.

Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Digital Inputs1 GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Peak Current, S or D 100 mA (pulsed at 1 ms, 10% duty cycle max) Continuous Current per Channel, S or D 25 mA Operating Temperature Range Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP , θJA Thermal Impedance 112°C/W 12-Lead LFCSP , θJA Thermal Impedance 80°C/W Reflow Soldering Peak Temperature, Pb Free 260°C 1 Over voltages at IN, S, or D are clamped by internal diodes. Current must be limited to the maximum ratings given. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION TRUTH TABLE FOR SWITCHES Table 4. IN Switch A Switch B

0 Off On

1 On Off

Rev. A | Page 8 of 16 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tTRANS The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED. Figure 31. 12-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. A | Page 15 of 16 NOTES

Rev. A | Page 16 of 16 NOTES ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04776-0-3/16(A)