ADG1223BRMZ1

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS® Dual SPST Switches ADG1221/ADG1222/ADG1223 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.

FEATURES

<0.5 pC charge injection over full signal range Off capacitance: 2 pF Off leakage: 20 pA Supply range: 33 V On resistance: 120 Ω Fully specified at ±15 V, +12 V No V L supply required

3 V logic-compatible inputs

APPLICATIONS

SWITCHES SHOWN FOR A LOGIC 0 INPUT 06574-001 Figure 1. GENERAL DESCRIPTION The ADG1221/ADG1222/ADG1223 are monolithic, complemen- tary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an iCMOS (industrial CMOS) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs, capable of 33 V operation, in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and exceptionally low charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the full signal range of the device. The ADG1221/ADG1222/ADG1223 contain two independent single-pole/single-throw (SPST) switches. The ADG1221 and ADG1222 differ only in that the digital control logic is inverted. The ADG1221 switches are turned on with Logic 1 on the appro- priate control input, and Logic 0 is required for the ADG1222. The ADG1223 has one switch with digital control logic similar to that of the ADG1221; the logic is inverted on the other switch. The ADG1223 exhibits break-before-make switching action for use in multiplexer applications. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. 0.5 –0.5 –15 15 06574-041 INPUT VOLTAGE (V) CHARGE INJECTION (pC) 0.4 0.3 0.2 0.1 –0.1 –0.2 –0.3 –0.4 –10 –5 0 5 10 TA = 25ºC VDD = +15V VSS = –15V VDD = +5V VSS = –5V VDD = 12V VSS = 0V Figure 2. Charge Injection vs. Input Voltage

Rev. A | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

3/09—Rev. 0 to Rev. A Changes to Power Requirements, IDD, Digital Inputs = 5 V Changes to t ON Parameter and Power Requirements, IDD, Digital 2/07—Rev. 0: Initial Version

Rev. A | Page 3 of 16 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Temperature Parameter 25°C –40°C to +85°C –40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON VDD = +13.5 V, VSS = –13.5 V, VS = ±10 V, IS = –1 mA (see Figure 23) 120 Ω typ 200 240 270 Ω max On Resistance Match Between Channels, ∆RON V S = ±10 V, IS = –1 mA 2.5 Ω typ 6 10 12 Ω max On Resistance Flatness, RFLAT(ON) V S = –5 V/0 V/+5 V; IS = –1 mA 20 Ω typ 64 76 83 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = –16.5 V Source Off Leakage, IS (Off) VS = ±10 V, VD = ±10 V (see Figure 24) ±0.002 nA typ ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off) VS = ±10 V, VD = ±10 V (see Figure 24) ±0.002 nA typ ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (On) VS = VD = ±10 V (see Figure 25) ±0.01 nA typ ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH V IN = VINL or VINH 0.005 μA typ ±0.1 μA max Digital Input Capacitance, CIN 2.5 pF typ DYNAMIC CHARACTERISTICS1 tON RL = 300 Ω, CL = 35 pF, VS = 10 V (see Figure 26) 130 ns typ 170 210 240 ns max tOFF RL = 300 Ω, CL = 35 pF, VS = 10 V (see Figure 26) 85 ns typ 105 130 140 ns max Break-Before-Make Time Delay (ADG1223 Only), tBBM RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 10 V (see Figure 27) 40 ns typ 10 ns min Charge Injection, QINJ 0.1 pC typ V S = 0 V, RS = 0 Ω, CL = 1 nF (see Figure 28) Off Isolation 75 dB typ RL = 50 Ω, CL = 1 pF, f = 1 MHz (see Figure 29)

Rev. A | Page 4 of 16 Temperature Parameter 25°C –40°C to +85°C –40°C to +125°C Unit Test Conditions/Comments Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 1 pF, f = 1 MHz (see Figure 30) Total Harmonic Distortion + Noise, THD + N 0.15 % typ R L = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz –3 dB Bandwidth 960 MHz typ R L = 50 Ω, CL = 1 pF (see Figure 31) CS (Off) VS = 0 V, f = 1 MHz 1.7 pF typ 2.2 pF max CD (Off) VS = 0 V, f = 1 MHz 1.7 pF typ 2.2 pF max CD, CS (On) VS = 0 V, f = 1 MHz 3 pF typ 4 pF max POWER REQUIREMENTS VDD = +16.5 V, VSS = –16.5 V IDD 0.001 μA typ Digital inputs = 0 V or V DD 1.0 μA max Digital inputs = 0 V or V DD 140 μA typ Digital inputs = 5 V 190 μA max Digital inputs = 5 V ISS Digital inputs = 0 V, 5 V, or VDD 0.001 μA typ 1.0 μA max VDD/VSS ±5/±16.5 V min/max GND = 0 V 1 Guaranteed by design, not subject to production test. SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Temperature Parameter 25°C –40°C to +85°C –40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON VDD = 10.8 V, VSS = 0 V, VS = 0 V to 10 V, IS = –1 mA (see Figure 23) 300 Ω typ 475 567 625 Ω max On Resistance Match Between Channels, ∆RON V S = 0 V to 10 V, IS = –1 mA 4.5 Ω typ 16 26 27 Ω max On Resistance Flatness, RFLAT(ON) 60 Ω typ V S = 3 V/6 V/9 V, IS = –1 mA LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off) VS = 1 V/10 V, VD = 10 V/1 V (see Figure 24) ±0.002 nA typ ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off) VS = 1 V/10 V, VD = 10 V/1 V (see Figure 24) ±0.002 nA typ ±0.1 ±0.6 ±1 nA max

Rev. A | Page 5 of 16 Temperature Parameter 25°C –40°C to +85°C –40°C to +125°C Unit Test Conditions/Comments Channel On Leakage, ID, IS (On) VS = VD = 1 V or 10 V (see Figure 25) ±0.01 nA typ ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH V IN = VINL or VINH 0.001 μA typ ±0.1 μA max Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS1 tON RL = 300 Ω, CL = 35 pF, VS = 8 V (see Figure 26) 190 ns typ 250 300 345 ns max tOFF RL = 300 Ω, CL = 35 pF, VS = 8 V (see Figure 26) 120 ns typ 150 190 225 ns max Break-Before-Make Time Delay (ADG1223 Only), tBBM RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 8 V (see Figure 27) 70 ns typ 10 ns min Charge Injection, QINJ 0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF (see Figure 28) Off Isolation 75 dB typ RL = 50 Ω, CL =1 pF, f = 1 MHz (see Figure 29) Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 1 pF, f = 1 MHz (see Figure 30) −3 dB Bandwidth 550 MHz typ R L = 50 Ω, CL = 1 pF (see Figure 31) CS (Off) VS = 6 V, f = 1 MHz 2.1 pF typ 2.6 pF max CD (Off) VS = 6 V, f = 1 MHz 2.1 pF typ 2.6 pF max CD, CS (On) VS = 6 V, f = 1 MHz 3.8 pF typ 4.6 pF max POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 μA typ Digital inputs = 0 V or V DD 1.0 μA max Digital inputs = 0 V or V DD 140 μA typ Digital inputs = 5 V 190 μA max Digital inputs = 5 V VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V 1 Guaranteed by design, not subject to production test.

TA = 25°C, unless otherwise noted. limited to the maximum ratings given. soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance

Figure 3. 10-Lead MSOP Pin Configuration Table 5. Pin Function Descriptions 2 S1 Source Terminal. Can be an input or output. 3 D1 Drain Terminal. Can be an input or output. 4 D2 Drain Terminal. Can be an input or output. 5 S2 Source Terminal. Can be an input or output. 6 V SS Most Negative Power Supply Potential. 8 GND Ground (0 V) Reference. 9 V DD Most Positive Power Supply Potential. Table 6. ADG1221/ADG1222 Truth Table Table 7. ADG1223 Truth Table

0 Off On

1 On Off

Rev. A | Page 8 of 16 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. V D (VS) The analog voltage on Terminal D and Terminal S. R ON The ohmic resistance between Terminal D and Terminal S. R FLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. V INL The maximum input voltage for Logic 0. V INH The minimum input voltage for Logic 1. I INL (IINH) The input current of the digital input. C S (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. C IN The digital input capacitance. tON The delay between applying the digital control input and the output switching on (see Figure 26). tOFF The delay between applying the digital control input and the output switching off (see Figure 26). tBBM Off time or on time measured between the 90% points of both switches, when switching from one address state to another (ADG1223 only). QINJ (Charge Injection) A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. –3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N (Total Harmonic Noise Plus Distortion) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.

1.10 MAX

0.50 BSC

Figure 33. 10-Lead Mini Small Outline Package [MSOP]

Rev. A | Page 16 of 16 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06574-0-3/09(A)