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Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS Quad SPST Switches Data Sheet ADG1211/ADG1212/ADG1213 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.

FEATURES

2.6 pF on capacitance <1 pC charge injection

33 V supply range

120 Ω on resistance Fully specified at ±15 V, +12 V No VL supply required

3 V logic-compatible inputs

16-lead TSSOP and 16-lead LFCSP Typical power consumption: <0.03 µW

APPLICATIONS

The ADG1211/ADG1212/ADG1213 are monolithic complemen- tary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an iCMOS® (industrial CMOS) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. FUNCTIONAL BLOCK DIAGRAM IN1 IN2 IN3 IN4 ADG1211 SWITCHES SHOWN FOR A LOGIC 1 INPUT IN1 IN2 IN3 IN4 ADG1212 IN1 IN2 IN3 IN4 ADG1213 04778-001 Figure 1. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. The ADG1211/ADG1212/ADG1213 contain four independent single-pole/single-throw (SPST) switches. The ADG1211 and ADG1212 differ only in that the digital control logic is inverted. The ADG1211 switches are turned on with Logic 0 on the appropriate control input, while Logic 1 is required for the ADG1212. The ADG1213 has two switches with digital control logic similar to that of the ADG1211; the logic is inverted on the other two switches. The ADG1213 exhibits break-before- make switching action for use in multiplexer applications. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. PRODUCT HIGHLIGHTS 1. Ultralow capacitance. 2. <1 pC charge injection. 3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V . 4. No VL logic power supply required. 5. Ultralow power dissipation: <0.03 µW . 6. 16-lead TSSOP and 3 mm × 3 mm LFCSP packages.

ADG1211/ADG1212/ADG1213 Data Sheet Rev. B | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

8/12—Rev. A to Rev. B 2/09—Rev. 0 to Rev. A Changes to Power Requirements, IDD, Digital Inputs = 5 V Changes to Power Requirements, IDD, Digital Inputs = 5 V 7/05—Revision 0: Initial Versi on

Data Sheet ADG1211/ADG1212/ADG1213 Rev. B | Page 3 of 16 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) 120 Ω typ VS = ±10 V, IS = −1 mA; see Figure 20 190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between Channels (∆RON) 2.5 Ω typ VS = ±10 V, IS = −1 mA 6 10 11 Ω max On Resistance Flatness (RFLAT(ON)) 20 Ω typ VS = −5 V/0 V/+5 V; IS = −1 mA 57 72 79 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage, IS (Off) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max Digital Input Capacitance, CIN 2.5 pF typ DYNAMIC CHARACTERISTICS2 tON 110 ns typ RL = 300 Ω, CL = 35 pF 130 160 195 ns max VS = 10 V; see Figure 23 tOFF 85 ns typ RL = 300 Ω, CL = 35 pF 115 130 150 ns max VS = 10 V; see Figure 23 Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF (ADG1213 Only) 10 ns min VS1 = VS2 = 10 V; see Figure 24 Charge Injection −0.3 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 25 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz −3 dB Bandwidth 1000 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28 CS (Off) 0.9 pF typ VS = 0 V, f = 1 MHz 1.1 pF max VS = 0 V, f = 1 MHz CD (Off) 1 pF typ VS = 0 V, f = 1 MHz 1.2 pF max VS = 0 V, f = 1 MHz CD, CS (On) 2.6 pF typ VS = 0 V, f = 1 MHz 3 pF max VS = 0 V, f = 1 MHz

ADG1211/ADG1212/ADG1213 Data Sheet Rev. B | Page 4 of 16 Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 220 µA typ Digital inputs = 5 V 380 µA max ISS 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max ISS 0.001 µA typ Digital inputs = 5 V 1.0 µA max VDD/VSS ±4.5/±16.5 V min/max 1 Temperature range for Y version is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Data Sheet ADG1211/ADG1212/ADG1213 Rev. B | Page 5 of 16 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA; see Figure 20 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels (∆RON) 4.5 Ω typ VS = 0 V to 10 V, IS = −1 mA 12 26 27 Ω max On Resistance Flatness (RFLAT(ON)) 60 Ω typ VS = 3 V/6 V/9 V, IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.001 µA typ VIN = VINL or VINH ±0.1 µA max Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS2 tON 130 ns typ RL = 300 Ω, CL = 35 pF 170 210 240 ns max VS = 8 V; see Figure 23 tOFF 95 ns typ RL = 300 Ω, CL = 35 pF 120 145 180 ns max VS = 8 V; see Figure 23 Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF (ADG1213 Only) 10 ns min VS1 = VS2 = 8 V; see Figure 24 Charge Injection 0 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 25 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 −3 dB Bandwidth 900 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28 CS (Off) 1.2 pF typ VS = 6 V, f = 1 MHz 1.4 pF max VS = 6 V, f = 1 MHz CD (Off) 1.3 pF typ VS = 6 V, f = 1 MHz 1.5 pF max VS = 6 V, f = 1 MHz CD, CS (On) 3.2 pF typ VS = 6 V, f = 1 MHz 3.9 pF max VS = 6 V, f = 1 MHz POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 220 µA typ Digital inputs = 5 V 1.0 µA max VDD 5/165 V min/max VSS = 0 V, GND = 0 V 1 Temperature range for Y version is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

TA = 25°C, unless otherwise noted. limited to the maximum ratings given. Table 4. ADG1211/ADG1212 Truth Table Table 5. ADG1213 Truth Table

0 Off On

1 On Off

degradation or loss of functionality.

Figure 2. TSSOP Pin Configuration

  1. EXPOSED PAD TIED TO SUBSTRATE, VSS.

2 VSS

3 GND

11 VDD

5 D46 IN47 IN38 D3

Figure 3. LFCSP Pin Configuration Table 6. Pin Function Descriptions 1 15 IN1 Logic Control Input. 2 16 D1 Drain Terminal. Can be an input or output. 3 1 S1 Source Terminal. Can be an input or output. 4 2 VSS Most Negative Power Supply Potential. 5 3 GND Ground (0 V) Reference. 6 4 S4 Source Terminal. Can be an input or output. 7 5 D4 Drain Terminal. Can be an input or output. 8 6 IN4 Logic Control Input. 9 7 IN3 Logic Control Input. 10 8 D3 Drain Terminal. Can be an input or output. 11 9 S3 Source Terminal. Can be an input or output. 12 10 NC No Internal Connection. 13 11 VDD Most Positive Power Supply Potential. 14 12 S2 Source Terminal. Can be an input or output. 15 13 D2 Drain Terminal. Can be an input or output. 16 14 IN2 Logic Control Input.

ADG1211/ADG1212/ADG1213 Data Sheet Rev. B | Page 8 of 16 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. V D (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON The delay between applying the digital control input and the output switching on. See Figure 23. tOFF The delay between applying the digital control input and the output switching off. See Figure 23. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] XCEPT FOR EXPOSED PAD DIMENSION.

0.60 MAX

1.50 REF

0.25 MIN

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Data Sheet ADG1211/ADG1212/ADG1213 Rev. B | Page 15 of 16 ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding ADG1211YRUZ −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1211YRUZ-REEL −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1211YRUZ-REEL7 −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1211YCPZ-500RL7 −40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 S07 ADG1211YCPZ-REEL7 −40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 S07 ADG1212YRUZ −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1212YRUZ-REEL −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1212YRUZ-REEL7 −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1212YCPZ-500RL7 −40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 S08 ADG1212YCPZ-REEL7 −40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 S08 ADG1213YRUZ −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1213YRUZ-REEL −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1213YRUZ-REEL7 −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16 ADG1213YCPZ-500RL7 −40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 S09 ADG1213YCPZ-REEL7 −40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 S09 1 Z = RoHS Compliant Part.

ADG1211/ADG1212/ADG1213 Data Sheet Rev. B | Page 16 of 16 NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04778-0-8/12(B)