ADG1208YRUZ

ADG1208 AD | Alldatasheet

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Low Capacitance, 4-/8-Channel ±15 V/+12 V iCMOS™ Multiplexers ADG1208/ADG1209 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.

FEATURES

<1 pC charge injection over full signal range 1 pF off capacitance

33 V supply range

120 Ω on resistance Fully specified at ±15 V/+12 V

3 V logic compatible inputs

Break-before-make switching action Available in 16-lead TSSOP and 4 mm × 4 mm LFCSP_VQ Typical power consumption < 0.03 μW

APPLICATIONS

D ADG1209 S1A S4B DA DB S4A S1B 1-OF-4 DECODER 1-OF-8 DECODER A0 A1 ENA0 A1 A2 EN 05713-001 Figure 1. GENERAL DESCRIPTION The ADG1208 and ADG1209 are monolithic, iCMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG1208 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1, and A2. The ADG1209 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metal- oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the entire signal range of the device. iCMOS construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery powered instruments. VS (V) CHARGE INJECTION (pC) 1.0 –15 15 05713-051 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –10 –5 0 5 10 MUX (SOURCE TO DRAIN) TA =2 5 ° C VDD = +15V VSS = –15V VDD =+ 5 V VSS = –5V VDD = +12V VSS =0 V Figure 2. Source to Drain Charge Injection vs. Source Voltage

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

4/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 20 SPECIFICATIONS DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V , unless otherwise noted.1 Table 1. Parameter +25ºC −40ºC to +85ºC −40ºC to +125ºC Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to VDD V On Resistance, RON 120 Ω typ VS = ±10 V, IS = −1 mA, see Figure 29 200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between Channels, ∆RON 3.5 Ω typ VS = ±10 V, IS = −1 mA 6 10 12 Ω max On Resistance Flatness, RFLAT (On) 20 Ω typ VS = −5 V, 0 V, +5 V, IS = −1 mA 64 76 83 Ω max LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.02 nA typ VD = ±10 V, VS = −10 V, see Figure 30 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off ) ±0.02 nA typ VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 30 ADG1208 ±0.1 ±0.6 ±1 nA max ADG1209 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V, see Figure 31 ADG1208 ±0.2 ±0.6 ±1 nA max ADG1209 ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±0.005 μA max VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION 80 ns typ RL = 300 Ω, CL = 35 pF 130 165 185 ns max VS = 10 V, see Figure 32 tON (EN) 75 ns typ RL = 300 Ω, CL = 35 pF 95 105 115 ns max VS = 10 V, see Figure 34 tOFF (EN) 83 ns typ RL = 300 Ω, CL = 35 pF 100 125 140 ns max VS = 10 V, see Figure 34 Break-Before-Make Time Delay, tBBM 25 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 10 V, see Figure 33 Charge Injection 0.4 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 35 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36 Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38 Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz, see Figure 39 −3 dB Bandwidth 550 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37 CS (Off ) 1 pF typ f = 1 MHz, VS = 0 V 1.5 pF max f = 1 MHz, VS = 0 V CD (Off ) ADG1208 6 pF typ f = 1 MHz, VS = 0 V 7 pF max f = 1 MHz, VS = 0 V CD (Off ) ADG1209 3.5 pF typ f = 1 MHz, VS = 0 V 4.5 pF max f = 1 MHz, VS = 0 V

Rev. 0 | Page 4 of 20 Parameter +25ºC −40ºC to +85ºC −40ºC to +125ºC Unit Test Conditions/Comments CD, CS (On) ADG1208 7 pF typ f = 1 MHz, VS = 0 V 8 pF max f = 1 MHz, VS = 0 V CD, CS (On) ADG1209 5 pF typ f = 1 MHz, VS = 0 V 6 pF max f = 1 MHz, VS = 0 V POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 220 μA typ Digital inputs = 5 V 320 μA max ISS 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max ISS 0.002 μA typ Digital inputs = 5 V 1.0 μA max VDD/VSS ±5/±16.5 V min/max |VDD | = |VSS| 1 Temperature range is as follows: Y version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. 0 | Page 5 of 20 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted.1 Table 2. Parameter +25ºC −40ºC to +85ºC −40ºC to +125ºC Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 300 Ω typ VS = 0 V to10 V, IS = −1 mA, see Figure 29 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels, ∆RON 5 Ω typ VS = 0 V to 10 V, IS = −1 mA 16 26 27 Ω max On Resistance Flatness, RFLAT (On) 60 Ω typ VS = 3 V, 6 V, 9 V; IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V Source Off Leakage, IS (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 ADG1208 ±0.1 ±0.6 ±1 nA max ADG1209 ±0.1 ±0.6 ±1 nA max Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V; see Figure 31 ADG1208 ±0.2 ±0.6 ±1 nA max ADG1209 ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±0.001 ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION 100 ns typ RL = 300 Ω, CL = 35 pF 170 210 235 VS = 8 V, see Figure 32 tON (EN) 90 ns typ RL = 300 Ω, CL = 35 pF 110 140 160 VS = 8 V, see Figure 34 tOFF (EN) 105 ns typ RL = 300 Ω, CL = 35 pF 130 155 175 VS = 8 V, see Figure 34 Break-Before-Make Time Delay, tBBM 45 ns typ RL = 300 Ω, CL = 35 pF 20 ns min VS1 = VS2 = 8 V, see Figure 33 Charge Injection −0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 35 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36 Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38 −3 dB Bandwidth 450 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37 CS (Off ) 1.2 pF typ f = 1 MHz, VS = 6 V 1.8 pF max f = 1 MHz, VS = 6 V CD (Off ) ADG1208 7.5 pF typ f = 1 MHz, VS = 6 V 9 pF max f = 1 MHz, VS = 6 V CD (Off ) ADG1209 4.5 pF typ f = 1 MHz, VS = 6 V 5.5 pF max f = 1 MHz, VS = 6 V CD, CS (On) ADG1208 9 pF typ f = 1 MHz, VS = 6 V 10.5 pF max f = 1 MHz, VS = 6 V CD, CS (On) ADG1209 6 pF typ f = 1 MHz, VS = 6 V 7.5 pF max f = 1 MHz, VS = 6 V

Rev. 0 | Page 6 of 20 Parameter +25ºC −40ºC to +85ºC −40ºC to +125ºC Unit Test Conditions/Comments POWER REQUIREMENTS VDD = 13.2 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 220 μA typ Digital inputs = 5 V 330 μA max VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V 1 Temperature range is as follows: Y version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. 0 | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog, Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) Continuous Current, S or D 30 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle max) 100 mA Operating Temperature Range Industrial (Y Version) –40°C to +125°C Storage Temperature –65°C to +150°C Junction Temperature 150°C TSSOP , θJA, Thermal Impedance 112°C/W LFCSP_VQ, θJA, Thermal Impedance 30.4°C/W Reflow Soldering Peak Temperature (Pb-Free) 260(+0/−5)°C 1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. ADG1208 Pin Configuration (TSSOP)

11 VDD

12 GND

Figure 4. ADG1208 Pin Configuration (LFCSP_VQ), Table 4. ADG1208 Pin Function Descriptions 1 15 A0 Logic Control Input. 2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 4 2 S1 Source Terminal 1. Can be an input or an output. 5 3 S2 Source Terminal 2. Can be an input or an output. 6 4 S3 Source Terminal 3. Can be an input or an output. 7 5 S4 Source Terminal 4. Can be an input or an output. 8 6 D Drain Terminal. Can be an input or an output. 9 7 S8 Source Terminal 8. Can be an input or an output. 10 8 S7 Source Terminal 7. Can be an input or an output. 11 9 S6 Source Terminal 6. Can be an input or an output. 12 10 S5 Source Terminal 5. Can be an input or an output. 13 11 VDD Most Positive Power Supply Potential. 14 12 GND Ground (0 V) Reference. 15 13 A2 Logic Control Input. 16 14 A1 Logic Control Input. Table 5. ADG1208 Truth Table

Figure 5. ADG1209 Pin Configuration (TSSOP)

11 S1B

12 VDD

10 S2B

Figure 6. ADG1209 Pin Configurations (LFCSP_VQ), Table 6. ADG1209 Pin Function Descriptions 1 15 A0 Logic Control Input. 2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 4 2 S1A Source Terminal 1A. Can be an input or an output. 5 3 S2A Source Terminal 2A. Can be an input or an output. 6 4 S3A Source Terminal 3A. Can be an input or an output. 7 5 S4A Source Terminal 4A. Can be an input or an output. 8 6 DA Drain Terminal A. Can be an input or an output. 9 7 DB Drain Terminal B. Can be an input or an output. 10 8 S4B Source Terminal 4B. Can be an input or an output. 11 9 S3B Source Terminal 3B. Can be an input or an output. 12 10 S2B Source Terminal 2B. Can be an input or an output. 13 11 S1B Source Terminal 1B. Can be an input or an output. 14 12 VDD Most Positive Power Supply Potential. 15 13 GND Ground (0 V) Reference. 16 14 A1 Logic Control Input. Table 7. ADG1209 Truth Table

Figure 19. ADG1208 Crosstalk vs. Frequency Figure 20. ADG1209 Crosstalk vs. Frequency Figure 21. On Response vs. Frequency Figure 22. THD + N vs. Frequency Figure 23. ADG1208 Capacitance vs. Source Voltage, Figure 24. ADG1208 Capacitance vs. Source Voltage,

12 V Single Supply

Rev. 0 | Page 14 of 20 TERMINOLOGY RON Ohmic resistance between D and S. ΔRON Difference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD (VS) Analog voltage on terminals D, S. CS (Off) Channel input capacitance for off condition. CD (Off) Channel output capacitance for off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]

1.95 BSC

0.80 SEATING

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.65 BSC

0.60 MAX

Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 18 of 20 NOTES

Rev. 0 | Page 19 of 20 NOTES

Rev. 0 | Page 20 of 20 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05713-0-4/06(0)