ADG1206YCPZ-REEL7

ADG1206 AD | Alldatasheet

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Low Capacitance, 16- and 8-Channel ±15 V/+12 V i CMOS™ Multiplexers ADG1206/ADG1207 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

<1 pC charge injection over full signal range 1.5 pF off capacitance

33 V supply range

120 Ω on resistance Fully specified at ±15 V/+12 V

3 V logic-compatible inputs

Break-before-make switching action 28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP_VQ

APPLICATIONS

D 1-OF-16 DECODER A0 A1 A2 A3 EN 06119-001 Figure 1. GENERAL DESCRIPTION The ADG1206 and ADG1207 are monolithic iCMOS analog multiplexers comprising sixteen single channels and eight differential channels, respectively. The ADG1206 switches one of sixteen inputs to a common output, as determined by the 4- bit binary address lines A0, A1, A2, and A3. The ADG1207 switches one of eight differential inputs to a common differential output, as determined by the 3-bit binary address lines A0, A1, and A2. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metal- oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased perfor- mance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the entire signal range of the device. iCMOS construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments. VS (V) CHARGE INJECTION (pC) 1.0 –15 15 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –10 –5 0 5 10 MUX (SOURCE TO DRAIN) TA = 25°C VDD = +15V VSS = –15V VDD = +5V VSS = –5V VDD = +12V VSS = 0V 06119-002 Figure 2. Source-to-Drain Charge Injection vs. Source Voltage

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 20 SPECIFICATIONS DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V , unless otherwise noted.1 Table 1. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to VDD V On Resistance, RON 120 Ω typ VS = ±10 V, IS = −1 mA; see Figure 28 200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between Channels, ∆RON 3.5 Ω typ VS = ±10 V, IS = −1 mA 6 10 12 Ω max On Resistance Flatness, RFLAT (On) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA 64 76 83 Ω max LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.03 nA typ VD = ±10 V, VS = ∓10 V; see Figure 29 ±0.2 ±0.6 ±1 nA max Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 29 ±0.2 ±0.6 ±2 nA max Channel On Leakage, ID, IS (On) ±0.08 nA typ VS = VD = ±10 V; see Figure 30 ±0.2 ±0.6 ±2 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±0.005 μA typ VIN = VINL or VINH ±0.1 μA max Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION 80 ns typ RL = 300 Ω, CL = 35 pF 130 165 185 ns max VS = 10 V; see Figure 31 tON (EN) 75 ns typ RL = 300 Ω, CL = 35 pF 95 105 115 ns max VS = 10 V; see Figure 33 tOFF (EN) 85 ns typ RL = 300 Ω, CL = 35 pF 100 125 140 ns max VS = 10 V; see Figure 33 Break-Before-Make Time Delay, tBBM 20 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 10 V; see Figure 32 Charge Injection 0.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 34 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37 Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz; see Figure 38 −3 dB Bandwidth ADG1206 280 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36 −3 dB Bandwidth ADG1207 490 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36 CS (Off ) 1.5 pF typ f = 1 MHz, VS = 0 V 2 pF max f = 1 MHz, VS = 0 V CD (Off ) ADG1206 11 pF typ f = 1 MHz, VS = 0 V 12 pF max f = 1 MHz, VS = 0 V CD (Off ) ADG1207 7 pF typ f = 1 MHz, VS = 0 V 9 pF max f = 1 MHz, VS = 0 V

Rev. 0 | Page 4 of 20 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments CD, CS (On) ADG1206 13 pF typ f = 1 MHz, VS = 0 V 15 pF max f = 1 MHz, VS = 0 V CD, CS (On) ADG1207 8 pF typ f = 1 MHz, VS = 0 V 10 pF max f = 1 MHz, VS = 0 V POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 260 μA typ Digital inputs = 5 V 420 μA max ISS 0.002 μA typ Digital inputs = 0 V, 5 V, or VDD 1.0 μA max VDD/VSS ±5/±16.5 V min/max GND = 0V 1 Temperature range for Y version is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. 0 | Page 5 of 20 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted.1 Table 2. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 300 Ω typ VS = 0 V to10 V, IS = −1 mA; see Figure 28 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels, ∆RON 5 Ω typ VS = 0 V to 10 V, IS = −1 mA 16 26 27 Ω max On Resistance Flatness, RFLAT (On) 60 Ω typ VS = 3 V, 6 V, 9 V; IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V Source Off Leakage, IS (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 ±0.2 ±0.6 ±1 nA max Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 ±0.2 ±0.6 ±2 nA max Channel On Leakage, ID, IS (On) ±0.08 nA typ VS = VD = 1 V or 10 V; see Figure 30 ±0.2 ±0.6 ±2 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±0.001 μA typ ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION 100 ns typ RL = 300 Ω, CL = 35 pF 140 175 200 ns max VS = 8 V; see Figure 31 tON (EN) 80 ns typ RL = 300 Ω, CL = 35 pF 100 120 130 ns max VS = 8 V; see Figure 33 tOFF (EN) 90 ns typ RL = 300 Ω, CL = 35 pF 110 130 155 ns max VS = 8 V; see Figure 33 Break-Before-Make Time Delay, tBBM 25 ns typ RL = 300 Ω, CL = 35 pF 15 ns min VS1 = VS2 = 8 V; see Figure 32 Charge Injection 0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37 −3 dB Bandwidth ADG1206 185 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36 −3 dB Bandwidth ADG1207 300 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36 CS (Off ) 1.5 pF typ f = 1 MHz, VS = 6 V 2 pF max f = 1 MHz, VS = 6 V CD (Off ) ADG1206 13 pF typ f = 1 MHz, VS = 6 V 15 pF max f = 1 MHz, VS = 6 V CD (Off ) ADG1207 9 pF typ f = 1 MHz, VS = 6 V 11 pF max f = 1 MHz, VS = 6 V CD, CS (On) ADG1206 15 pF typ f = 1 MHz, VS = 6 V 17 pF max f = 1 MHz, VS = 6 V CD, CS (On) ADG1207 10 pF typ f = 1 MHz, VS = 6 V 12 pF max f = 1 MHz, VS = 6 V

Rev. 0 | Page 6 of 20 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = 13.2 V IDD 0.002 μA typ Digital inputs = 0 V or VDD 1.0 μA max IDD 260 μA typ Digital inputs = 5 420 μA max VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V 1 Temperature range for Y version is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. 0 | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog, Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Continuous Current, S or D 30 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) 100 mA Operating Temperature Ranges Industrial (Y Version) –40°C to +125°C Storage –65°C to +150°C Junction Temperature 150°C 28-Lead TSSOP θJA, Thermal Impedance 97.9°C/W θJC, Thermal Impedance 14°C/W 32-Lead LFCSP_VQ θJA, Thermal Impedance 27.27°C/W Reflow Soldering Peak Temperature (Pb-Free) 260(+0/−5)°C 1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. ADG1206 Pin Configuration—TSSOP Figure 4. ADG1206 Pin Configuration—5 mm × 5 mm LFCSP_VQ, Table 4. ADG1206 Pin Function Descriptions 1 31 VDD Most Positive Power Supply Potential. 4 1 S16 Source Terminal 16. Can be an input or an output. 5 2 S15 Source Terminal 15. Can be an input or an output. 6 3 S14 Source Terminal 14. Can be an input or an output. 7 4 S13 Source Terminal 13. Can be an input or an output. 8 5 S12 Source Terminal 12. Can be an input or an output. 9 6 S11 Source Terminal 11. Can be an input or an output. 10 7 S10 Source Terminal 10. Can be an input or an output. 11 8 S9 Source Terminal 9. Can be an input or an output. 12 9 GND Ground (0 V) Reference. 14 10 A3 Logic Control Input. 15 11 A2 Logic Control Input. 16 14 A1 Logic Control Input. 17 15 A0 Logic Control Input. turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 17 S1 Source Terminal 1. Can be an input or an output. 20 18 S2 Source Terminal 2. Can be an input or an output. 21 19 S3 Source Terminal 3. Can be an input or an output. 22 20 S4 Source Terminal 4. Can be an input or an output. 23 21 S5 Source Terminal 5. Can be an input or an output. 24 22 S6 Source Terminal 6. Can be an input or an output. 25 23 S7 Source Terminal 7. Can be an input or an output. 26 24 S8 Source Terminal 8. Can be an input or an output. 28 29 D Drain Terminal. Can be an input or an output.

Table 5. ADG1206 Truth Table

24 S8A

23 S7A

22 S6A

21 S5A

20 S4A

19 S3A

18 S2A

17 S1A

Figure 5. ADG1207 Pin Configuration—TSSOP Figure 6. ADG1207 Pin Configuration—5 mm × 5 mm LFCSP_VQ Table 6. ADG1207 Pin Function Descriptions 1 29 VDD Most Positive Power Supply Potential. 2 31 DB Drain Terminal B. Can be an input or an output. 4 1 S8B Source Terminal 8B. Can be an input or an output. 5 2 S7B Source Terminal 7B. Can be an input or an output. 6 3 S6B Source Terminal 6B. Can be an input or an output. 7 4 S5B Source Terminal 5B. Can be an input or an output. 8 5 S4B Source Terminal 4B. Can be an input or an output. 9 6 S3B Source Terminal 3B. Can be an input or an output. 10 7 S2B Source Terminal 2B. Can be an input or an output. 11 8 S1B Source Terminal 1B. Can be an input or an output. 12 9 GND Ground (0 V) Reference. 15 10 A2 Logic Control Input. 16 14 A1 Logic Control Input. 17 15 A0 Logic Control Input. turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 17 S1A Source Terminal 1A. Can be an input or an output. 20 18 S2A Source Terminal 2A. Can be an input or an output. 21 19 S3A Source Terminal 3A. Can be an input or an output. 22 20 S4A Source Terminal 4A. Can be an input or an output. 23 21 S5A Source Terminal 5A. Can be an input or an output. 24 22 S6A Source Terminal 6A. Can be an input or an output. 25 23 S7A Source Terminal 7A. Can be an input or an output. 26 24 S8A Source Terminal 8A. Can be an input or an output. 28 27 DA Drain Terminal A. Can be an input or an output.

Table 7. ADG1207 Truth Table

Rev. 0 | Page 16 of 20 TERMINOLOGY RON Ohmic resistance between D and S. ΔRON Difference between the RON of any two channels. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD (VS) Analog voltage on Terminals D and S. CS (Off) Channel input capacitance for the off condition. CD (Off) Channel output capacitance for the off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and the switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and the switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% points of the switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.

1.20 MAX

6.40 BSC

Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP] WITH EXCEPTION TO PADDLE ORIENTATION.

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00 MAX

0.85 NOM

3.50 REF

Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 20 of 20 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06119-0-7/06(0)