ADG1204

ADG1204 (Rev. C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

Low Capacitance, Low Charge Injection, ±15 V/+12 V, 4:1 iCMOS Multiplexer Data Sheet ADG1204 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

1.5 pF off source capacitance <1 pC charge injection

33 V supply range

120 Ω on resistance Fully specified at ±15 V, +12 V No V L supply required

3 V logic-compatible inputs

14-lead TSSOP and 12-lead LFCSP Typical power consumption < 0.03 μW

APPLICATIONS

D ENA1 A0

1 OF 4

Figure 1. GENERAL DESCRIPTION The ADG1204 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer, comprising four single channels designed on an iCMOS (industrial CMOS) process. iCMOS® is a modular manufacturing process that combines high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of this multiplexer makes it an ideal solution for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth makes the device suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the device ideally suited for portable and battery-powered instruments. The ADG1204 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines: A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break- before-make switching action. PRODUCT HIGHLIGHTS 1. 1.5 pF off capacitance (±15 V supply). 2. <1 pC charge injection. 3. 3 V logic-compatible digital inputs: VIH = 2.0 V , VIL = 0.8 4. No VL logic power supply required. 5. Ultralow power dissipation: <0.03 μW . 6. 14-lead TSSOP and 12-lead, 3 mm × 3 mm LFCSP packages.

Rev. C | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

3/16—Rev. B to Rev. C 2/09—Rev. A to Rev. B Changes to Power Requirements, IDD, Digital Inputs = 5 V Changes to Power Requirements, IDD, Digital Inputs = 5 V 7/06—Rev. 0 to Rev. A 7/05—Revision 0: Initial Version

Rev. C | Page 3 of 16 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) 120 Ω typ VS = ±10 V, IS = −1 mA; see Figure 21 190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between 3.5 Ω typ VS = ±10 V, IS = −1 mA Channels (ΔRON) 6 10 12 Ω max On Resistance Flatness (RFLAT(ON)) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA 57 72 79 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage, IS (OFF) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (ON) ±0.02 nA typ VS = VD = ±10 V; see Figure 23 ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or INH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max Digital Input Capacitance, CIN 2.5 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS 120 ns typ RL = 300 Ω, CL = 35 pF 150 180 200 ns max VS = 10 V; see Figure 24 tON (EN) 70 ns typ RL = 300 Ω, CL = 35 pF 85 100 110 ns max VS = 10 V; see Figure 26 tOFF (EN) 90 ns typ RL = 300 Ω, CL = 35 pF 110 135 155 ns max VS = 10 V; see Figure 26 Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 10 V; see Figure 25 Charge Injection −0.7 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz; see Figure 31 Bandwidth −3 dB 800 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (OFF) 1.2 pF typ f = 1 MHz, VS = 0 V 1.5 pF max f = 1 MHz, VS = 0 V CD (OFF) 3.6 pF typ f = 1 MHz, VS = 0 V 4.2 pF max f = 1 MHz, VS = 0 V CD, CS (ON) 5.5 pF typ f = 1 MHz, VS = 0 V 6.5 pF max f = 1 MHz, VS = 0 V

Rev. C | Page 4 of 16 Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 170 µA typ Digital inputs = 5 V 285 µA max ISS 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max ISS 0.001 µA typ Digital inputs = 5 V 1.0 µA max 1 Y version temperature range is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. C | Page 5 of 16 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA; see Figure 21 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels 5 Ω typ VS = 0 V to 10 V, IS = −1 mA (ΔRON) 16 26 27 Ω max On Resistance Flatness (RFLAT(ON)) 60 Ω typ VS = 3 V, 6 V, 9 V; IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V Source Off Leakage, IS (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; ±0.1 ±0.6 ±1 nA max see Figure 22 Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; ±0.1 ±0.6 ±1 nA max see Figure 22 Channel On Leakage, ID, IS (ON) ±0.02 nA typ VS = VD = 1 V or 10 V; see Figure 23 ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.001 µA typ VIN = VINL or VINH ±0.1 µA max Digital Input Capacitance, CIN 2.5 pF typ DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS 150 ns typ RL = 300 Ω, CL = 35 pF 190 240 265 ns max VS = 8 V; see Figure 24 tON (EN) 95 ns typ RL = 300 Ω, CL = 35 pF 120 150 170 ns max VS = 8 V; see Figure 26 tOFF (EN) 100 ns typ RL = 300 Ω, CL = 35 pF 125 155 170 ns max VS = 8 V; see Figure 26 Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 8 V; see Figure 25 Charge Injection −0.4 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Bandwidth −3 db 550 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (OFF) 1.2 pF typ f = 1 MHz; VS = 6 V 1.5 pF max f = 1 MHz; VS = 6 V CD (OFF) 3.6 pF typ f = 1 MHz; VS = 6 V 4.2 pF max f = 1 MHz; VS = 6 V CD, CS (ON) 5.5 pF typ f = 1 MHz; VS = 6 V 6.5 pF max f = 1 MHz; VS = 6 V

Rev. C | Page 6 of 16 Y Version1 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 170 µA typ Digital inputs = 5 V 285 µA max 1 Y version temperature range is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.

Rev. C | Page 7 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Digital Inputs1 GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Peak Current, S or D 100 mA (pulsed at 1 ms, 10% duty cycle maximum) Continuous Current 45 mA Operating Temperature Range Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 14-Lead TSSOP , θJA Thermal Impedance (4-Layer Board) 112°C/W 12-Lead LFCSP , θJA Thermal Impedance 80°C/W Reflow Soldering Peak Temperature, Pb Free 260°C 1 Overvoltages at IN, S, or D are clamped by internal diodes. Current must be limited to the maximum ratings given. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION

Figure 2. TSSOP Pin Configuration

1. NC = NO CONNECT. DO NOT CONNECT
2. THE EXPOSED PAD MUST BE TIED

Figure 3. LFCSP Pin Configuration Table 4. Pin Function Descriptions 1 11 A0 Logic Control Input. 2 12 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 3 1 VSS Most Negative Power Supply Potential. 4 2 S1 Source Terminal. Can be an input or an output. 5 3 S2 Source Terminal. Can be an input or an output. 6 4 D Drain Terminal. Can be an input or an output. 10 6 S4 Source Terminal. Can be an input or an output. 11 7 S3 Source Terminal. Can be an input or an output. 12 8 VDD Most Positive Power Supply Potential. 13 9 GND Ground (0 V) Reference. 14 10 A1 Logic Control Input.

0 X X Off Off Off Off

Rev. C | Page 14 of 16 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (OFF) The source leakage current with the switch off. ID (OFF) The drain leakage current with the switch off. ID, IS (ON) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (OFF) The off switch source capacitance, which is measured with reference to ground. CD (OFF) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON (EN) The delay between applying the digital control input and the output switching on. t OFF (EN) The delay between applying the digital control input and the output switching off. t TRANS The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by −3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

0.65 BSC

Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED. Figure 33. 12-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. C | Page 16 of 16 NOTES ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04779-0-3/16(C)