ADG1201

ADG1201 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 14

Technical content

Low Capacitance, Low Charge Injection, ±15 V/+12 V, iCMOS, SPST in SOT-23 Data Sheet ADG1201 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2008–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

2.4 pF typical off switch source capacitance, dual supply <1 pC charge injection Low leakage: 0.6 nA maximum at 85°C 120 Ω typical on resistance at 25°C, dual supply Fully specified at ±15 V, +12 V No V L supply required

3 V logic-compatible inputs

VINH = 2.0 V minimum VINL = 0.8 V maximum Rail-to-rail operation 6-lead SOT-23 package

APPLICATIONS

SWITCH SHOWN FOR A LOGIC 1 INPUT 06576-001 Figure 1. GENERAL DESCRIPTION The ADG1201 is a monolithic complementary metal-oxide semiconductor (CMOS) device containing a single-pole, single-throw (SPST) switch designed in an iCMOS® process. iCMOS is a modular manufacturing process combining a high voltage CMOS and bipolar technologies. iCMOS enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of this switch makes it an ideal solution for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth also makes the device suitable for video signal switching. iCMOS construction ensures ultra low power dissipation, making the device ideally suited for portable and battery- powered instruments. The ADG1201 contains a SPST switch. Figure 1 shows that with a logic input of 1, the switch of the ADG1201 is closed. The switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. PRODUCT HIGHLIGHTS 1. Ultralow capacitance. 2. <1 pC charge injection. 3. Ultralow leakage. 4. 3 V logic-compatible digital inputs: V INH = 2.0 V minimum, VINL = 0.8 V maximum. 5. No logic voltage (VL) power supply required. 6. SOT-23 package.

Rev. A | Page 2 of 14 TABLE OF CONTENTS

REVISION HISTORY

1/2019—Rev. 0 to Rev. A Changes to Features Section and Product Highlights Section ... 1 Changes to Absolute Maximum Ratings Section and Table 3 .... 6 Changes to Figure 9 Caption, Figure 10 Caption, and 2/2008—Revision 0: Initial Version

Rev. A | Page 3 of 14 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) 120 Ω typ VDD = +13.5 V, VSS = −13.5 V 200 240 270 Ω max Analog voltage on Terminal S (VS) = ±10 V, source leakage current (IS) = −1 mA, see Figure 20 On Resistance Flatness (RFLAT(ON)) 20 Ω typ VS = −5 V, 0 V, and +5 V, IS = −1 mA 60 72 79 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage (IS (Off )) ±0.004 nA typ VS = ±10 V, analog voltage on Terminal D (VD) = ±10 V, see Figure 21 ±0.1 ±0.6 ±1 nA max Drain Off Leakage (ID (Off )) ±0.004 nA typ VS = ±10 V, VD = ±10 V, see Figure 21 ±0.1 ±0.6 ±1 nA max Channel On Leakage (ID, IS (On)) ±0.04 nA typ VS = VD = ±10 V, see Figure 22 ±0.15 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage (VINH) 2.0 V min Input Low Voltage (VINL) 0.8 V max Input Current (IINL or IINH) 0.005 µA typ Voltage on IN pin (VIN) = VINL or VINH ±0.1 µA max Digital Input Capacitance (CIN) 2.5 pF typ DYNAMIC CHARACTERISTICS1 On Time (tON) 140 ns typ Load resistance (RL) = 300 Ω, load capacitance (CL) = 35 pF 170 200 230 ns max VS = 10 V, see Figure 26 Off Time (tOFF) 90 ns typ RL = 300 Ω, CL = 35 pF 105 130 141 ns max VS = 10 V, see Figure 26 Charge Injection −0.8 pC typ VS = 0 V, supply resistance (RS) = 0 Ω, CL = 1 n F, see Figure 27 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23 Total Harmonic Distortion + Noise (THD + N) 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz −3 dB Bandwidth 660 MHz typ RL = 50 Ω, CL = 5 pF , see Figure 24 Off Switch Source Capacitance (CS (Off )) 2.4 pF typ VS = 0 V, frequency = 1 MHz 3 pF max VS = 0 V, frequency = 1 MHz Off Switch Drain Capacitance (CD (Off )) 2.8 pF typ VS = 0 V, frequency = 1 MHz 3.3 pF max VS = 0 V, frequency = 1 MHz On Switch Capacitance (CD, CS (On)) 4.7 pF typ VS = 0 V, frequency = 1 MHz 5.6 pF max VS = 0 V, frequency = 1 MHz

Rev. A | Page 4 of 14 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V Positive Supply Current (IDD) 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 60 µA typ Digital inputs = 5 V 95 µA max Negative Supply Current (ISS) 0.001 µA typ Digital inputs = 0 V, 5 V, or VDD 1.0 µA max VDD/VSS ±5 to ±16.5 V min/max GND = 0 V 1 Guaranteed by design, not subject to production test. SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V , GND = 0 V , unless otherwise noted. Table 2. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V RON 300 Ω typ VDD = 10.8 V, VSS = 0 V 475 567 625 Ω max VS = 0 V to 10 V, IS = −1 mA, see Figure 20 RFL AT (ON ) 60 Ω typ VS = 3 V, 6 V, and 9 V, IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V IS (Off ) ±0.006 nA typ VS = 1 V or 10 V, VD = 10 V or 1 V, see Figure 21 ±0.1 ±0.6 ±1 nA max ID (Off ) ±0.006 nA typ VS = 1 V or 10 V, VD = 10 V or 1 V, see Figure 21 ±0.1 ±0.6 ±1 nA max ID, IS (On) ±0.04 nA typ VS = VD = 1 V or 10 V, see Figure 22 ±0.15 ±0.6 ±1 nA max DIGITAL INPUTS VINH 2.0 V min VINL 0.8 V max IINL or IINH 0.001 µA typ VIN = VINL or VINH ±0.1 µA max CIN 3 pF typ DYNAMIC CHARACTERISTICS1 tON 190 ns typ RL = 300 Ω, CL = 35 pF 250 295 340 ns max VS = 8 V, see Figure 26 tOFF 120 ns typ RL = 300 Ω, CL = 35 pF 155 190 210 ns max VS = 8 V, see Figure 26 Charge Injection 0.8 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 27 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, frequency = 1 MHz, see Figure 23 −3 dB Bandwidth 520 MHz typ RL = 50 Ω, CL = 5 pF , see Figure 24 CS (Off ) 2.7 pF typ VS = 6 V, frequency = 1 MHz 3.3 pF max VS = 6 V, frequency = 1 MHz CD (Off ) 3.1 pF typ VS = 6 V, frequency = 1 MHz 3.6 pF max VS = 6 V, frequency = 1 MHz CD, CS (On) 5.3 pF typ VS = 6 V, frequency = 1 MHz 6.3 pF max VS = 6 V, frequency = 1 MHz

Rev. A | Page 5 of 14 Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 60 µA typ Digital inputs = 5 V 95 µA max VDD 5 to 16.5 V min/max VSS = 0 V, GND = 0 V 1 Guaranteed by design, not subject to production test.

TA = 25°C, unless otherwise noted. limited to the maximum ratings given. PCB thermal design is required. the junction to case thermal resistance. Table 4. Thermal Resistance 1 Thermal impedance values measured on a JEDEC 1S2P thermal test board.

Figure 2. Pin Configuration Table 5. Pin Function Descriptions 1 V DD Most Positive Power Supply Potential. 2 GND Ground (0 V) Reference. 3 V SS Most Negative Power Supply Potential. 4 S Source Terminal. This pin can be an input or output. 5 D Drain Terminal. This pin can be an input or output. Table 6. ADG1201 Truth Table

0 Off

Rev. A | Page 13 of 14 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON The delay between applying the digital control input and the output switching on. See Figure 26. tOFF The delay between applying the digital control input and the output switching off. See Figure 26. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (AC PSRR) AC PSRR measures the ability of a device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the AC PSRR.

2.90 BSC

0.95 BSC

0.15 MAX

1.45 MAX

Figure 28. 6-Lead Small Outline Transistor Package [SOT-23] registered trademarks are the property of their respective owners.