ADFS5758

ADFS5758 AD | Alldatasheet

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Single-Channel, 16-Bit, Current/Voltage Output DAC, Functional Safety Approved for Unipolar Current Output Data Sheet ADFS5758 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Functional safety approved to SIL 2/SC3 for unipolar current output by TÜV Rheinland, File Number 968/FSP 2055.00/20 Current/voltage output available on a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, 0 mA to 24 mA, ±20 mA, ±24 mA, −1 mA to +22 mA Voltage output ranges (with 20% overrange): 0 V to 5 V,

0 V to 10 V, ±5 V, and ±10 V

Advanced on-chip diagnostics 12-bit ADC functioning as an independent monitoring function that can validate the output and accuracy. On-chip reference DPC for thermal management User-programmable offset and gain Robust architecture, including output fault protection EMC test standards IEC 61000-4-6 conducted immunity (10 V, Class A) IEC 61000-4-3 radiated immunity (20 V/m, Class A) IEC 61000-4-2 ESD (±6 kV contact, Class B) IEC 61000-4-4 electrical fast transient (EFT) (±4 kV, Class B) IEC 61000-4-5 surge (±4 kV, Class B) CISRP 11 radiated emissions (Class B) 32-lead, 5 mm × 5 mm LFCSP −40°C to +105°C temperature range

APPLICATIONS

Channel isolated analog outputs Programmable logic controller (PLC) and distributed control system (DCS) applications HART network connectivity GENERAL DESCRIPTION The ADFS5758 is a single-channel, 16-bit, current/voltage output DAC. The device is functional safety approved for unipolar current output and is a fully compliant item with a systematic capability of SC3, which can be used in safety-related applications up to SIL 2, according to IEC 61508. This arrangement allows a single ADFS5758 to be used to achieve SIL 2 for a nonredundant configuration. The safe state for the ADFS5758 is open circuit/high impedance. The ADFS5758 is a single-channel, voltage and current output digital-to-analog converter (DAC) that operates with a power supply range from −33 V minimum on AVSS to +33 V maximum on AVDD1 with a maximum operating voltage between the two rails of 60 V. On-chip dynamic power control (DPC) minimizes package power dissipation, which is achieved by regulating the supply voltage (VDPC+) to the VIOUT output driver circuitry from

4.95 V to 27 V using a buck dc-to-dc converter, optimized for

minimum on-chip power dissipation. The CHART pin enables a HART® signal to be coupled onto the current output. The device uses a versatile 4-wire serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface standards. The interface also features an optional SPI cyclic redundancy check (CRC) and a windowed watchdog timer. The ADFS5758 offers improved diagnostic features from its predecessors, such as an integrated independent 12-bit diagnostic analog-to-digital converter (ADC) that can be used to digitize both internal and external nodes. PRODUCT HIGHLIGHTS 1. Functional safety approved to SIL 2/SC3 by TÜV Rheinland. 2. Range of advanced diagnostic features, including an integrated ADC for high reliability. 3. DPC using an integrated buck dc-to-dc converter for thermal management. When used with the ADP1031, the ADFS5758 enables eight channel to channel isolated outputs at <2 W dissipated power. 4. Programmable power control (PPC) mode to enable faster settling time (15 µs typical). 5. Highly robust with output protection from miswire events (±38 V). COMPANION PRODUCTS Product Family: AD5755-1, AD5422, AD5758, AD5753, AD5423 HART Modem: AD5700, AD5700-1 External References: ADR431, ADR3425, ADR4525 Digital Isolators: ADuM142D, ADuM141D Power: ADP1031, LT8300, ADP2360, ADM6339

Rev. 0 | Page 2 of 75 TABLE OF CONTENTS Programming Sequence to Enable the Output Correctly .... 54

REVISION HISTORY

6/2020—Revision 0: Initial Version

Rev. 0 | Page 3 of 75 FUNCTIONAL BLOCK DIAGRAM ADFS5758 AVSS AGND AVDD1AVDD2 DGND SCLK SDI SDO DC-TO-DC CONVERTER SYNC FAULT DATA AND CONTROL REGISTERS DIGITAL BLOCK WATCHDOG TIMER STATUS REGISTER POWER-ON RESET REFERENCE BUFFERS DAC REG VREF CALIBRATION MEMORY VOUT RANGE SCALING REFOUT REFIN AD0 CLKOUT 16-BIT DAC 1616 SW+ VDPC+ USER GAIN USER OFFSET RB +VSENSE VIOUT –VSENSE CHART RA IOUT RANGE SCALING IOUT VOUT DYNAMIC POWER CONTROL AD1 REFGND POWER MANAGEMENT BLOCK VLOGIC CCOMP PGND1 ADC1 TEMPERATURE SENSOR ANALOG DIAGNOSTICS RESET VLDO VDPC+ 10MHz RSET VX VIOUT_PULLDOWN_EN LDAC 3-WIRE INTERFACE HART_EN MCLK VDPC+ ADC2 21790-001 INDEPENDENT MONITORING ADC Figure 1.

Rev. 0 | Page 4 of 75 SPECIFICATIONS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = −15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: load resistance (RLOAD) = 1 kΩ, load capacitance (CL) = 220 pF; current output: RL = 300 Ω; all specifications at TA = −40°C to +105°C, TJ < 125°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CURRENT OUTPUT Output Current Ranges (IOUT) 0 24 mA Functional safety approved range 0 20 mA Functional safety approved range 4 20 mA Functional safety approved range −20 +20 mA −24 +24 mA −1 +22 mA Resolution 16 Bits CURRENT OUTPUT ACCURACY (EXTERNAL CURRENT SETTING RESISTOR (RSET))1 Assumes ideal 13.7 kΩ resistor Unipolar Ranges 4 mA to 20 mA, 0 mA to 20 mA, and 0 mA to 24 mA ranges Total Unadjusted Error (TUE) −0.06 +0.06 % FSR −0.012 +0.012 % FSR TA = 25°C TUE Long-Term Stability 125 ppm FSR Drift after 1000 hours, TJ = 135°C Output Drift 3 7 ppm FSR/°C Integral Nonlinearity (INL) −0.006 +0.006 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.03 ±0.002 +0.03 % FSR Zero-Scale Temperature Coefficient (TC)3 ±0.5 ppm FSR/°C Offset Error −0.03 ±0.001 +0.03 % FSR Offset Error TC3 ±0.7 ppm FSR/°C Gain Error −0.05 ±0.001 +0.05 % FSR Gain Error TC3 ±3 ppm FSR/°C Full-Scale Error −0.05 ±0.001 +0.05 % FSR Full-Scale Error TC3 ±3 ppm FSR/°C Bipolar Ranges ±20 mA, ±24 mA, and −1 mA to +22 mA ranges TUE −0.08 +0.08 % FSR −0.014 +0.014 % FSR TA = 25°C TUE Long-Term Stability2 125 ppm FSR Drift after 1000 hours, TJ = 135°C Output Drift 12 15.5 ppm FSR/°C INL −0.01 +0.01 % FSR DNL −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.04 ±0.002 +0.04 % FSR Zero-Scale TC3 ±0.9 ppm FSR/°C Bipolar Zero Error −0.02 ±0.002 +0.02 % FSR Bipolar Zero Error TC3 ±0.4 ppm FSR/°C Offset Error −0.06 ±0.002 +0.06 % FSR Offset Error TC3 ±0.9 ppm FSR/°C Gain Error −0.08 ±0.002 +0.08 % FSR Gain Error TC3 ±4 ppm FSR/°C Full-Scale Error −0.08 ±0.002 +0.08 % FSR Full-Scale Error TC3 ±3 ppm FSR/°C

Rev. 0 | Page 5 of 75 Parameter Min Typ Max Unit Test Conditions/Comments CURRENT OUTPUT ACCURACY (INTERNAL RSET) Unipolar Ranges 4 mA to 20 mA, 0 mA to 20 mA, and 0 mA to 24 mA ranges TUE −0.12 +0.12 % FSR TUE Long-Term Stability2 380 ppm FSR Drift after 1000 hours, TJ = 135°C Output Drift 3 6 ppm FSR/°C Output drift INL −0.01 +0.01 % FSR DNL −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.04 ±0.001 +0.04 % FSR Zero-Scale TC3 ±0.5 ppm FSR/°C Offset Error −0.04 ±0.001 +0.04 % FSR Offset Error TC3 ±1 ppm FSR/°C Gain Error −0.1 ±0.003 +0.1 % FSR Gain Error TC3 ±3 ppm FSR/°C Full-Scale Error −0.12 ±0.003 +0.12 % FSR Full-Scale Error TC3 ±3 ppm FSR/°C Bipolar Ranges ±20 mA, ±24 mA, and −1 mA to +22 mA ranges TUE −0.12 +0.12 % FSR TUE Long-Term Stability2 380 ppm FSR Drift after 1000 hours, TJ = 135°C Output Drift 3 6 ppm FSR/°C Output drift INL −0.02 +0.02 % FSR DNL −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.06 ±0.001 +0.06 % FSR Zero-Scale TC3 ±2 ppm FSR/°C Bipolar Zero Error −0.02 ±0.002 +0.02 % FSR Bipolar Zero Error TC3 ±0.3 ppm FSR/°C Offset Error −0.06 ±0.001 +0.06 % FSR Offset Error TC3 ±1 ppm FSR/°C Gain Error −0.12 ±0.003 +0.12 % FSR Gain Error TC3 ±3 ppm FSR/°C Full-Scale Error −0.12 ±0.005 +0.12 % FSR Full-Scale Error TC3 ±3 ppm FSR/°C CURRENT OUTPUT CHARACTERISTICS Headroom 2.3 V Minimum voltage required between VIOUT and VDPC+ supply Footroom 2.35/0 V Minimum voltage required between VIOUT and AVSS supply and unipolar ranges do not require any footroom Resistive Load3 1000 Ω The dc-to-dc converter is characterized with a maximum load of 1 kΩ, chosen such that headroom/footroom compliance is not exceeded Output Impedance 100 MΩ Midscale output DC Power Supply Rejection Ratio (PSRR) 0.1 µA/V

Rev. 0 | Page 6 of 75 Parameter Min Typ Max Unit Test Conditions/Comments VOLTAGE OUTPUT Output Voltage Ranges (VOUT) 0 5 V Trimmed VOUT ranges 0 10 V −5 +5 V −10 +10 V Output Voltage Overranges 0 6 V Untrimmed overranges 0 12 V −6 +6 V −12 +12 V Output Voltage Offset Ranges −0.3 +5.7 V Untrimmed negatively offset ranges −0.4 +11.6 V Resolution 16 Bits VOLTAGE OUTPUT ACCURACY Loaded and unloaded, accuracy specifications refer to trimmed VOUT ranges only, unless otherwise noted TUE −0.05 +0.05 % FSR TUE Long-Term Stability2 15 ppm FSR Drift after 1000 hours, TJ = 135°C Output Drift 0.35 1.35 ppm FSR/°C Output drift Relative Accuracy (INL) −0.006 +0.006 % FSR All ranges DNL −1 +1 LSB Guaranteed monotonic, all ranges Zero-Scale Error −0.02 ±0.002 +0.02 % FSR Zero-Scale Error TC3 ±0.3 ppm FSR/°C Bipolar Zero Error −0.015 +0.001 +0.015 % FSR ±5 V, ±10 V Bipolar Zero Error TC3 ±0.3 ppm FSR/°C ±5 V, ±10 V Offset Error −0.02 ±0.002 +0.02 % FSR Offset Error TC3 ±0.3 ppm FSR/°C Gain Error −0.02 ±0.001 +0.02 % FSR Gain Error TC3 ±0.3 ppm FSR/°C Full-Scale Error −0.02 ±0.001 +0.02 % FSR Full-Scale Error TC3 ±0.3 ppm FSR/°C VOLTAGE OUTPUT CHARACTERISTICS Headroom 2 V Minimum voltage required between VIOUT and VDPC+ supply Footroom 2 V Minimum voltage required between VIOUT and AVSS supply Short-Circuit Current 16 mA Load3 1 kΩ For specified performance Capacitive Load Stability3 10 nF 2 µF External compensation capacitor of 220 pF connected DC Output Impedance 7 mΩ DC PSRR 10 µV/V VOUT/−VSENSE Common-Mode Rejection Ratio (CMRR) 10 µV/V Error in VOUT voltage due to changes in −VSENSE voltage

Rev. 0 | Page 7 of 75 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT Reference Input Reference Input Voltage4 2.5 V For specified performance DC Input Impedance 55 120 MΩ Reference Output Output Voltage 2.495 2.5 2.505 V TA = 25°C (including drift after 1000 hours at TJ = 135°C) Reference TC3 −10 +10 ppm/°C Output Noise (0.1 Hz to

10 Hz)3

7 µV p-p Noise Spectral Density3 80 nV/√Hz At 10 kHz Capacitive Load3 1000 nF Load Current 3 mA Short-Circuit Current 5 mA Line Regulation 1 ppm/V Load Regulation 80 ppm/mA Thermal Hysteresis3 150 ppm VLDO OUTPUT Output Voltage 3.3 V Output Voltage TC3 25 ppm/°C Output Voltage Accuracy −2 +2 % Externally Available Current 30 mA Short-Circuit Current 55 mA Load Regulation 0.8 mV/mA Capacitive Load 0.1 µF Recommended operation DC-TO-DC Start-Up Time 1.25 ms Switch Peak Current Limit3 150 400 mA User programmable in 50 mA steps via the DCDC_CONFIG2 register Oscillator Oscillator Frequency (fSW) 500 kHz Minimum Duty Cycle 5 % Current Output DPC Mode Current output dynamic power control mode VDPC+ Voltage Range 4.95 27 V Assuming sufficient supply margin between AVDD1 and VDPC+; see the Power Dissipation Control section for further details; maximum operating range of |VDPC+ to AVSS| = 50 V VDPC+ Headroom 2.3 2.5 V Typical voltage headroom between VIOUT and VDPC+; only applicable when dc-to-dc converter is in regulation (that is, load is sufficiently high) Current Output PPC Mode PPC mode VDPC+ Voltage Range 5 25.677 V Assuming sufficient supply margin between AV DD1 and VDPC+; see the Power Dissipation Control section for further details; maximum operating range of |VDPC+ to AVSS| = 50 V VDPC+ Voltage Accuracy −500 +500 mV Only applicable when dc-to-dc is operating in regulation (that is, load is sufficiently high) Voltage Output DPC Mode Voltage output dynamic power control mode VDPC+ Voltage Range 5 15 25 V 5 V = −VSENSE (MIN) + 15 V; 25 V = −VSENSE (MAX) + 15 V; assuming sufficient supply margin between AVDD1 and VDPC+; see the Power Dissipation Control section for further details; maximum operating range of |V DPC+ to AVSS| = 50 V VDPC+ Voltage Accuracy −500 +500 mV Only applicable when dc-to-dc is operating in regulation (that is, load sufficiently high)

Rev. 0 | Page 8 of 75 Parameter Min Typ Max Unit Test Conditions/Comments VIOUT LINE PROTECTOR On Resistance (RON) 12 Ω TA = 25°C Overvoltage Response Time (tRESPONSE) 250 ns Overvoltage Leakage Current ±100 µA Line protector fault detect block sinks current for a positive fault and sources current for a negative fault ADC Resolution 12 Bits Input Voltage Range ADC1 Pin 0 0.5 V ADC_IP_SELECT = 10000 −0.5 +0.5 V ADC_IP_SELECT = 10010, AVSS must be ≤−1 V 0 1.25 V ADC_IP_SELECT = 01111 0 2.5 V ADC_IP_SELECT = 10001 ADC2 Pin −15 +15 V Total Error ADC1 Pin −0.25 +0.25 % FSR 2.5 V input range −0.3 +0.3 % FSR 1.25 V input range −0.5 +0.5 % FSR 0 V to 0.5 V and ±0.5 V input ranges ADC2 Pin −0.5 +0.5 % FSR All other ADC Inputs ±0.3 % FSR Table 19 lists all ADC input nodes Conversion Time3 100 µs DIGITAL INPUTS Input Voltage 3 V ≤ VLOGIC ≤ 5.5 V High, VIH 0.7 × VLOGIC V Low, VIL 0.3 × VLOGIC V

1.71 V ≤ VLOGIC < 3 V

High, VIH 0.8 × VLOGIC V Low, VIL 0.2 × VLOGIC V Input Current −1.5 +1.5 µA Per pin, internal pull-down on SCLK, SDI, RESET, and LDAC; internal pull-up on SYNC Pin Capacitance3 2.4 pF Per pin DIGITAL OUTPUTS SDO Output Voltage Low, VOL 0.4 V Sinking 200 µA High, VOH VLOGIC − 0.2 V Sourcing 200 µA High Impedance Leakage Current −1 +1 µA High Impedance Output Capacitance3 2.2 pF FAULT Output Voltage Low, VOL 0.4 V 10 kΩ pull-up resistor to VLOGIC 0.6 V At 2.5 mA High, VOH VLOGIC − 0.05 V 10 kΩ pull-up resistor to VLOGIC

Rev. 0 | Page 9 of 75 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS Supply Voltages AVDD15 7 33 V Maximum operating range of |AVDD1 to AVSS| = 60 V AVDD2 5 33 V Maximum operating range of |AVDD2 to AVSS| = 50 V AVSS5 −33 0 V Maximum operating range of |AVDD1 to AVSS| =

60 V; for bipolar output ranges, VOUT/IOUT head-

room must be obeyed when calculating AVSS maximum; for unipolar current output ranges, AVSS maximum = 0 V; for unipolar voltage output ranges, AVSS maximum = −2 V VLOGIC 1.71 5.5 V Supply Quiescent Currents5 Quiescent current, assuming no load current AVDD1 Current (AIDD1) 0.05 0.11 mA Voltage output mode, dc-to-dc converter enabled but not active 0.05 0.11 mA Current output mode, dc-to-dc converter enabled but not active AVDD2 Current (AIDD2) 3.3 3.6 mA Voltage output mode, dc-to-dc converter enabled but not active 2.9 3.1 mA Current output mode, dc-to-dc converter enabled but not active AVSS Current (AISS) −1.4 −1.1 mA Voltage output mode −3.15 −2.4 mA Bipolar current output mode −0.26 −0.23 mA Unipolar current output mode VLOGIC Current (ILOGIC) 0.01 mA VIH = VLOGIC, VIL = DGND VDPC+ Current (IDPC+) 1.0 1.3 mA Voltage output mode 0.8 1 mA Unipolar current output mode 2.4 3.15 mA Bipolar current output mode Power Dissipation Power dissipation assuming an ideal power supply and excluding external load power dissipation, current output DPC mode, 0 mA to 20 mA range 103 mW AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −15 V, RLOAD = 1 kΩ, IOUT = 20 mA 145 mW AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −15 V, RLOAD = 0 Ω, IOUT = 20 mA 155 mW AVDD1 = AVDD2 = 24 V, AVSS = −15 V, RLOAD = 1 kΩ, IOUT = 20 mA 200 mW AVDD1 = AVDD2 = 24 V, AVSS = −15 V, RLOAD = 0 Ω, IOUT = 20 mA 1 See the Current Output Mode section for more information about the internal and external RSET resistors. 2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 3 Guaranteed by design and characterization; not production tested. 4 The ADFS5758 is factory calibrated with an external 2.5 V reference connected to REFIN. 5 Production tested to AVDD1 maximum = 30 V and AVSS minimum = −30 V.

Rev. 0 | Page 10 of 75 AC PERFORMANCE CHARACTERISTICS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = −15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 kΩ, CL = 220 pF; current output: RL = 300 Ω; all specifications at TA = −40°C to +105°C, TJ < 125°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Current Output Output Current Settling Time 15 µs To 0.1% FSR (0 mA to 24 mA), dc-to-dc converter disabled 15 µs PPC mode, dc-to-dc converter enabled, dc-to-dc current limit = 150 mA 200 µs DPC mode, dc-to-dc converter enabled; external inductor and capacitor components as described in Table 10, dc-to-dc current limit = 150 mA. Output Noise (0.1 Hz to 10 Hz Bandwidth)

0.2 LSB p-p 16-bit LSB, 0 mA to 24 mA range

Output Noise Spectral Density 0.8 nA/√Hz Measured at 10 kHz, midscale output, 0 mA to 24 mA range AC PSRR 80 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage Voltage Output Output Voltage Settling Time Output voltage settling time specifications also apply for dc- to-dc converter enabled 6 20 µs 5 V step to ±0.03% FSR, 0 V to 5 V range 12 20 µs 10 V step to ±0.03% FSR, 0 V to 10 V range 15 µs 100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V range Slew Rate 3 V/µs 0 V to 10 V range, digital slew rate control disabled Power-On Glitch Energy 25 nV-sec Digital-to-Analog Glitch Energy 5 nV-sec Glitch Impulse Peak Amplitude 25 mV Digital Feedthrough 2 nV-sec Output Noise (0.1 Hz to 10 Hz Bandwidth)

0.2 LSB p-p 16-bit LSB, 0 V to 10 V range

Output Noise Spectral Density 185 nV/√Hz Measured at 10 kHz, midscale output, 0 V to 10 V range AC PSRR 70 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage 1 Guaranteed by design and characterization; not production tested.

Rev. 0 | Page 11 of 75 TIMING CHARACTERISTICS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = −15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 kΩ, CL = 220 pF; current output: RL = 300 Ω; all specifications at TA = −40°C to +105°C, TJ < 125°C, unless otherwise noted. Table 3. Parameter1, 2, 3 1.71 V ≤ V LOGIC < 3 V 3 V ≤ V LOGIC ≤ 5.5 V Unit Description t1 33 20 ns min SCLK cycle time, write operation 120 66 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time, write operation 60 33 ns min SCLK high time, read operation t3 16 10 ns min SCLK low time, write operation 60 33 ns min SCLK low time, read operation t4 10 10 ns min SYNC falling edge to SCLK falling edge setup time, write operation 33 33 ns min SYNC falling edge to SCLK falling edge setup time, read operation t5 10 10 ns min 24th/32nd SCLK falling edge to SYNC rising edge t6 500 500 ns min SYNC high time (all register writes outside of those listed in this table) 1.5 1.5 μs min SYNC high time (DAC_INPUT register write) 500 500 μs min SYNC high time (DAC_CONFIG register write, where the range bits, Bits[3:0], change; see the Calibration Memory CRC section) t7 5 5 ns min Data setup time t8 6 6 ns min Data hold time t9 750 750 ns min LDAC falling edge to SYNC rising edge t10 1.5 1.5 μs min SYNC rising edge to LDAC falling edge t11 250 250 ns min LDAC pulse width low t12 600 600 ns max LDAC falling edge to DAC output response time, digital slew rate control disabled 2 2 μs max LDAC falling edge to DAC output response time, digital slew rate control enabled t13 See the AC Performance Characteristics section μs max DAC output settling time t14 1.5 1.5 μs max SYNC rising edge to DAC output response time (LDAC = 0) t15 5 5 μs min RESET pulse width t16 40 28 ns max SCLK rising edge to SDO valid t17 100 100 μs min RESET rising edge to first SCLK falling edge after SYNC falling edge (t17 does not appear in the timing diagrams) 1 Guaranteed by design and characterization. Not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V. tR is rise time. tF is fall time. 3 See Figure 2 to Figure 5.

±200 mA do not cause silicon controlled rectifier (SCR) latch-up.

1 Power dissipated on chip must be derated to keep the junction temperature

2 As per ANSI/ESDA/JEDEC JS-001, all pins. 3 As per ANSI/ESDA/JEDEC JS-002, all pins. operational section of this specification is not implied. extended periods may affect product reliability. Table 5. Thermal Resistance

1 Test Condition 1: thermal impedance simulated values are based on a JEDEC 2S2P

thermal test board with thermal vias. See JEDEC JESD51.

23 AD0

22 AD1

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE

Figure 6. Pin Configuration Table 6. Pin Function Descriptions 1 SW+ Switching Output for the DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 77. 2 AVDD1 Positive Analog Supply. The voltage range is from 7 V to 33 V. 3 AVDD2 Positive Low Voltage Analog Supply. The voltage range is from 5 V to 33 V. 4 ADC1 Multiplexed ADC External Input 1 (Input Range of 0 V to 0.5 V, 0 V to 2.5 V, or ±0.5 V). 5 AGND Ground Reference Point for the Analog Circuitry. This pin must be connected to 0 V. 6 REFGND Ground Reference Point for Internal Reference. This pin must be connected to 0 V. external resistor be placed as close as possible to the ADFS5758. external resistor be placed as close as possible to the ADFS5758. 9 REFIN External 2.5 V Reference Voltage Input. capacitor between REFOUT and REFGND is not recommended. HART_EN bit in the GP_CONFIG1 register. 12 VLDO 3.3 V Low Dropout (LDO) Output Voltage. VLDO must be decoupled to AGND with a 0.1 µF capacitor. readback mode is 15 MHz (depending on the VLOGIC voltage). See the Timing Characteristics section. hardware RESET pin or via software). Timing Characteristics section for the timing specifications). oscillator (MCLK) and is configured in the GP_CONFIG1 register. speed is 15 MHz (depending on the VLOGIC voltage). See the Timing Characteristics section for the timing specifications. 20 SDI Serial Data Input. Data must be valid on the falling edge of SCLK.

Rev. 0 | Page 16 of 75 Pin No. Mnemonic Description 21 SYNC Frame Synchronization Signal for the Serial Interface. Active low input. While SYNC is low, data is transferred in on the falling edge of SCLK. 22 AD1 Address Decode 1 for the ADFS5758 on the Board. 23 AD0 Address Decode 0 for the ADFS5758 on the Board. 24 FAULT Fault Pin. Active low, open-drain output. This pin is high impedance when no faults are detected and is asserted low when certain faults are detected, for example, an open circuit in current mode, a short circuit in voltage mode, a CRC error, or an overtemperature error (see the Output Fault section). This pin must be connected to VLOGIC with a 10 kΩ pull-up resistor. 25 AVSS Negative Analog Supply. The voltage range is from 0 V to −33 V. If using the device solely for unipolar current output purposes, AVSS can be 0 V. For a unipolar voltage output, AVSS (maximum) is −2.5 V. When using bipolar output ranges, VOUT/IOUT headroom must be obeyed when calculating the AVSS maximum. For example, for a ±10 V output, the AVSS maximum is −12.5 V. See the AVSS Considerations section for an important note on power supply sequencing. 26 −VSENSE Sense Connection for the Negative Voltage Output Load Connection for VOUT Mode. This pin must stay within ±10 V of AGND for specified operation. It is recommended to connect a series 1 kΩ resistor to this pin. If remote sensing is not being used, short this pin to AGND via the 1 kΩ resistor. 27 CCOMP Optional Compensation Capacitor Connection for the Voltage Output Buffer. Connecting a 220 pF capacitor between this pin and the VIOUT pin allows the voltage output to drive up to 2 µF. The addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 28 +VSENSE Sense Connection for the Positive Voltage Output Load Connection for Voltage Output Mode. It is recommended to connect a series 1 kΩ resistor to this pin. If remote sensing is not being used, short this pin to VIOUT via the 1 kΩ resistor. 29 VIOUT Voltage/Current Output Pin. VIOUT is a shared pin, providing either a buffered output voltage or current. 30 ADC2 Multiplexed ADC External Input 2 (Input Range of ±15 V). 31 VDPC+ Positive Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect as shown in Figure 77. 32 PGND1 Power Ground. EPAD Exposed Pad. Connect the exposed pad to the potential of the AVSS pin, or, alternatively, it can be left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.

Figure 45. DNL Erorr vs. AVDD1/|AVSS| Supply Figure 46. Total Unadjusted Error vs. AVDD1/|AVSS| Supply Figure 47. Sink and Source Capability of the Output Amplifier Figure 48. Full-Scale Positive Step Figure 49. Full-Scale Negative Step

0 TO 10V RANGE

Figure 50. Digital-to-Analog Glitch Major Code Transition

Rev. 0 | Page 29 of 75 TERMINOLOGY Total Unadjusted Error (TUE) TUE is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or INL, is a measure of the maximum deviation, in LSBs or % FSR, from the best fit line passing through the DAC transfer function. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The ADFS5758 is monotonic over its full operating temperature range. Zero-Scale/Negative Full-Scale Error Zero-scale/negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC output register. Zero-Scale Temperature Coefficient (TC) Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC output register is loaded with 0x8000 (straight binary coding). Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Offset Error Offset error is the deviation of the analog output from the ideal and is measured using ¼ scale and ¾ scale digital code measurements. It is expressed in % FSR. Offset Error (TC) Offset error TC is a measure of the change in the offset error with a change in temperature. It is expressed in ppm FSR/°C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature. Gain error TC is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC output register. Ideally, the output is full-scale − 1 LSB. Full-scale error is expressed in % FSR. Headroom Headroom is the difference between the voltage required at the output (programmed voltage in voltage output mode and programmed current × RLOAD in current output mode) and the voltage supplied by the positive supply rail, VDPC+. Headroom is relevant when the output is positive with respect to ground. Footroom Footroom is the difference between the voltage required at the output (programmed voltage in voltage output mode and programmed current × RLOAD in current output mode) and the voltage supplied by the negative supply rail, AVSS. Footroom is relevant when the output is negative with respect to ground. VOUT/−VSENSE Common-Mode Rejection Ratio (CMRR) VOUT/−VSENSE CMRR is the error in VOUT voltage due to changes in −VSENSE voltage. Current Loop Compliance Voltage The maximum voltage at the VIOUT pin for which the output current is equal to the programmed value. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at 25°C compared to the output voltage measured at 25°C after cycling the temperature from 25°C to −40°C to +105°C and then back to 25°C. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: −= TempRangeV VVTC NOMREF MINREFMAXREF where: VREF_MAX is the maximum reference output measured over the total temperature range. VREF_MIN is the minimum reference output measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range, −40°C to +105°C. Line Regulation Line regulation is the change in reference output voltage due to a specified change in power supply voltage. It is expressed in ppm/V.

Rev. 0 | Page 30 of 75 Load Regulation Load regulation is the change in reference output voltage due to a specified change in reference load current. It is expressed in ppm/mA. Dynamic Power Control (DPC) In this mode, the ADFS5758 circuitry senses the output voltage and dynamically regulates the supply voltage, V DPC+, to meet compliance requirements plus an optimized headroom voltage for the output buffer. Programmable Power Control (PPC) In this mode, the VDPC+ voltage is user programmable to a fixed level that must accommodate the maximum output load required. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. This specification depends on the manner in which the DPC feature is configured (enabled, disabled, or PPC mode enabled) and on the characteristics of the external dc-to-dc inductor and capacitor components used. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is expressed in V/µs. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the ADFS5758 is powered on. It is specified as the area of the glitch in nV-sec. Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the energy of the impulse injected into the analog output when the input code in the DAC output register changes state. It is normally specified as the area of the glitch in nV-sec. Worst case is usually when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC output register changes state. It is specified as the amplitude of the glitch in millivolts and worst case is usually when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated (LDAC pin is held high). It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage.

industrial factory automation and process control applications. performed over an internal 3-wire interface. requirements of IEC 61508 and is approved by TÜV Rheinland. of the full-scale range, proportional to the digital input code. For example, 2.5% of a 4 mA to 20 mA range is 400 µA. Safety Manual) on request from Analog Devices, Inc. the VIOUT pin. Only one mode can be enabled at any one time. used for the voltage to current conversion. Figure 74. Voltage-to-Current Conversion Circuitry unipolar or bipolar voltage range (see Figure 75). Figure 75. Voltage Output buffered before it is applied to the DAC. internal reference to drive the DAC.

compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary. addressed via the SPI interface. Table 7. Writing to a Register (CRC Enabled) Table 8. Ideal Output Voltage to Input Code Relationship allow time for internal calibrations to take place (see Figure 93). Figure 76. Power-On Reset Block Diagram four supply rails and the associated conditions. VDPC+ voltage for a given mode of operation. Table 9. AVDD1 to VDPC+ Margin the dc-to-dc converter modes of operation.

Rev. 0 | Page 33 of 75 Calculating Supply Voltage Assuming DPC current mode, use the following equations to calculate the voltage and current values: VDPC+ Maximum = IOUT Maximum Voltage + IOUT Headroom = 22.5 V where: IOUT Maximum = 20 mA (RLOAD = 1 kΩ). IOUT Maximum Voltage is IOUT Maximum × RLOAD = 20 V. IOUT Headroom = 2.5 V. |VDPC+ to AVDD1| headroom can be calculated as 5% of 22.5 V = 1.125 V. Therefore, AVDD1 minimum = 22.5 V + 1.125 V = 23.625 V. Assuming a worst case AVDD1 supply rail tolerance of ±10%, this example requires an AVDD1 supply rail of approximately 26.25 V. AVSS Considerations AVSS is the negative supply rail and has a range of −33 V to 0 V. As in the case of AVDD1, AVSS must obey the maximum operating range of |AVDD1 to AVSS| of 60 V. For bipolar current output ranges, the maximum AVSS can be calculated as (IOUT_MAX × RLOAD) + IOUT footroom. For unipolar current output ranges, AVSS can be tied to AGND (that is, 0 V). For unipolar voltage output ranges, the maximum AVSS is −2 V to enable sufficient footroom for the internal voltage output circuitry. To avoid power supply sequencing issues, a Schottky diode must be placed between AVSS and GND (the GND supply must always be available). AVDD2 Considerations AVDD2 is the positive low voltage supply rail and has a range of 5 V to 33 V. If only one positive power rail is available, AVDD2 can be tied to AVDD1. However, to optimize for reduced power dissipation, supply AVDD2 with a separate lower voltage supply. VLOGIC Considerations VLOGIC is the digital supply for the device and can range from 1.71 V to 5.5 V. The 3.3 V VLDO output voltage can be used to drive VLOGIC.

components recommended by Analog Devices listed in Table 10. Table 11. DC-to-DC Converter Mode vs. Settling Time internal switch if the inductor current reaches that limit. capability across all operating modes. of the capacitor must also be considered for a given application. parallel with a 0.1 μF (0402 size) capacitor is recommended. exhibit a large sensitivity to dc bias voltages and temperature. register and is disabled by default. main die, and the 3-wire interface slave is on the dc-to-dc die. to the DCDC_CONFIG1 and DCDC_CONFIG2 registers. read of the internal status register of the dc-to-dc die is required. this transfer time reduces to 30 µs.

die. An automatic status read of the dc-to-dc die is performed. write to either DCDC_CONFIGx register resets this bit to 0. ERR_3WI bit in the DIGITAL_DIAG_RESULTS register is set. RESULTS register is also set. both connections using 1 kΩ resistors. Figure 78. Voltage Output capacitive loads up to 10 nF can be driven. ANALOG_DIAG_RESULTS register is set. also set and is located in the ANALOG_DIAG_RESULTS register.

an 8-bit cyclic redundancy check (CRC-8) enabled by default. frame is still accepted but the last eight bits are ignored. Table 12. Writing to a Register (CRC Enabled) are sent to the ADFS5758 before taking SYNC high. to clear register (see the Sticky Diagnostic Results Bits section). return high (assuming that there are no other active faults). can decide whether the SPI CRC error affects the FAULT pin. transmission and receipt of data packets. Figure 80. CRC Timing (Assume LDAC = 0) in the DIGITAL_DIAG_RESULTS register.

• Two-stage readback mode
• Autostatus readback mode
• Shared SYNC autostatus readback mode
• Echo mode The two stage readback consists of a write to a dedicated register, TWO_STAGE_READBACK_SELECT, to select the register location to be read back. This write is followed by a no operation (NOP) command, during which the contents of the selected register are available on SDO.

Table 13. SDO Contents for Read Operation

Table 15. Offset Register Adjustment D is the code loaded to the DAC_INPUT register. M is the code in the USER_GAIN register (default code = 216 − 1). C is the code in the USER_OFFSET register (default code = 215). OFFSET register, the DAC output is not automatically updated. calibration was performed and not the result of the calibration.

• If a write is performed to the DAC_INPUT register with the hardware LDAC pin tied low, the DAC_OUTPUT register is updated on the rising edge of SYNC (subject to the timing specifications in Table 2.
• If the hardware LDAC pin is high and a write to the DAC_INPUT register occurs, the DAC_OUTPUT register does not update until a software LDAC instruction is issued or the hardware LDAC pin is pulsed low.
• If a WDT timeout occurs with the CLEAR_ON_WDT_FAIL bit set, the CLEAR_CODE register contents are loaded to the DAC_OUTPUT register.
• If the slew rate control feature is enabled, the DAC_OUTPUT register contains the dynamic value of the DAC as it slews between values. Note that, while a WDT fault is active, all writes to the DAC_ INPUT register as well as hardware or software LDAC events are ignored. If the CLEAR_ON_WDT_FAIL bit was set, such that the output was set to the clear code, when the WDT fault flag is cleared, the DAC_INPUT register must be written to before an update to the DAC_OUTPUT register occurs, that is, performing a software or hardware LDAC only reloads the DAC with the clear code. As described in the Echo Mode section, after configuring the DAC range (via the DAC_CONFIG register), a write to the DAC_INPUT register must occur, even if the contents of the DAC_INPUT register are not changing from their current value. Note also that the GP_CONFIG2 register contains a bit to enable a global software LDAC mode, whereby the ADFS5758 address bits of the SW_LDAC command are ignored, thus enabling multiple ADFS5758 devices to be simultaneously updated using a single SW_LDAC command. This is a useful feature if the hardware LDAC pin is not being used in a system containing multiple ADFS5758 devices.

Rev. 0 | Page 42 of 75 USE OF KEY CODES The use of key codes (via the key register) allows direct access to functions while keeping the user configuration register space locked as read only. This functionality is contained within one register and allows multiple commands (see the Key Register section for full details).

• Initiate calibration memory refresh
• Lock and unlock the user configuration register space.
• Initiate a software reset.
• Initiate a single ADC conversion.
• Watchdog timer reset keys.
• Recalculation of the background CRC diagnostic feature. As well as enabling device access while the user configuration register space is locked, using specific keys for initiating actions such as a calibration memory refresh or a device reset provides extra system robustness because it reduces the probability of either of these tasks being initiated in error. SOFTWARE RESET A software reset requires two consecutive writes of 0x15FA and 0xAF51 to the key register. A device reset can be initiated via the hardware RESET pin, the software reset keys, or automatically after a WDT timeout (if configured to do so). The RESET_ OCCURRED bit in the DIGITAL_DIAG_RESULTS register is set whenever the device is reset. This bit defaults to 1 on power- up. Both of the diagnostic results registers implement a write 1 to clear feature. That is, a 1 must be written to this bit to clear it (see the Sticky Diagnostic Results Bits section). CALIBRATION MEMORY CRC For every calibration memory refresh cycle (which is initiated via a key code write to the key register or automatically initiated when the range bits, Bits[3:0] of the DAC_CONFIG register, are changed), an automatic CRC is calculated on the contents of the calibration memory shadow registers. The result of this CRC is compared with the factory stored reference CRC value. If the CRC values match, the read of the entire calibration memory is considered valid. If they do not match, the CAL_ MEM_CRC_ERR bit in the DIGITAL_DIAG_RESULTS register is set to 1. This feature is enabled by default and can be disabled via the CAL_MEM_CRC_EN bit in the DIGITAL_DIAG_CONFIG register. While this calibration memory refresh cycle is active, two-stage readback commands are permitted, but a write to any register (other than the TWO_STAGE_READBACK_SELECT register or the NOP register) causes the INVALID_SPI_ACCESS_ERR bit in the DIGITAL_DIAG_RESULTS register to set. As described in the Echo Mode section, a wait period of 500 µs is recommended after a calibration memory refresh cycle is initiated. BACKGROUND CRC CHECK After the device powers up, it is possible for the user to initiate a background CRC calculation of the combined calibration memory and register configuration space. Note that such a background CRC calculation is enabled only when the configuration space is locked. Any attempt to initiate a CRC calculation when the configuration space is unlocked is ignored. When the config- uration space is locked (see the Lockable User Configuration Space section), a CRC is automatically calculated in the back- ground and stored as the ideal CRC value that all subsequent background CRC calculations are compared to. The back- ground CRC calculation takes approximately 6 µs to complete. A CRC check is configured by setting the relevant bits in the DIGITAL_DIAG_CONFIG register. There are three approaches to enable such a CRC check, as follows:
• Initiate a CRC recalculation upon issuing a specific key (default).
• Enable an autocheck of the CRC to be performed on completion of any valid SPI frame.
• Enable continuous monitor mode to continually recalculate the CRC in the background when enabled. INTERNAL OSCILLATOR DIAGNOSTICS An internal frequency monitor uses the internal oscillator (MCLK) to increment a 16-bit counter at a rate of 1 kHz (MCLK/10,000). The value of the counter is available to be read in the FREQ_ MONITOR register. The user can poll this register periodically and use it both as a diagnostic tool for the internal oscillator (to monitor that the oscillator is running), and to measure the frequency. This feature is enabled by default via the FREQ_ MON_EN bit in the DIGITAL_DIAG_CONFIG register. In the event that the internal MCLK oscillator stops, the ADFS5758 sends a specific code of 0x07DEAD to the SDO line for every SPI frame. This feature is enabled by default and can be disabled by clearing the OSC_STOP_DETECT_EN bit in the GP_CONFIG1 register. Note that this feature is limited to the maximum readback timing specifications as outlined in Table 3.

to the nominal value of 3.3 V. is still present, and Logic 0 if the fault is no longer present. are included in the logical OR of the DIG_DIAG_STATUS bit. requirement to poll the ADC. overtemperature indicator trip point. be powered up and this node available to the REFIN comparator. the flag remains high even after a 1 has been written to clear it. Table 17. Comparator Supply Activation Thresholds FAULT pin is active, then the FAULT_PIN_STATUS bit is 1.

Table 18. FAULT Pin Trigger Sources

2 Although the SCLK count error cannot be masked in the FAULT_PIN_CONFIG

QUIET_EN bit (Bit 3 in the GP_CONFIG1 register). pin or FAULT_PIN_STATUS bit to be activated. ADC_IP_SELECT bits (see Table 43). Table 19 for a summary of all transfer function equations). Figure 85. IOUT Monitoring via ADC1 Pin by the ADC and the corresponding transfer function equations. Analog Devices recommends a low drift, high accuracy resistor.

Table 19. ADC Input Node Summary

00010 Reserved Reserved

00101 Reserved Reserved

00110 Reserved Reserved

01100 ADC2 pin input ADC2 (V) = (30 × D)/212 − 15

01101 Voltage on +VSENSE buffer output +VSENSE (V) = ((50 × D)/212) − 25

01110 Voltage on −VSENSE buffer output −VSENSE (V) = ((50 × D)/212) − 25

10011 Reserved Reserved

10100 INT_AVCC INT_AVCC (V) = D/212 × 10

10101 VLDO VLDO (V) = D/212 × 10

10110 VLOGIC VLOGIC (V) = D/212 × 10

11110 DC-to-dc die node, configured in the DCDC_CONFIG2 register

converting on the first channel in the sequence. is issued to enable automatic sequencing mode (see Figure 87). reconfigured, unless the desired list of nodes changes. configuration of sequencer depth and channels is stored. required without unlocking the user configuration space. Table 21. These commands are available in the ADC_CONFIG

1. Load the channels into the sequencer N times for N channels.

ADC nodes is shown in Figure 87. Table 21. Command Bits

000 Set the sequencer depth (0 to 7)

001 Load sequencer Channel N with the selected ADC input

010 Enable or disable the key sequencer

011 Enable or disable the automatic sequencer

100 Perform a single conversion on the currently selected

101 Set up single key conversion, that is, select the ADC

1. STATUS REGISTER CONTENTS CONTAINING ADC CONVERSION RESULT, CORRESPONDING

ADDRESS, AND ADC BUSY INDICATOR. Figure 88. ADC Conversion Timing Example

wide, with the last eight bits corresponding to the CRC code. depend on the register that is being addressed. Table 22. Writing to a Register Table 23. Input Register Decode ADFS5758_AD1 Slip bit. This bit must equal the inverse of Bit D22 (that is, ADFS5758_AD1). Selects which register is written to. See Table 27 for a summary of the available registers.

• Two-stage readback
• Autostatus readback
• Shared SYNC autostatus readback
• Echo mode Two-Stage Readback Mode Two-stage readback mode consists of a write to the TWO_ STAGE_READBACK_SELECT register to select the register location to be read back, followed by a NOP command. To perform a NOP command, write all zeros to Bits[D15:D0] of the NOP register. During the NOP command, the contents of the selected register are available on SDO in the format shown in Table 24. It is also possible to write a new two-stage readback command during the second frame such that the corresponding new data is available on SDO in the subsequent frame (see Figure 89). Bits[D31:D30] (or Bits[D23:D22], if SPI CRC is not enabled) = 10 are used as part of the synchronization during readback. The contents of the first write instruction (to the TWO_STAGE_READBACK_SELECT register) is shown in Table 25.

Table 24. SDO Contents for Read Operation

10 FAULT pin status Register address Data

Table 25. Reading from a Register (Using Two-Stage Readback Mode) Figure 89. Two-Stage Readback Example

details on the ADC sequencer. Table 26. SDO Contents for a Read Operation in the Status Register Figure 90. Autostatus Readback Example

Rev. 0 | Page 54 of 75 PROGRAMMING SEQUENCE TO ENABLE THE OUTPUT CORRECTLY To correctly write to and set up the device from a power-on or reset condition, use the following sequence: 1. Perform a hardware or software reset and wait 100 µs. 2. Perform a calibration memory refresh by writing 0xFCBA to the key register. Wait a minimum of 500 µs before proceeding to Step 3 to allow time for the internal calibrations to complete. As an alternative to waiting 500 µs for the refresh cycle to complete, poll the CAL_MEM_ UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register until it is 0. 3. Write 1 to Bit D13 in the DIGITAL_DIAG_RESULTS register to clear the RESET_OCCURRED flag. 4. If CLKOUT is required, configure and enable this feature via the GP_CONFIG1 register. It is important to configure this feature before enabling the dc-to-dc converter. 5. Write to the DCDC_CONFIG2 register to set the dc-to-dc current limit. Wait 300 µs to allow the 3-wire interface communication to complete. As an alternative to waiting 300 µs for the 3-wire interface communication to complete, poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 6. Write to the DCDC_CONFIG1 register to set up the dc-to-dc converter mode (thereby enabling the dc-to-dc converter). Wait 300 µs to allow the 3-wire interface communication to complete. As an alternative to waiting 300 µs to the 3-wire interface communication to complete, poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. 7. Write to the DAC_CONFIG register to set the INT_EN bit (powers up the DAC and internal (INT) amplifiers without enabling the output) and configure the output range, internal/ external R SET, and slew rate. Keep the OUT_EN bit disabled at this point. Wait 500 µs minimum before proceeding to Step 8 to allow time for the internal calibrations to complete. As an alternative to waiting 500 µs for the refresh cycle to complete, poll the CAL_MEM_ UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register until it is 0. 8. Write zero-scale DAC code to the DAC_INPUT register. If a bipolar range was selected in Step 7, a DAC code that represents a 0 mA/0 V output must be written to the DAC_INPUT register. It is important that this step be completed even if the contents of the DAC_INPUT register are not changing. 9. If LDAC functionality is being used, perform either a software or hardware LDAC command. 10. Enable the background supply monitoring voltage comparators. 11. Rewrite the same word to the DAC_CONFIG register as in Step 7 except, this time, with the OUT_EN bit enabled. Allow 1.25 ms minimum between Step 6 and Step 11; this is the time from when the dc-to-dc is enabled to when the VI OUT output is enabled. 12. Write the required DAC code to the DAC_INPUT register. 13. Write 0x4765 to the key register to lock the user configuration register space. This is an optional step. An example configuration is shown in Figure 93. Additional configuration and diagnostics including ADC configuration must be configured before Step 13. Changing and Reprogramming the Range After the output is enabled, use the following recommended steps when changing the output range. If the user configuration register space is locked, it must first be unlocked by writing to the key register before Step 2 can be performed. It can be relocked, if required, after Step 4. 1. Write to the DAC_INPUT register. Set the output to 0 mA or 0 V. 2. Write to the DAC_CONFIG register. Disable the output (OUT_EN = 0), and set the new output range. Keep the INT_EN bit set. Wait 500 µs minimum before proceeding to Step 3 to allow time for internal calibrations to complete. 3. Write Code 0x0000 (in the case of bipolar ranges write Code 0x8000) to the DAC_INPUT register. It is important that this step be completed even if the contents of the DAC_INPUT register are not changing. 4. Reload the DAC_CONFIG register word from Step 2 except, this time, set the OUT_EN bit to 1 to enable the output. 5. Write the required DAC code to the DAC_INPUT register.

1. LDAC FUNCTIONALITY IS NOT BEING USED. DEFAULT DC-TO-DC CURRENT LIMIT IS BEING USED.

Figure 93. Example Configuration to Enable the Output Correctly (CRC Disabled for Simplicity)

Table 27. Register Summary 1 Any read or write to this register flags the INVALID_SPI_ACCESS_ERR bit in the digital diagnostics register.

Write 0x0000 to Bits[D15:D0] at this address to perform a no operation (NOP) command. Bits[15:0] of this register always read back as 0x0000. Table 28. Bit Descriptions for NOP software LDAC command is written. Table 29. Bit Descriptions for DAC_INPUT fault, this register contains the clear code until the DAC is updated to another code. Table 30. Bit Descriptions for DAC_OUTPUT does not update the DAC_OUTPUT register to a new code until the DAC_INPUT register is first written to. Table 31. Bit Descriptions for CLEAR_CODE

maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy. Table 32. Bit Descriptions for USER_GAIN The 16-bit USER_OFFSET register allows the user to adjust the offset of the DAC channel by −32,768 LSBs to +32,768 LSBs in steps of 1 LSB. The USER_OFFSET register coding is straight binary. The default code is 0x8000, which results in zero offset programmed to the output. Table 33. Bit Descriptions for USER_OFFSET Table 34. Bit Descriptions for DAC_CONFIG define the rate of change of the output value.

0: select internal RSET resistor (default). 1: select external RSET resistor. 0: disable VIOUT output (default). delay before enabling the output. This delay results in a reduced output enable glitch. returns to 0. Writes to invalid range codes are ignored. 0000: 0 V to 5 V voltage range (default). 0001: 0 V to 10 V voltage range. 1000: 0 mA to 20 mA current range. 1001: 0 mA to 24 mA current range. 1010: 4 mA to 20 mA current range. 1101: −1 mA to +22 mA current range. updated via the SW_LDAC command. Bits[15:0] of this register always read back as 0x0000. Table 35. Bit Descriptions for SW_LDAC

always read back as 0x0000. All unlisted key codes are reserved. Table 36. Bit Descriptions for Key 0x896D: first of two keys to unlock the user configuration register space. 0x57AB: second of two keys to unlock the user configuration register space. 0x15FA: first of two keys to initiate a software reset. 0xAF51: second of two keys to initiate a software reset. 0x1ADC: key to initiate a single ADC conversion on the selected ADC channel. 0x0D06: first of two keys to reset the watchdog timer. 0xF00D: second of two keys to reset the watchdog timer. 0x5CEA: key to force a recalculation of the background CRC. within a given system reset cycle. Table 37. Bit Descriptions for GP_CONFIG1 00: disable; no clock is output on the CLKOUT pin (default). 10: reserved (do not select this option). 11: reserved (do not select this option).

0: output of the DAC drives the output stage directly (default). connection of a slew capacitor. becomes −300 mV to +5.7 V; the 0 V to 12 V range becomes −400 mV to 11.6 V. the FAULT pin if this bit is set. Table 38. Bit Descriptions for GP_CONFIG2 the temperature comparators are permanently enabled. 00: disable voltage comparators (default). ANALOG_DIAG_RESULTS register. assert in the ANALOG_DIAG_RESULTS register.

Rev. 0 | Page 62 of 75 Bits Bit Name Description Reset Access 11: enable voltage comparators. Note that the INT_EN bit in the DAC_ CONFIG register must be set for the REFIN buffer to be powered up and this node available to the REFIN comparator. 12 VLDO_CAP_DETECT_EN Initiates a diagnostic test to detect a missing external capacitor on the VLDO pin. Note that this bit returns to 0 once the test is complete and thus, polling this bit can be used to determine when the test is complete. 0x0 R/W 0: disable (default). 1: enable. 11 RESERVED Reserved. 0x0 R/W

10 GLOBAL_SW_LDAC When enabled, the ADFS5758 address bits are ignored when performing a

software LDAC command, enabling multiple devices to be simultaneously updated using one SW_LDAC command. 0x0 R/W 0: disable (default). 1: enable. 9 FAULT_TIMEOUT Enable reduced fault detect timeout. This bit configures the delay from when the analog block indicates a VIOUT fault has been detected to the associated change of the relevant bit in the ANALOG_DIAG_RESULTS register. This feature provides flexibility to accommodate a variety of output load values. 0x1 R/W 0: fault detect timeout = 25 ms. 1: fault detect timeout = 6.5 ms (default). [8:5] FAULT_INJ_3WI 3WI Fault Injection Enable. All unlisted codes are reserved and must not be selected. 0x0 R/W 0000: no 3WI fault injection (default). 0100: enable fault injection on 3-wire interface by forcing DCLK low.

4 DAC_LATCH_MON_

FAULT_INJ If this bit is enabled, the signal output from the DAC is changed, which triggers the DAC_LATCH_MON_ERR bit in the DIGITAL_DIAG_RESULTS register. 0x0 R/W 0: disable (default). 1: enable. 3 DUAL_CAL_FAULT_INJ If this bit is enabled, a bit is input to the internal DAC controller circuitry, which causes an error in the internal DAC calibration calculation. This causes the two calculations in the subsequent dual calibration test to disagree and flag the error via the DUAL_CAL_ERR bit in the DIGITAL_DIAG_RESULTS register. 0x0 R/W 0: disable (default). 1: enable.

2 INVERSE_DAC_CHECK_

FAULT_INJ If this bit is enabled, a bit is input to the internal DAC controller circuitry, which causes an error in the DAC inverse calculation. This causes the INVERSE_DAC_ CHECK_ERR flag to set in the DIGITAL_DIAG_RESULTS register when completing the subsequent calculation. 0x0 R/W 0: disable (default). 1: enable. 1 BKGND_CRC_FAULT_INJ If this bit is enabled, a fault is injected into one of the bits that is used to build the CRC which is checked against the ideal CRC. This is flagged by the BKGND_ CRC_ERR bit in the DIGITAL_DIAG_RESULTS register upon completion of the subsequent background CRC check. 0x0 R/W 0: disable (default). 1: enable.

0 SPI_READ_FAULT_INJ If this bit is enabled, the MSB of the SPI readback frame flips to ensure mismatch

between the read data and the read CRC bits for the subsequent SPI readback operation. This is flagged by the SPI_CRC_ERR in the DIGITAL_DIAG_RESULTS register. 0x0 R/W 0: disable (default). 1: enable.

This register is used to configure the dc-to-dc controller mode. Table 39. Bit Descriptions for DCDC_CONFIG1 00: DC-to-DC converter powered off (default). and 25.677 V (depending on the DCDC_VPROG bits, Bits[4:0]) with respect to −VSENSE. to enabling PPC current mode. regulated with respect to −VSENSE. Table 40. Bit Descriptions for DCDC_CONFIG2

21 FAULT_PIN_STATUS The FAULT_PIN_STATUS bit reflects the inverted current status of the

0: 3-wire interface not currently active. configuration registers clears this bit to 0. registers on the main die match the contents on the dc-to-dc die. 0: enable automatic read and compare cycle (default). after each 3-wire interface write.

0: deglitch time set to 1.02 ms (default). 1: deglitch time set to 128 μs. 01: internal 2.5 V supply on dc-to-dc die. 11: reserved (do not select this option). resulting response to a WDT fault (for example, clear the output or reset the device). Table 41. Bit Descriptions for WDT_CONFIG be cleared before the WDT can be restarted.

7 DOUBLE_WR_KICK_EN When this bit is set, two specific consecutive keys codes are required to kick the

0: disable (default). A single key code is required to kick the watchdog timer. 1: enable. A double key code is required to kick the watchdog timer.

the watchdog timer is monitored for early or late reset events. This register configures various digital diagnostic features of interest for a particular application. Table 42. Bit Descriptions for DIGITAL_DIAG_CONFIG 00: user controls CRC check using a key code (default). 01: CRC automatically done on completion of any valid SPI frame. 10: CRC runs continually in background. 11: CRC runs continually in background. DAC_LATCH_MON_ERR flag to be set in the DIGITAL_DIAG_RESULTS register. 5 DUAL_CAL_EN Enable internal calibration on the 16-bit user DAC code to be completed twice. 1.5 μs to 2 μs if this feature is enabled.

corresponding flag within the DIGITAL_DIAG_RESULTS register. conversion of the currently selected ADC_IP_SELECT node, or single-key conversion. Table 43. Bit Descriptions for ADC_CONFIG 001: set the channel SEQUENCE_DATA[7:5] with the ADC input, ADC_IP_SELECT[4:0]. SEQUENCE_DATA[7:5] bits. SEQUENCE_DATA[7:5] = 001: enable key sequencer. SEQUENCE_DATA[7:5] ≠001: disable key sequencer. sequencer. SEQUENCE_DATA[7:5] ≠001: disable automatic sequencer. autosequencing. SEQUENCE_DATA[7:5] bits are not applicable for this command. applicable for this command. 110: reserved (do not select this option). 111: reserved (do not select this option). issued by the SEQUENCE_COMMAND[10:8] bits.

and returns an ADC result of zero. 00000: main die temperature. 00001: dc-to-dc die temperature. 00010: reserved (do not select this option). REFIN buffer to be powered up and this node to be available to the ADC. 00100: REF2; internal 1.23 V reference voltage. 00101: reserved (do not select this option). 00110: reserved (do not select this option). 01101: voltage on +VSENSE buffer output. 01111: ADC1 pin input (0 V to 1.25 V input range). 10000: ADC1 pin input (0 V to 0.5 V input range). 10001: ADC1 pin input (0 V to 2.5 V input range). 10010: ADC1 pin input (±0.5 V input range). 10011: reserved (do not select this option). 11110: dc-to-dc die node, configured in DCDC_CONFIG2 register. This register is used to mask particular fault bits from the FAULT pin, if so desired. Table 44. Bit Descriptions for FAULT_PIN_CONFIG

15 INVALID_SPI_ACCESS_ERR If this bit is set, do not map the INVALID_SPI_ACCESS_ERR fault flag to the

readback is stored in Bits[D4:D0]. Table 45. Bit Descriptions for TWO_STAGE_READBACK_SELECT 0: two stage SPI readback mode (default). as SYNC goes low, unless the internal flag is set (that is, the previous SPI write is valid). 0x00: NOP register (default). 0x0B: DCDC_CONFIG1 register. 0x0C: DCDC_CONFIG2 register. 0x0D: reserved (do not select this option). 0x0E: reserved (do not select this option). 0x10: DIGITAL_DIAG_CONFIG register. 0x12: FAULT_PIN_CONFIG register. 0x13: TWO_STAGE_READBACK_SELECT register. 0x14: DIGITAL_DIAG_RESULTS register. 0x15: ANALOG_DIAG_RESULTS register.

0x18: FREQ_MONITOR register. corresponding enable bits in the DIGITAL_DIAG_CONFIG register are not enabled, the respective flag bits read as zero. Table 46. Bit Descriptions for DIGITAL_DIAG_RESULTS cleared after the calibration memory refresh completes. 0: calibration memory is refreshed. bit asserts if the range bits are modified in the DAC_CONFIG register. in this register, this bit is automatically cleared when slewing is complete.

9 BKGND_CRC_ERR This bit flags an error for the background CRC calculation of the combined

flags if a parity error occurs during a 3-wire read and compare transaction.

6 INVERSE_DAC_CHECK_ERR This bit flags if a fault it detected between the DAC code driven by the

digital core and an inverted copy.

5 CAL_MEM_CRC_ERR This bit flags a CRC error for the CRC calculation of the calibration memory

4 INVALID_SPI_ACCESS_ERR This bit flags if an invalid SPI access is attempted, such as writing to or

during a calibration memory refresh and does not cause this flag to set. Attempting to write to a read only register also causes this bit to assert.

3 CFG_LOCK_CHECK_ERR This bit flags if there is a write attempted on the user configuration space

CRC is enabled and 24 clocks or 32 clocks are required if SPI CRC is not enabled.

1 SLIPBIT_ERR This bit flags an SPI frame slip bit error, that is, the MSB of the SPI word is not

equal to the inverse of MSB − 1. corresponding diagnostic features are not enabled, the respective error flags are read as zero. Table 47. Bit Descriptions for ANALOG_DIAG_RESULTS the target VDPC+ voltage due to an insufficient AVDD1 voltage.

8 VLDO_CAP_ERR This bit flags an error if no capacitor present on VLDO pin following the capacitor

3 REFOUT_ERR This bit flags that the REFOUT node is outside of the comparator threshold levels

or if its short-circuit current limit occurs.

0 VLDO_ERR This bit flags that the VLDO node is outside of the comparator threshold levels or if

its short-circuit current limit occurs.

This register contains ADC data and status bits, as well as the WDT, OR'ed analog and digital diagnostics, and the FAULT pin status bits. Table 48. Bit Descriptions for Status

21 FAULT_PIN_STATU

20 DIG_DIAG_STATUS This bit represents the result of a logical OR of the contents of Bits[15:0] in the

the DIG_DIAG_STATUS bit is not set high.

19 ANA_DIAG_STATU

ANA_DIAG_STATUS bit is high. This register contains the silicon revision ID of both the main die and the dc-to-dc die. Table 49. Bit Descriptions for CHIP_ID robustness check of the internal oscillator. Table 50. Bit Descriptions for FREQ_MONITOR

from DEVICE_ID_1 is 0x38A8 and the data read back from DEVICE_ID_2 is 0x14D2. Then, the device ID is 0x14D238A8A5D2. Table 51. Bit Descriptions for DEVICE_ID_0 Table 52. Bit Descriptions for DEVICE_ID_1 Table 53. Bit Descriptions for DEVICE_ID_2 Table 54. Bit Descriptions for DEVICE_ID_3

total module power is calculated as approximately 226 mW. on the choice of component used. becomes approximately 206 mW in a short-circuit load condition. Table 55. Quiescent Current Power Calculation quiescent current power is 19.18 mW. quiescent current power is 19.18 mW.

Figure 94. Example Module Containing the ADP1031 and the ADFS5758

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

01-17-2016-ACOMPLIANT TO JEDEC STANDARDS MO-220-VHHD-5. Figure 95. 32-Lead Lead Frame Chip Scale Package [LFCSP]

2 USB interface board, EVAL-SDP-CS1Z

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