ADF9010

ADF9010 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 25

Technical content

900 MHz ISM Band

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

840 MHz to 960 MHz ISM bands

Rx baseband analog low-pass filtering and PGA Integrated RF Tx upconverter Integrated integer-N PLL and VCO Integrated Tx PA preamplifier Differential fully balanced architectures

3.3 V supply

Low power mode: <1 mA power-down current Programmable Rx LPF cutoff 330 kHz, 880 kHz, 1.76 MHz, and bypass Rx PGA gain settings: 3 dB to 24 dB in 3 dB steps Low noise BiCMOS technology 48-lead, 7 mm × 7 mm LFCSP

APPLICATIONS

900 MHz RFID readers

Unlicensed band 900 MHz applications FUNCTIONAL BLOCK DIAGRAM AGNDDGND ÷ 4 24-BIT INPUT SHIFT REGISTER PHASE FREQUENCY DETECTOR PRESCALER P/P + 1 N COUNTER N = BP + A PLL DC OFFSET CORRECTION DC OFFSET CORRECTION TxOUTP TxOUTN TxBBIP TxBBIN TxBBQP TxBBQN CP REFIN SCLK SDATA SLE AVDD DVDDVP MUXOUT RxCM R COUNTER B COUNTER A COUNTER VCM VCM RSET RxINIP RxININ RxBBIP RxBBIN RxBBQP RxBBQN RxINQP RxINQN OVF CEXT1 CEXT2 CEXT3 CEXT4 CT CE ADF9010 LOOUTP LOOUTN QUADRATURE PHASE SPLITTER CHARGE PUMP RXVDD VTUNE 07373-001 Figure 1. GENERAL DESCRIPTION The ADF9010 is a fully integrated RF Tx modulator and Rx analog baseband front end that operates in the frequency range from 840 MHz to 960 MHz. The receive path consists of a fully differential I/Q baseband PGA, low-pass filter, and general signal conditioning before connecting to an Rx ADC for baseband conversion. The Rx LPF gain ranges from 3 dB to 24 dB, programmable in 3 dB steps. The Rx LPF features four programmable modes with cutoff frequencies of 330 kHz, 880 kHz, and 1.76 MHz, or the filter can be bypassed if necessary. The transmit path consists of a fully integrated differential Tx direct I/Q upconverter with a high linearity PA driver amplifier. It converts a baseband I/Q signal to an RF carrier-based signal between 840 MHz and 960 MHz. The highly linear transmit signal path ensures low output distortion. Complete local oscillator (LO) signal generation is integrated on chip, including the integer-N synthesizer and VCO, which generate the required I and Q signals for transmit I/Q upconver- sion. The LO signal is also available at the output to drive an external RF demodulator. Control of all the on-chip registers is via a simple 3-wire serial interface. The device operates with a power supply ranging from 3.15 V to 3.45 V and can be powered down when not in use.

Rev. A | Page 2 of 25 TABLE OF CONTENTS

REVISION HISTORY

12/2017—Rev. 0 to Rev. A 8/2008—Revision 0: Initial Version

Rev. A | Page 3 of 25 SPECIFICATIONS TRANSMIT CHARACTERISTICS AVDD = DVDD = 3.3 V ± 5%, AGND = DGND = GND = 0 V , TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted. Table 1. Parameter B Version1 Unit Test Conditions/Comments Min Typ Max TRANSMIT MODULATOR CHARACTERISTICS Operating Frequency Range 840 960 MHz Range over which uncompensated sideband suppression < −30 dBc Output Power 3 dBm VIQ = 1.4 V p-p differential Output P1 dB 10 dBm Carrier Feedthrough −40 dBm Sideband Suppression −46 dBc Output IP3 24 dBm POUT = −4 dBm per tone, 10 MHz and 12 MHz baseband input frequencies used. Noise Floor −158 dBm/Hz TRANSMIT BASEBAND CHARACTERISTICS Input Impedance of Each Pin 4 kΩ typ Single-ended frequencies up to 2 MHz Input Capacitance of Each Pin 3 pF At 10 MHz Input Signal Level 1.4 V p-p Measured differentially at I or Q Common-Mode Output Level 0.6 V Tx Baseband 3 dB Bandwidth 20 MHz POWER SUPPLIES Voltage Supply 3.15 3.45 V IDD Digital IDD 5 6 mA Rx Baseband 70 80 mA Maximum gain settings Tx Modulator 140 mA Full power, baseband inputs biased at 0.5 V LO Synthesizer and VCO 140 mA + 5 dBm LO power setting selected Total IDD 360 410 mA Power-Down Rx VDD 1 mA AVDD 1 20 µA DVDD 1 20 µA LOGIC INPUTS (SERIAL INTERFACE) Input High Voltage, VINH 1.4 V 1.8 V logic compatible Input Low Voltage, VINL 0.4 V Input Current, IINH/IINL ±1 µA Input Capacitance, CIN 5 pF LOGIC OUTPUTS (MUXOUT) Output High Voltage, VOH DVDD − 0.4 V IOL = 500 µA Output Low Voltage, VOL 0.4 V IOH = 500 µA 1 Operating temperature range for the B version is −40°C to +85°C.

Rev. A | Page 4 of 25 RECEIVE BASEBAND CHARACTERISTICS AVDD = DVDD = 3.3 V ± 5%, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted. Table 2. Parameter B Version1 Unit Test Conditions/Comments Min Typ Max RECEIVE BASEBAND PGA Highest Voltage Gain 24 dB Lowest Voltage Gain 3 dB Gain Control Range 18 dB Programmable using 3-bit interface Gain Control Step 3 dB Noise Spectral Density (Referred to Input) 3.5 nV/√Hz At maximum PGA gain RECEIVE BASEBAND FILTERS 3 dB Cutoff Frequency (Mode 0) 320 kHz After filter calibration Gain Flatness 0.5 dB Typical from dc to 90 kHz Differential Group Delay 500 µs DC to 360 kHz 150 µs 170 kHz to 310 kHz Attenuation Template After filter calibration At 330 kHz Offset −3 dB At 500 kHz Offset −8 dB At 1 MHz Offset −28 dB 3 dB Cutoff Frequency (Mode 1) 880 kHz After filter calibration Gain Flatness 0.5 dB DC to 90 kHz Differential Group Delay 500 µs DC to 360 kHz 150 µs 170 kHz to 310 kHz Attenuation Template After filter calibration At 880 kHz Offset −3 dB At 2 MHz Offset −17 dB At 4 MHz Offset −38 dB 3 dB Cutoff Frequency (Mode 2) 1.76 MHz After filter calibration Gain Flatness 0.5 dB DC to 90 kHz Differential Group Delay 500 µs DC to 360 kHz 150 µs 170 kHz to 310 kHz Attenuation Template After filter calibration At 1.76 MHz Offset −3 dB At 4 MHz Offset −18 dB At 8 MHz Offset −38 dB At 16 MHz Offset −60 dB 3 dB Cutoff Frequency (Mode 3) 4 MHz After filter calibration Gain Flatness 0.5 dB DC to 90 kHz Differential Group Delay 500 µs DC to 360 kHz At 2 MHz Offset −0.5 dB At 4 MHz Offset −2 dB Input Impedance of Each Pin At 24 dB gain 250 Ω At 3 dB gain 4 kΩ Input Capacitance of Each Pin 3 pF At 10 MHz Input Signal Level 2 V p-p Measured differentially at I or Q Common-Mode Output Level 1.65 V On Rx baseband outputs Maximum Residual DC 150 mV Baseband gain 0 dB − 27 dB 1 Operating temperature range for the B version is −40°C to +85°C.

Rev. A | Page 5 of 25 INTEGER-N PLL AND VCO CHARACTERISTICS Table 3. Parameter B Version1 Unit Test Conditions/Comments Min Typ Max VCO OPERATING FREQUENCY 3360 3840 MHz LO OUTPUT CHARACTERISTICS Measured at LO output (900 MHz) VCO Control Voltage Sensitivity 8 MHz/V 3.6 GHz VCO frequency (taking into account divide by 4) Harmonic Content (Second) −27 dBc Harmonic Content (Third) −14 dBc Frequency Pushing (Open Loop) 1.2 MHz/V Frequency Pulling (Open Loop) 10 Hz Into 2.00 VSWR load. Lock Time 1000 µs 10 kHz loop bandwidth Output Power −4 to +5 dBm LO outputs combined in a 1:1 transformer; programmable in 3 dB steps Output Power Variation ±3 dB NOISE CHARACTERISTICS Measured at LO output (900 MHz) VCO Phase Noise Performance2 At 100 kHz Offset −120 dBc/Hz At 1 MHz Offset −141 dBc/Hz At 10 MHz Offset −154 dBc/Hz In-Band Phase Noise3, 4 −96 dBc/Hz at 1 kHz offset from carrier Normalized In-Band Phase Noise Floor3, 4 −220 dBc/Hz Spurious Frequencies at Output Channel Spacing −70 dBc 900 MHz offset, 1 MHz PFD frequency, 250 kHz channel spacing; loop bandwidth = 7.5 kHz PHASE DETECTOR Phase Detector Frequency5 8 MHz Maximum Allowable Prescaler Output Frequency6 325 MHz CHARGE PUMP ICP Sink/Source With RSET = 4.7 kΩ High Value 5 mA Low Value 0.625 mA RSET Range 2.7 10 kΩ ICP Three-State Leakage Current 0.2 nA Sink and Source Current Matching 2 % 1.25 V ≤ VCP ≤ 2.5 V ICP vs. VCP 1.5 % 1.25 V ≤ VCP ≤ 2.5 V ICP vs. Temperature 2 % VCP = 2.0 V PLL REFERENCE Reference Clock Frequency 10 104 MHz Reference Clock Sensitivity 0.7 PLL VDD V p-p Reference Input Capacitance 5 pF REFIN Input Current ±100 µA 1 Operating temperature range for the B version is −40°C to +85°C. 2 The noise of the VCO is measured in open-loop conditions. 3 The phase noise is measured with the EVAL-ADF9010EBZ1 evaluation board and the Agilent E5052A spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 4 fREFIN = 10 MHz; fPFD = 1000 kHz; N = 3600; loop BW = 25 kHz. 5 Guaranteed by design. Sample tested to ensure compliance. 6 This is the maximum operating frequency of the CMOS counters. The prescaler value must be chosen to ensure that the RF input is divided down to a frequency that is less than this value.

AVDD = DVDD = 3.3 V ± 5%; AGND = DGND = GND = 0 V; TA = 25°C, guaranteed by design, but not production tested. Figure 2. Write Timing Diagram

Rev. A | Page 7 of 25 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 5. Parameter Rating DVDD, RxVDD, AVDD to GND1 −0.3 V to +3.9 V RxVDD, AVDD to DVDD −0.3 V to +0.3 V VP to GND1 −0.3 V to +5.5 V Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND1 −0.3 V to AVDD + 0.3 V Charge Pump Voltage to GND1 −0.3 V to VP to GND1 REFIN, LOEXTP, LOEXTN to GND1 −0.3 V to VDD + 0.3 V LOEXTP to LOEXTN ±320 mV Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C LCSP θJA Thermal Impedance 26°C/W Reflow Soldering Peak Temperature 260°C/W Time at Peak Temperature 40 sec 1 GND = AGND = DGND = 0 V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high-performance RF integrated circuit with an ESD rating of <0.5 kV and is ESD sensitive. Proper precautions must be taken for handling and assembly. TRANSISTOR COUNT The ADF9010 transistor count is 40,454 (CMOS) and 994 (bipolar). ESD CAUTION

1. NC = NO CONNECT. THIS PIN IS CONNECTED INTERNALLY. DO NOT CONNECT ON PCB.
2. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

Figure 3. Pin Configuration Table 6. Pin Function Descriptions 1, 2 RxINIP, RxININ Input/Complementary In-Phase Input to the Receive Filter Stage. 6, 12, 18, 24, 44 AGND Analog Ground. This is the ground return path of analog circuitry. oscillator, or it must be ac-coupled. ground plane must be placed as close as possible to this pin. DVDD must be the same value as AVDD. DVDD. If an external VCO is used, the voltage can be AVDD < VP < 5.5 V. ambient temperature, the voltage is 2.0 V.

Rev. A | Page 9 of 25 Pin No. Mnemonic Description 17 VTUNE Control Input to the VCO. This input determines the VCO frequency and is derived from filtering the CP output. 19, 20 LOEXTP, LOEXTN Single-Ended External VCO Input of 50 Ω. This is used if the ADF9010 utilizes an optional external VCO. These pins are internally dc-biased and must be ac-coupled. AC-couple LOEXTN to ground with 100 pF and ac-couple the VCO signal with 100 pF through LOEXTP. 22, 23 TxOUTP, T xOUTN Buffered Tx Output. These pins contain the Tx output signal, which can be combined in a balun for best results. 25, 26 TxBBQN, TxBBQP Baseband Quadrature Phase Input/Complementary Input to the Transmit Modulator. 27, 28 TxBBI P, T xBBIN Baseband In-Phase Input/Complementary to the Transmit Modulator. 30 RSET Connecting a resistor between this pin and AGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is ICPMAX = 25.5/RSET where: RSET is 5.1 kΩ. ICPMAX is 5 mA. 31 CEXT4 A capacitor connected to this pin is used to roll off noise from the VCO. It must be decoupled to AGND with a value of 10 nF. 32 CEXT3 A capacitor connected to this pin is used to roll off noise from the VCO. It must be decoupled to AGND with a value of 10 nF. 33, 34 RxBBQN, RxBBQP Output/Complementary Filtered Quadrature Signals from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip. 35, 36 RxBBI P, R xBBIN Output/Complementary Filtered In-Phase from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip. 38 CE Chip Enable. A Logic 0 on this pin powers down the device. A Logic 1 on this pin enables the device depending on the status of the power-down bits. 39 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the SCLK rising edge. This is a high impedance CMOS input. 40 SDATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. 41 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into one of the four latches; the latch uses the control bits. 42 MUXOUT This multiplexer output allows either the PLL lock detect, the scaled VCO frequency, or the scaled PLL reference frequency to be accessed externally. 43 OVF A rising edge on this pin drops the gain of the Rx path by 6 dB. This is used to rapidly drop the gain if the ADC detects an overload. 45 NC No Connect. This pin is connected internally. Do not connect on printed circuit board (PCB). 47, 48 RxINQ P, R xINQN Input/Complementary Quadrature Input to the Receive Filter Stage. EPAD Exposed Pad. The exposed pad must be connected to AGND.

0 DISABLED

1 ENABLED

1 ENABLED F3

0 NORMAL

1 THREE-STATE

0 NEGATIVE

1 POSITIVE

1 COUNTERS HELD

Figure 22. Control Latch

1 X X ALL OFF

Figure 23. Tx Latch

Figure 24. Rx Calibration Latch

0 USE THE PROGRAMMED CHARGE PUMP

1 USE THE MAXIMUM CHARGE PUMP CURRENT

N = BP + A, P IS THE PRESCALER VALUE SET IN THE FUNCTION LATCH. ADJACENT VALUES OF (N × FREF) AT THE OUTPUT, NMIN IS (P2 – P). 0 VCO FEEDBACK TO N DIVIDER. 1 MUX FEEDBACK TO N DIVIDER. Figure 25. LO Latch

00 L O W

Figure 26. Rx Latch

Rev. A | Page 22 of 25 Rx Calibration Divider Bit RC6 to Bit RC1 program a 6-bit divider, which outputs a divided REFIN signal to assist calibration of the cutoff frequency, fC, of the Rx filters. The calibration circuit uses this divided down PLL reference frequency to ensure an accurate cutoff frequency in the Rx filter. Choose the divider value to ensure that the frequency of the divided down signal is exactly 2 MHz, that is, if a 32 MHz crystal is used as the PLL REFIN frequency, then a value of 16 is programmed to the counter to ensure accurate calibration. High-Pass Filter Boost Timeout Counter In most applications of the ADF9010, a high-pass filter is placed between the demodulator outputs and the ADF9010 Rx inputs. The capacitors used in these filters may require a long charge up time, and to address this, a filter boost function exists that charges up the capacitor to ~1.6 V . The duration for this boost is set by the product of the period of the Rx calibration signal, (REFIN divided by the Rx calibration divider) and the 6-bit value programmed to these registers. This value can be as large as 63. Programming a value of 000000 leads to the calibration time being manually set by the HPF boost in the Rx latch. It becomes necessary in such cases to program this bit to 0 for normal Rx operation. LO LATCH Program the LO latch with (C2, C1) = (1, 0). Figure 25 shows the input data format for programming the LO latch. Prescaler Bit P2 and Bit P1 in the LO latch set the prescaler values. CP Gain Setting G1 to 0 chooses the programmed charge pump current setting from the control latch. Setting this bit to 1 chooses the maximum possible setting. N Div Mux Setting M1 to 0 feeds the VCO signals back to the N divider. Setting this bit to 1 allows the mux signal to be fed back instead. B Counter Latch Bit B13 to Bit B1 program the B counter. The divide range is 3 (00 … 0011) to 8191 (11 … 111). A Counter Latch Bit A5 to Bit A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111). Rx LATCH Program the Rx latch with (C2, C1) = (1, 1). Figure 26 shows the input data format for programming the LO latch. High-Pass Filter Boost This function is enabled by setting the HP bit to 1. A 0 disables this function. This is used to reduce settling time on the high- pass filter from the Rx demodulator. This is usually used in conjunction with the high-pass filter boost counter (See the RX Calibration Latch section). Rx Filter Bandwidth The Rx filter bandwidth is programmable and is controlled by Bit BW2 and Bit BW1. See the truth table in Figure 26. Rx Filter Gain Steps Bit G3 to Bit G1 set the gain of the Rx filters. The gain can vary from 3 dB to 24 dB in 3 dB steps. See the truth table in Figure 26. INITIALIZATION The correct initialization sequence for the ADF9010 is as follows: 1. Power-down all blocks: Tx, Rx, PLL, and VCO. Set the Tx output power off control latch to (1, 1). Set the LO phase select off (P1, P2, P3) in Tx latch to (1, 1, 1). 2. Program the R1 latch with the desired R counter and Tx values. 3. Program R5 with Rx calibration data for frequency calibration and high-pass filter boost. 4. Program R0 to power up all LO and Tx/Rx blocks. 5. Program R2 to encode correct LO frequency. 6. Program R3 to power up Rx filter. INTERFACING The ADF9010 has a simple SPI®-compatible interface for writing to the device. SCLK, SDATA, and SLE control the data transfer. See Figure 2 for the timing diagram. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 µs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds.

Rev. A | Page 24 of 25 LO AND Tx OUTPUT MATCHING The LO and Tx output stages are each connected to the collectors of an NPN differential pair driven by buffered outputs from the VCO or mixer outputs, respectively. The recommended matching for each of these circuits consists of a 7.5 nH shunt inductor to VDD, a 100 pF series capacitor, and in the case of the Tx output a 50:100 balun to combine the Tx outputs. The Anaren BD0810J50100A00 is ideally suited to this task. PCB DESIGN GUIDELINES The lands on the chip scale package (CP-48-4) are rectangular. The printed circuit board pad for these must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land must be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. T he thermal pad on the printed circuit board must be at least as large as this exposed pad. On the printed circuit board, there must be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they must be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz. copper to plug the via. The user must connect the printed circuit board thermal pad to AGND.

Rev. A | Page 25 of 25 OUTLINE DIMENSIONS 0.45 0.40 0.35

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4 0.50 BSC BOTTOM VIEWTOP VIEW PIN 1 INDICATOR 1324 0.80 0.75 0.70

0.05 MAX

0.02 NOM

0.203 REF

0.08 0.30 0.23 0.18 02-22-2017-B 7.10 7.00 SQ 6.90

5.50 REF

5.20 5.10 SQ 5.00 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) DETAIL A (JEDEC 95) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Fig ure 29. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-4) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADF9010BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP) CP-48-4 ADF9010BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP) CP-48-4 ADF9010BCPZ-RL7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP) CP-48-4 EVAL-ADF9010EBZ1 Evaluation Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07373-0-12/17(A)