ADF7242

ADF7242 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 108

Technical content

Low Power IEEE 802.15.4/Proprietary GFSK/FSK Zero-IF 2.4 GHz Transceiver IC ADF7242 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Frequency range (global ISM band) 2400 MHz to 2483.5 MHz Programmable data rates and modulation IEEE 802.15.4-2006-compatible (250 kbps) GFSK/FSK/GMSK/MSK modulation 50 kbps to 2000 kbps data rates Low power consumption 19 mA (typical) in receive mode 21.5 mA (typical) in transmit mode (P O = 3 dBm) 1.7 μA, 32 kHz crystal oscillator wake-up mode High sensitivity (IEEE 802.15.4-2006) −95 dBm at 250 kbps High sensitivity (0.1% BER) −96 dBm at 62.5 kbps (GFSK) −93 dBm at 500 kbps (GFSK) −90 dBm at 1 Mbps (GFSK) −87.5 dBm at 2 Mbps (GFSK) Programmable output power −20 dBm to +4.8 dBm in 2 dB steps Integrated voltage regulators 1.8 V to 3.6 V input voltage range Excellent receiver selectivity and blocking resilience Zero-IF architecture Complies with EN300 440 Class 2, EN300 328, FCC CFR47 Part 15, ARIB STD-T66 Digital RSSI measurement Fast automatic VCO calibration Automatic RF synthesizer bandwidth optimization On-chip low power processor performs Radio control Packet management Packet management support Insertion/detection of preamble/SWD/CRC/address IEEEE 802.15.4-2006 frame filtering IEEEE 802.15.4-2006 CSMA/CA unslotted modes Flexible 256-byte transmit/receive data buffer IEEEE 802.15.4-2006 and GFSK/FSK SPORT modes Fast settling automatic frequency control Flexible multiple RF port interface External PA/LNA support hardware Switched antenna diversity support Wake-up timer Very few external components Integrated PLL loop filter, receive/transmit switch, battery monitor, temperature sensor, 32 kHz RC and crystal oscillators Flexible SPI control interface with block read/write access Small form factor 5 mm × 5 mm 32-lead LFCSP package

APPLICATIONS

Automatic meter reading/smart metering Industrial wireless control Healthcare Wireless audio/video Consumer electronics ZigBee FUNCTIONAL BLOCK DIAGRAM DAC DAC ADC LNA1 ADC LNA2 PA 4kB PROGRAM ROM 2kB PROGRAM RAM 256-BYTE PACKET RAM 64-BYTE BBRAM 256-BYTE MCR GPIO SPORT IRQ 8-BIT PROCESSOR RADIO CONTROLLER PACKET MANAGER FSK DEMOD DSSS DEMOD AGC OCL AFC CDR SPIWAKE-UP CTRL GAUSSIAN FILTER PRE-EMPHASIS FILTER FRACTIONAL-N RF SYNTHESIZER LDO × 4 BIAS BATTERY MONITOR TEMPERATURE SENSOR 26MHz OSC 32kHz RC OSC 32kHz XTAL OSC ADF7242 08912-001 Figure 1

Rev. 0 | Page 2 of 108 TABLE OF CONTENTS IEEE 802.15.4 Frame Filtering, Automatic Acknowledge, and Configuration Values Common to IEEE 802.15.4 and Configuration Values for GFSK/FSK Packet and SPORT Configuration Values for IEEE 802.15.4-2006 Packet and

Rev. 0 | Page 3 of 108

REVISION HISTORY

7/10—Revision 0: Initial Version

Rev. 0 | Page 4 of 108 GENERAL DESCRIPTION The ADF7242 is a highly integrated, low power, and high perfor- mance transceiver for operation in the global 2.4 GHz ISM band. It is designed with emphasis on flexibility, robustness, ease of use, and low current consumption. The IC supports the IEEE 802.15.4- 2006 2.4 GHz PHY requirements as well as proprietary GFSK/ FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. With a minimum number of external compo- nents, it achieves compliance with the FCC CFR47 Part 15, ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328 (FHSS, DR > 250 kbps), and ARIB STD T-66 standards. The ADF7242 complies with the IEEE 802.15.4-2006 2.4 GHz PHY requirements with a fixed data rate of 250 kbps and DSSS- OQPSK modulation. With its support of GFSK/FSK/GMSK/MSK modulation schemes, the IC can operate over a wide range of data rates from 50 kbps to 2 Mbps and is, therefore, equally suitable for proprietary applications in the areas of smart metering, industrial control, home and building automation, and consumer electronics. In addition, the agile frequency synthesizer of the ADF7242, together with short turnaround times, facilitates the implementation of FHSS systems. The transmitter path of the ADF7242 is based on a direct closed-loop VCO modulation scheme using a low noise fractional-N RF frequency synthesizer. The automatically calibrated VCO operates at twice the fundamental frequency to reduce spurious emissions and avoid PA pulling effects. The bandwidth of the RF frequency synthesizer is automatically optimized for transmit and receive operations to achieve optimum phase noise, modulation quality, and synthesizer settling time performance. The transmitter output power is programmable from −20 dBm to +4 dBm with automatic PA ramping to meet transient spurious specifications. An integrated biasing and control circuit is available in the IC to significantly simplify the interface to external PAs. The receive path is based on a zero-IF architecture enabling very high blocking resilience and selectivity performance, which are critical performance metrics in interference dominated environ- ments such as the 2.4 GHz band. In addition, the architecture does not suffer from any degradation of blocker rejection in the image channel, which is typically found in low IF receivers. In GFSK/FSK modes, the receiver features a high speed automatic frequency control (AFC) loop, which allows the frequency synthesizer to find and correct any frequency errors in the received packet. The IC can operate with a supply voltage between 1.8 V and 3.6 V with very low power consumption in receive and transmit modes while maintaining its excellent RF performance, making it espe- cially suitable for battery-powered systems. The ADF7242 features a flexible dual-port RF interface that can be used with an external LNA and/or PA in addition to support- ing switched antenna diversity. The ADF7242 incorporates a very low power custom 8-bit processor that supports a number of transceiver management functions. These functions are handled by the two main mod- ules of the processor; the radio controller and the packet manager. The radio controller manages the state of the IC in various operating modes and configurations. The host MCU can use single byte commands to interface to the radio controller. The packet manager is highly flexible and supports various packet formats. In transmit mode, the packet manager can be confi- gured to add preamble, sync, and CRC words to the payload data stored in the on-chip packet RAM. In receive mode, the packet manager can detect and generate an interrupt to the MCU upon receiving valid sync or CRC words, and store the received data payload in the packet RAM. A total of 256 bytes of transmit and receive packet RAM space is provided to decouple the over-the-air data rate from the host MCU processing speed. Thus, the ADF7242 packet manager eases the processing burden on the host MCU and saves the overall system power consumption. In addition, for applications that require data streaming, a synchronous bidirectional serial port (SPORT) provides bit- level input/output data, and has been designed to directly inter- face to a wide range of DSPs, such as ADSP-21xx, SHARC®, TigerSHARC®, and Blackfin®. The SPORT interface can option- ally be used for GFSK/FSK as well as IEEE 802.15.4-2006 modes. The processor also permits the download and execution of a set of firmware modules, which include IEEE 802.15.4 automatic modes, such as node address filtering, as well as unslotted CSMA/CA. Execution code for these firmware modules is available from Analog Devices, Inc. T o further optimize the system power consumption, the ADF7242 features an integrated low power 32 kHz RC wake-up oscillator, which is calibrated from the 26 MHz crystal oscillator while the transceiver is active. Alternatively, an integrated 32 kHz crystal oscillator can be used as a wake-up timer for applications requiring very accurate wake-up timing. A battery backed-up RAM (BBRAM) is available on the IC where IEEE 802.15.4- 2006 network node addresses can be retained when the IC is in the sleep state. The ADF7242 also features a very flexible interrupt controller, which provides MAC-level and PHY-level interrupts to the host MCU. The IC is equipped with a SPI interface, which allows burst-mode data transfer for high data throughput efficiency. The IC also integrates a temperature sensor with digital read- back and a battery monitor.

Figure 2. Detailed Functional Block Diagram

Rev. 0 | Page 6 of 108 SPECIFICATIONS VDD_BAT = 1.8 V to 3.6 V , GND = 0 V , TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD_BAT = 3.6 V , TA = 25°C, fCHANNEL = 2450 MHz. All measurements are performed using the ADF7242 reference design, RFIO2 port, unless otherwise noted. GENERAL SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions GENERAL PARAMETERS Voltage Supply Range VDD_BAT Input 1.8 3.6 V Frequency Range 2400 2483.5 MHz Operating Temperature Range −40 +85 °C Data Rate GFSK/FSK Mode 50 2000 kbps IEEE 802.15.4-2006 Mode 250 kbps Resolution 100 bps Applies to FSK modes only RF FREQUENCY SYNTHESIZER SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions CHANNEL FREQUENCY RESOLUTION 10 kHz Applies to GFSK/FSK modes PHASE ERROR 3 Degrees Receive mode; any data rate, IEEE 802.15.4-2006 or GFSK/FSK mode; integration bandwidth from 10 kHz to 400 kHz 1.5 Degrees Transmit mode; IEEE 802.15.4-2006, 2 Mbps to 290 kbps, GFSK/FSK/GMSK/MSK mode; integration bandwidth from 10 kHz to 1800 kHz 2 Degrees Transmit mode; 289.9 kbps to 184 kbps GFSK/FSK/GMSK/MSK mode; integration bandwidth from 10 kHz to 800 kHz 2.5 Degrees Transmit mode; 183.9 kbps to 50 kbps GFSK/FSK/GMSK/MSK mode; integration bandwidth from 10 kHz to 500 kHz VCO CALIBRATION TIME 52 μs Applies to all modes SYNTHESIZER SETTLING TIME Frequency synthesizer settled to <±5 ppm of the target frequency within this time following a VCO calibration 53 μs Receive mode; any data rate, IEEE 802.15.4-2006 or GFSK/FSK mode 80 μs Transmit mode; IEEE 802.15.4-2006, 2 Mbps to 289.6 kbps GFSK/FSK mode 39 μs Transmit mode; 289.7 kbps to 184 kbps GFSK/FSK mode 35 μs Transmit mode; 183.9 kbps to 50 kbps GFSK/FSK mode PHASE NOISE Receive mode; any data rate, IEEE 802.15.4-2006 or GFSK/FSK mode −135 dBc/Hz 10 MHz frequency offset −145 dBc/Hz ≥50 MHz frequency offset REFERENCE AND CLOCK-RELATED SPURIOUS 70 dBc Receive mode; IEEE 802.15.4-2006 or GFSK/FSK mode; f CHANNEL = 2405 MHz, 2450 MHz, and 2480 MHz

Rev. 0 | Page 7 of 108 Parameter Min Typ Max Unit Test Conditions INTEGER BOUNDARY SPURS 60 dBc Receive mode; IEEE 802.15.4-2006 or GFSK/FSK mode; measured at 400 kHz offset from fCHANNEL =

2405 MHz, 2418 MHz, 2431 MHz, 2444 MHz,

2457 MHz, 2470 MHz

Crystal Frequency 26 MHz Parallel load resonant crystal Maximum Parallel Load Capacitance 18 pF Minimum Parallel Load Capacitance 7 pF Maximum Crystal ESR 365.3 Ω Guarantees maximum crystal frequency error of 0.2 ppm; 33 pF on XOSC26P and XOSC26N Sleep-to-Idle Wake-Up Time 300 μs 15 pF load on XOSC26N and XOSC26P TRANSMITTER SPECIFICATIONS Table 3. Parameter Min Typ Max Unit Test Conditions GENERAL TRANSMITTER SPECIFICATIONS Maximum Transmit Power 3 dBm Minimum Transmit Power −25 dBm Maximum Transmit Power (High Power Mode) 4.8 dBm Refer to Power Amplifier section for details on how to enable this mode Minimum Transmit Power(High Power Mode) −22 dBm Transmit Power Variation 2 dB Transmit power = 3 dBm, fCHANNEL = 2400 MHz to 2483.5 MHz, TA = −40°C to +85°C, VDD_BAT = 1.8 V to 3.6 V Transmit Power Control Resolution 2 dB Transmit power = 3dBm Optimum PA Matching Impedance 43.7 + 35.2j Ω For maximum transmit power = 3 dBm Harmonics and Spurious Emissions Compliance with ETSI EN 300 440

25 MHz to 30 MHz −36 dBm Unmodulated carrier, 10 kHz RBW1

30 MHz to 1 GHz −36 dBm Unmodulated carrier, 100 kHz RBW1

47 MHz to 74 MHz, 87.5 MHz to

118 MHz, 174 MHz to 230 MHz,

470 MHz to 862 MHz

−54 dBm Unmodulated carrier, 100 kHz RBW1 Otherwise Above 1 GHz −30 dBm Unmodulated carrier, 1 MHz RBW1 Compliance with ETSI EN 300 328

1800 MHz to 1900 MHz −47 dBm Unmodulated carrier

5150 MHz to 5300 MHz −97 dBm/Hz

Compliance with FCC CFR47, Part15 4.5 GHz to 5.15 GHz −41 dBm 1 MHz RBW1 7.25 GHz to 7.75 GHz −41 dBm 1 MHz RBW1 TRANSMIT PATH IEEE 802.15.4-2006 MODE Transmit EVM 2 % Measured using Rohde & Schwarz FSU vector analyzer with Zigbee™ option Transmit EVM Variation 1 % fCHANNEL = 2405 MHz to 2480 MHz, TA= −40°C to +85°C, VDD_BAT = 1.8 V to 3.6 V Transmit PSD Mask −56 dBm RBW = 100 kHz; |f – fCHANNEL| > 3.5 MHz Transmit 20 dB Bandwidth 2252 MHz TRANSMIT PATH GFSK/FSK MODE Frequency Deviation Resolution 10 kHz Gaussian Filter BT 0.5 Gaussian filter available for 2000 kbps, 1000 kbps, 500 kbps, 250 kbps, 125 kbps and 62.5 kbps only

Rev. 0 | Page 8 of 108 Parameter Min Typ Max Unit Test Conditions Transmit Modulation Phase Error 7 Degrees 2 Mbps (fDEV = ±500 kHz) GFSK SPORT mode, transmitter output power = 3 dBm

6.5 Degrees 1 Mbps (fDEV = ±250 kHz) GFSK SPORT mode,

transmitter output power = 3 dBm

4.5 Degrees 500 kbps (fDEV = ±250 kHz) GFSK SPORT mode,

transmitter output power = 3 dBm

6 Degrees 250 kbps (fDEV = ±130 kHz) GFSK SPORT mode,

transmitter output power = 3 dBm

4 Degrees 125 kbps (fDEV = ±60 kHz) FSK SPORT mode,

transmitter output power = 3 dBm Transmit Modulation Error Rate (MER) 24 dB 2 Mbps GFSK SPORT mode, transmitter output power = 3dBm; measured as the standard deviation from ±500 kHz frequency deviation 24 dB 1 Mbps GFSK SPORT mode, transmitter output power = 3 dBm; measured as the standard deviation from ±250 kHz frequency deviation 24 dB 500 kbps GFSK SPORT mode, transmitter output power = 3dBm; measured as the standard deviation from ±250 kHz frequency deviation 24 dB 250 kbps GFSK SPORT mode, transmitter output power = 3 dBm; measured as the standard deviation from ±130 kHz frequency deviation 22 dB 125 kbps FSK SPORT mode, transmitter output power = 3 dBm; measured as the standard deviation from ±60 kHz frequency deviation Transmit 20 dB Bandwidth

2 Mbps GFSK SPORT Mode 2520 kHz 2 Mbps (fDEV = ±500 kHz) GFSK SPORT mode

1 Mbps GFSK SPORT Mode 1250 kHz 1 Mbps (fDEV = ±250 kHz) GFSK SPORT mode

500 kbps GFSK SPORT Mode 985 kHz 500 kbps (fDEV = ±250 kHz) GFSK SPORT mode 250 kbps GFSK SPORT Mode 520 kHz 250 kbps (fDEV = ±130 kHz) GFSK SPORT mode 125 kbps GFSK SPORT Mode 302 kHz 125 kbps (fDEV = ±60 kHz) FSK SPORT mode 62.5 kbps FSK SPORT Mode 226 kHz 62.5 kbps (fDEV = ±60 kHz) FSK SPORT mode Transmit Adjacent Channel Power ±First Channel −53.5 dBm 2 Mbps GFSK SPORT mode, 5 MHz channel spacing ±Second Channel −54.5 dBm 2.2 MHz channel bandwidth, transmitter output power = 3 dBm ±First Channel −27 dBm 250 kbps FSK SPORT mode, 300 kHz channel spacing ±Second Channel −51.5 dBm 250 kHz channel bandwidth, transmitter output power = 3 dBm 1 RBW = resolution bandwidth. RECEIVER SPECIFICATIONS Table 4. Parameter Min Typ Max Unit Test Conditions GENERAL RECEIVER SPECIFICATIONS RF Front-End LNA and Mixer IIP3 −13.6 dBm At maximum gain, fBLOCKER1 = 5 MHz, fBLOCKER2 = 10.1 MHz, PRF,IN = −35 dBm −12.6 dBm At maximum gain, fBLOCKER1 = 20 MHz, fBLOCKER2 = 40.1 MHz, PRF,IN = −35 dBm −10.5 dBm At maximum gain, fBLOCKER1 = 40 MHz, fBLOCKER2 = 80.1 MHz, PRF,IN = −35 dBm

Rev. 0 | Page 9 of 108 Parameter Min Typ Max Unit Test Conditions RF Front-End LNA and Mixer IIP2 24.7 dBm At maximum gain, fBLOCKER1 = 5 MHz, fBLOCKER2 = 5.5 MHz, PRF,IN = −50 dBm RF Front-End LNA and Mixer 1 dB Compression Point −20.5 dBm At maximum gain Receiver LO Level at RFIO2 Port −100 dBm IEEE 802.15.4 packet mode LNA Input Impedance at RFIO1 Port 50.2 − 52.2j Ω Measured in RX state LNA Input Impedance at RFIO2 Port 74.3 − 10.7j Ω Measured in RX state Receive Spurious Emissions Compliant with EN 300 440

30 MHz to 1000 MHz −57 dBm

1 GHz to 12.75 GHz −47 dBm RECEIVE PATH IEEE 802.15.4-2006 MODE Sensitivity (Prf,in,min, 802154) −95 dBm 1% PER with PSDU length of 20 bytes according to the IEEE 802.15.4-2006 standard Saturation Level −15 dBm 1% PER with PSDU length of 20 bytes CW Blocker Rejection ±5 MHz 55 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±10 MHz 60 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±20 MHz 63 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±30 MHz 64 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB Modulated Blocker Rejection ±5 MHz 48 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±10 MHz 61 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±15 MHz 62.5 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±20 MHz 65 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB ±30 MHz 65 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB Co-Channel Rejection −6 dB Prf,IN = Prf,IN,MIN + 10 dB Modulated Blocker Out-of Band Blocker Rejection −5 MHz −34.2 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz −10 MHz −30.7 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz −20 MHz −29.7 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz −30 MHz −25.7 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz −60 MHz −24.2 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz +5 MHz −33.4 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz +10 MHz −29.9 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz +20 MHz −28.2 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz +30 MHz −23.7 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz +60 MHz −29.9 dBm PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz Receiver Channel Bandwidth 2252 kHz Two-sided bandwidth; cascaded analog and digital channel filtering Frequency Error Tolerance −80 +80 ppm PRF,IN = PRF,IN,MIN + 3 dB

Rev. 0 | Page 10 of 108 Parameter Min Typ Max Unit Test Conditions RSSI Measured using IEEE 802.15.4-2006 packet mode Dynamic range 85 dB Accuracy ±3 dB Averaging Time 128 μs Minimum Sensitivity −95 dBm RECEIVE PATH GFSK MODE Sensitivity 1 % PER PRF,IN,MIN 2 Mbps −84.5 dBm 2000 kbps (fDEV = ±500 kHz) GFSK packet mode PRF,IN,MIN 1 Mbps −87.5 dBm 1000 kbps (fDEV = ±250 kHz) GFSK packet mode PRF,IN,MIN 500 kbps −92 dBm 500 kbps (fDEV = ±250 kHz) GFSK packet mode PRF,IN,MIN 250 kbps −92 dBm 250 kbps (fDEV = ±130 kHz) GFSK packet mode PRF,IN,MIN 125 kbps −94 dBm 125 kbps (fDEV = ±60 kHz) FSK packet mode PRF,IN,MIN 100 kbps −95 dBm 100 kbps (fDEV = ±30 kHz) FSK packet mode PRF,IN,MIN 62.5 kbps −96 dBm 62.5 kbps (fDEV = ±60 kHz) FSK packet mode PRF,IN,MIN 50 kbps −96 dBm 50 kbps (fDEV = ±30 kHz) FSK packet mode Sensitivity 0.1% BER PRF,IN,MIN 2 Mbps −87.5 dBm 2000 kbps (fDEV = ±500 kHz) GFSK SPORT mode PRF,IN,MIN 1 Mbps −90 dBm 1000 kbps (fDEV = ±250 kHz) GFSK SPORT mode PRF,IN,MIN 500 kbps −93 dBm 500 kbps (fDEV = ±250 kHz) GFSK SPORT mode PRF,IN,MIN 250 kbps −93 dBm 250 kbps (fDEV = ±130 kHz) GFSK SPORT mode PRF,IN,MIN 125 kbps −93 dBm 125 kbps (fDEV = ±60 kHz) FSK SPORT mode PRF,IN,MIN 62.5 kbps −96 dBm 62.5 kbps (fDEV = ±6 0kHz) FSK SPORT mode PRF,IN,MIN 50 kbps −96 dBm 50 kbps (fDEV = ±30 kHz) FSK SPORT mode Minimum Preamble Length 11 Bytes 2000 kbps (fDEV = ±50 0kHz) GFSK packet mode

9 Bytes 1000 kbps (fDEV = ±-250 kHz) GFSK packet mode

7 Bytes 500 kbps (fDEV = ±250 kHz) GFSK packet mode

7 Bytes 250 kbps (fDEV = ±-130 kHz) GFSK packet mode

7 Bytes 125 kbps (fDEV = ±60 kHz) FSK packet mode

7 Bytes 100 kbps (fDEV = ±-30 kHz) FSK packet mode

6 Bytes 62.5 kbps (fDEV = ±-60 kHz) FSK packet mode

6 Bytes 50 kbps (fDEV = ±30 kHz) FSK packet mode

Saturation Level −15 dBm All GFSK/FSK modes, packet and SPORT modes, 1% PER and 0.1% BER CW Blocking Rejection (2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode) PRF,IN = PRF,IN,MIN, 2 Mbps + 3 dB ±5 MHz 51 dB ±10 MHz 56 dB ±20 MHz 56.5 dB ±30 MHz 60.5 dB Modulated Blocking Rejection (2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode) PRF,IN = PRF,IN,MIN, 2 Mbps + 3 dB ±5 MHz 48 dB ±10 MHz 53 dB ±20 MHz 58 dB ±30 MHz 60 dB CW Blocker Rejection (125 kbps (fDEV = ±60 kHz) FSK Packet Mode) PRF,IN = PRF,IN,MIN, 125 kbps + 3 dB ±2 MHz 54.5 dB ±5 MHz 62 dB ±12 MHz 64 dB ±20 MHz 69 dB ±32 MHz 70.5 dB

Rev. 0 | Page 11 of 108 Parameter Min Typ Max Unit Test Conditions Modulated Blocking Rejection (2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode) PRF,IN = PRF,IN,MIN, 125 kbps + 3 dB ±2 MHz 52.5 dB ±5 MHz 60 dB ±12 MHz 64.5 dB ±20 MHz 68.5 dB ±32 MHz 71 dB Co-Channel Rejection −13 dB 2000 kbps (fDEV = ±500 kHz) GFSK packet mode, PRF,IN = PRF,IN,MIN, 2 Mbps + 10 dB, modulated blocker −9 dB 250 kbps (fDEV = ±130 kHz) GFSK packet mode, PRF,IN = PRF,IN,MIN, 250 kbps + 10 dB, modulated blocker Receiver Channel Bandwidth Minimum Channel 3 dB Bandwidth Analog Filter 1110 kHz Two-sided bandwidth Analog and Digital Filter Cascade 520 kHz Two-sided bandwidth Maximum Channel 3 dB Bandwidth 2252 kHz Two-sided bandwidth Frequency Error Tolerance, 2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode AFC Off ±55 kHz AFC On ±165 kHz AFC pull-in range = ±80 kHz Frequency Error Tolerance, 500 kbps (fDEV = ±250 kHz) FSK Packet Mode AFC Off ±90 kHz AFC On ±190 kHz AFC pull-in range = ±80 kHz RSSI, 2000 kbps (fDEV = ±500 kHz) GFSK Mode Accuracy ±3 dBm Minimum Sensitivity, Packet Mode −84.5 dBm Minimum Sensitivity, SPORT Mode −87.5 dBm SPORT mode with no preamble or SWD detection RSSI, 500 kbps (fDEV = ±250 kHz) GFSK Mode Accuracy ±3 dBm Minimum Sensitivity, Packet Mode −92 dBm Minimum Sensitivity, SPORT Mode −93 dBm SPORT mode with no preamble or SWD detection AUXILIARY SPECIFICATIONS Table 5. Parameter Min Typ Max Unit Test Conditions 32 kHz RC OSCILLATOR Frequency 32.768 kHz After calibration Frequency Accuracy 1 % After calibration at 25°C Frequency Drift Temperature Coefficient 0.14 %/°C Voltage Coefficient 4 %/V Calibration Time 1 ms 32 kHz CRYSTAL OSCILLATOR Frequency 32.768 kHz Maximum ESR 319.8 kΩ 10 pF on XOSC32KP and XOSC32KN Start-Up Time 2000 ms 12.5pF load capacitors on XOSC32KP and XOSC32KN WAKE-UP TIMER Prescaler Tick Period 0.0305 20,000 ms Wake-Up Period 61 × 10−6 1.31 × 105 sec

Rev. 0 | Page 12 of 108 Parameter Min Typ Max Unit Test Conditions TEMPERATURE SENSOR Range −40 +85 °C Resolution 4.7 °C Accuracy ±6.4 °C Average of 1000 ADC readbacks, after using linear fitting, with correction at known temperature BATTERY MONITOR Trigger Voltage 1.7 3.6 V Trigger Voltage Step Size 62 mV Start-Up Time 5 μs Current Consumption 30 μA EXTERNAL PA INTERFACE RON, PAVSUP_ATB3 to VDD_BAT 5 Ω extpa_bias_mode = 0, 1, 2, 5, 6 ROFF, PAVSUP_ATB3 to GND 10 MΩ extpa_bias_mode = 3, 4, power-down ROFF, PABIASOP_ATB4 to GND 10 MΩ extpa_bias_mode = 0, power-down PABIASOP_ATB4 Source Current, Maximum 80 μA expta_bias_mode = 1, 3 PABIASOP_ATB4 Sink Current, Minimum −80 μA extpa_bias_mode = 2, 4 PABIASOP_ATB4 Current Control Resolution 6 Bits extpa_bias_mode = 1, 2, 3, 4, 5 PABIASOP_ATB4 Compliance Voltage 150 mV extpa_bias_mode = 2, 4 PABIASOP_ATB4 Compliance Voltage 3.45 V extpa_bias_mode = 1, 3 Servo Loop Bias Current 22 mA extpa_bias_mode = 5, 6 Servo Loop Bias Current Control Step 0.349 mA extpa_bias_mode = 5, 6 CURRENT CONSUMPTION SPECIFICATIONS Table 6. Parameter Min Typ Max Unit Test Conditions CURRENT CONSUMPTION TX Mode Current Consumption −20 dBm 16.5 mA IEEE 802.15.4-2006 continuous packet transmission mode −10 dBm 17.4 mA IEEE 802.15.4-2006 continuous packet transmission mode 0 dBm 19.6 mA IEEE 802.15.4-2006 continuous packet transmission mode +3 dBm 21.5 mA IEEE 802.15.4-2006 continuous packet transmission mode +4 dBm 25 mA IEEE 802.15.4-2006 continuous packet transmission mode Idle Mode 1.8 mA XTO26M + digital active PHY_RDY Mode 10 mA RX Mode Current Consumption 19 mA IEEE 802.15.4-2006 packet mode MEAS State 3 mA SLEEP_BBRAM 0.3 μA BBRAM contents retained SLEEP_BBRAM_RCO 1 μA 32 kHz RC oscillator running, some BBRAM contents retained, wake-up time enabled SLEEP_BBRAM_XTO 1.7 μA 32 kHz crystal oscillator running, some BBRAM contents retained, wake-up time enabled

Table 7. Logic Levels Table 8. GPIOs Table 9. SPI Interface Timing

Table 10. IEEE 802.15.4 State Transition Timing Table 11. GFSK/FSK State Transition Timing 1 mac_delay_ext setting applies to both RX and TX states. The default setting is 0 μs.

Table 12. Timing IEEE 802.15.4-2006 SPORT Mode Table 13. MAC Timing Table 14. Timing GFSK SPORT Mode Figure 3. SPI Interface Timing Additional description and timing diagrams are available in the Serial Peripheral interface section.

Figure 12. GFSK/FSK RX SPORT Mode: SCLK and Data Pins Activity Gated By Synchronization Word Detection Table 18. GFSK/FSK TX SPORT Mode Configurations

Figure 13. GFSK/FSK TX SPORT Mode Refer to the SPORT Interface section for further details.

Rev. 0 | Page 22 of 108 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 19. Parameter Rating VDD_BAT to GND −0.3 V to +3.9 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance 26°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The exposed paddle of the LFCSP package should be connected to ground. This device is a high performance RF integrated circuit with an ESD rating of <2 kV , and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION

23 MOSI

22 SCLK

21 MISO

20 IRQ1_GP4

19 TRCLK_CKO_GP3

18 IRQ2_TRFS_GP2

1. THE EXPOSED PADDLE MUST BE CONNECTED

17 DT_GP1

Figure 14. Pin Configuration Table 20. Pin Function Descriptions 2 RBIAS Bias Resistor 27 kΩ to Ground. 3 CREGRF2 Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor to ground. 4 RFIO1P Differential RF Input Port 1 (Positive Terminal). A 10 nF coupling capacitor is required. 5 RFIO1N Differential RF Input Port 1 (Negative Terminal). A 10 nF coupling capacitor is required. 6 RFIO2P Differential RF Input/Output Port 2 (Positive Terminal). A 10 nF coupling capacitor required. 7 RFIO2N Differential RF Input/Output Port 2 (Negative Terminal). A 10 nF coupling capacitor required. 8 CREGRF3 Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor from this pin to GND. 9 CREGVCO Regulated Supply for VCO Section. Connect a 220 nF decoupling capacitor from this pin to GND. 10 VCOGUARD Guard Trench for VCO Section. Connect to Pin 9 (CREGVCO). 11 CREGSYNTH Regulated Supply for PLL Section. Connect a 220 nF decoupling capacitor from this pin to GND. 13 XOSC26N Terminal 2 of External Crystal and Loading Capacitor. Input for external oscillator. 14 DGUARD Guard Trench for Digital Section. Connect to Pin 15 (CREGDIG2). 15 CREGDIG2 Regulated Supply for Digital Section. Connect a 220 nF decoupling capacitor to ground. 16 DR_GP0 SPORT Receive Data Output/General-Purpose IO Port. 17 DT_GP1 SPORT Transmit Data Input/General-Purpose IO Port. 18 IRQ2_TRFS_GP2 Interrupt Request Output 2/Symbol Clock IEEE 802.15.4-2006 Mode/General-Purpose IO Port. 19 TRCLK_CKO_GP3 SPORT Clock Output/General-Purpose IO Port. 20 IRQ1_GP4 Interrupt Request Output1/General-Purpose IO Port. 21 MISO SPI Interface Serial Data Output. 22 SCLK SPI Interface Data Clock Input. 23 MOSI SPI Interface Serial Data Input. 24 CS SPI Interface Chip Select Input (and Wake-Up Signal). 25 TXEN_GP5 External PA Enable Signal/General-Purpose IO Port. 26 RXEN_GP6 External LNA Enable Signal/General-Purpose IO Port. 27 CREGDIG1 Regulated Supply for Digital Section. Connect a 1 nF decoupling capacitor from this pin to ground. 28 XOSC32KP_GP7_ATB1 Terminal 1 of 32 kHz Crystal Oscillator/General-Purpose IO Port/Analog Test Bus 1.

Rev. 0 | Page 24 of 108 Pin No. Mnemonic Description 29 XOSC32KN_ATB2 Terminal 2 of 32 kHz Crystal Oscillator/Analog Test Bus 2. 30 VDD_BAT Unregulated Supply Input from Battery. 31 PAVSUP_ATB3 External PA Supply Terminal/Analog Test Bus 3. 32 PABIAOP_ATB4 External PA Bias Voltage Output/Analog Test Bus 4. 33 (EPAD) GND Common Ground Terminal. The exposed paddle must be connected to ground.

Figure 63. Transmitter Phase Error vs. Data Rate for Each of the Transmitter Figure 66. Transmitter Output Power vs. Control Word for Default and High Figure 67. Transmitter Current Consumption vs. Control Word, for Default Figure 64. PA Output Power vs. RF Carrier Frequency, Temperature, and VDD_BAT

3 SIGMA TEMPERATURE ERROR

Figure 68. Temperature Sensor Performance Figure 65. PA Output Power vs. Control Word, Temperature, and VDD_BAT,

Rev. 0 | Page 34 of 108 TERMINOLOGY ACK IEEE 802.15.4-2006 acknowledgment frame ADC Analog-to-digital converter AFC Automatic frequency correction AGC Automatic gain control Battmon Battery monitor CCA Clear channel assessment BBRAM Backup battery random access memory CRC Cyclic redundancy check CSMA/CA Carrier-sense-multiple-access with collision avoidance DR Data rate DSSS Direct sequence spread spectrum FCS Frame check sequence FHSS Frequency hopping spread spectrum FCF Frame control field FSK Frequency shift keying GFSK Gaussian frequency shift keying LQI Link quality indicator MCR Modem configuration register MCU Microcontroller unit MER Modulation error ratio MSK Minimum shift keying NC Not connected OCL Offset correction loop OQPSK Offset-quadrature phase shift keying PA Power amplifier PHR PHY header PHY Physical layer POR Power-on reset PSDU PHY service data unit RC Radio controller RCO32K 32 kHz RC oscillator RSSI Receive signal strength indicator RTC Real-time clock SFD Start-of-frame delimiter SQI Signal quality indicator SWD Sync word detect VCO Voltage-controlled oscillator WUC Wa ke-up cont rol ler XTO26M

26 MHz crystal oscillator

1AVAILABLE IN IEEE 802.15.4 MODE OR IN FSK/GFSK PACKET MODE. 2THESE TRANSITIONS ARE CONFIGURED IN BUFFERCFG (0x107[3:2]). Figure 69. ADF7242 State Diagram

Rev. 0 | Page 36 of 108 The ADF7242 incorporates a radio controller that manages the state of the IC in various operating modes and configurations. The host MCU can use single-byte commands to interface to the radio controller. The function of the radio controller includes the control of the sequence of powering up and powering down various blocks as well as system calibrations in different states of the device. Figure 69 shows the state diagram of the ADF7242 with possible transitions that are initiated by the host MCU and automatically by the radio controller. Device Initialization When the battery voltage is first applied to the ADF7242, a cold start-up sequence should be followed, as shown in Figure 70. The start-up sequence is as follows:

• Apply the battery voltage, VDD_BAT, to the device with the desired voltage ramp rate. After a time, tRAMP, VDD_BAT reaches its final voltage value.
• After tRAMP, execute the SPI command, RC_RESET. This command resets and shuts down the device.
• After the specified time, t15, the host MCU can set the CS port of the SPI low.
• Wait until the MISO output of the SPI (SPI_READY flag) goes high, at which time the device is in the idle state and ready to accept commands. A power-on reset takes place when the host MCU sets the CS port of the SPI low. All device LDOs are enabled together with the 26 MHz crystal oscillator and the digital core. After the radio controller initializes the configuration registers to their default values, the device enters the idle state. The cold start-up sequence is needed only when the battery voltage is first applied to the device. Afterwards, a warm start- up sequence can be used where the host MCU can wake up the device from a sleep state by setting the CS port of the SPI low. Idle State In this state, the receive and transmit blocks are powered down. The digital section is enabled and all configuration registers as well as the packet RAM are accessible. The host MCU has to set any configuration parameters, such as modulation scheme, channel frequency, and WUC configuration in this state. Bringing the CS input low in the sleep state causes a transition into the idle state. The transition from the sleep state to the idle state timing is shown in . The idle state can also be entered by issuing an RC_IDLE command in any state other than the sleep state. Figure 4 PHY_RDY State Upon entering the PHY_RDY state from the idle state, the RF frequency synthesizer is enabled and a system calibration is carried out. The receive and transmit blocks are not enabled in this state. The system calibration is omitted when the PHY_RDY state is entered from the RX, TX, or CCA state. The PHY_RDY state can be entered from the idle, RX, TX, or CCA state by issuing an RC_PHY_RDY command. RX State The RF frequency synthesizer is automatically calibrated to the programmed channel frequency upon entering the RX state from the PHY_RDY or TX state. The frequency synthesizer calibration can be omitted for single-channel communication systems if short turnaround times are required. Following a programmable MAC delay period, the ADF7242 starts searching for a preamble and a synchronization word if enabled by the user. The RX state can be entered from the PHY_RDY , CCA, and TX states by issuing an RC_RX command. Depending on whether the device is configured to operate in packet or SPORT mode by setting Register buffercfg, Field rx_buffer_mode, the device can revert automatically to the PHY_RDY state when a packet is received, or remain in the RX state until a command to enter a different state is issued. Refer to the Receiver section for further details. CCA State Upon entering the CCA state, a clear channel assessment is performed. The CCA state can be entered from the PHY_RDY or RX state by issuing an RC_CCA command. By default, upon completion of the clear channel assessment, the ADF7242 automatically reverts to the state from which the RC_CCA command originated. TX State Upon entering the TX state, the RF frequency synthesizer is automatically calibrated to the programmed channel frequency. The frequency synthesizer calibration can be omitted for communication systems operating on a single channel if short turnaround times are required. Following a programmable delay period, the PA is ramped up and transmission is initiated. The TX state can be entered from the PHY_RDY or RX state by issuing the RC_TX command. Depending on whether the device is configured to operate in packet or SPORT mode by setting Register buffercfg, Field rx_buffer_mode, the device can revert automatically to the PHY_RDY state when a packet is transmitted, or remain in the TX state until a command to enter a different state is issued. Refer to the Transmitter section for further details. MEAS State The MEAS state is used to measure the chip temperature. The transmitter and receiver blocks are not enabled in this state. The chip temperature is measured using the ADC, which can be read from Register adc_rbk, Field adc_out, and is continuously updated with the chip temperature reading. This state is enabled by issuing the RC_MEAS command from the idle state and can be exited using the RC_IDLE command.

modes, which are listed in Table 21. set using, for example, Register irq1_en0, Field wakeup = 1. how to configure the ADF7242 WUC. Table 21. ADF7242 Sleep Modes contents are not maintained. configuration registers in the BBRAM during the sleep state. set using, for example, Register irq1_en0, Field wakeup = 1. how to configure the ADF7242 WUC. for details on how to configure the ADF7242 WUC. section for further details. tmr_cfg0 and Register tmr_cfg1 are reset in the sleep state. by setting Register tmr_cfg1, Field sleep_config = 1. Figure 70. Cold Start Sequence from Application of the Battery

Rev. 0 | Page 39 of 108 on the required data rate to ensure optimum modulation quality. The frequency synthesizer bandwidth is optimized for the recommended modulation schemes, data rates, and fre- quency deviations given in Table 22. If the user requires a different modulation scheme or data rate from those listed in Table 22, it is recommended, for optimum device performance, to choose a frequency deviation for the required data rate that gives a modulation index close to those recommended in Table 22. RF CHANNEL FREQUENCY PROGRAMMING The frequency of the synthesizer is programmed with the frequency control word, ch_freq[23:0], which extends over Register ch_freq0, Register ch_freq1, and Register ch_freq2. The frequency control word, ch_freq[23:0], contains a binary representation of the absolute frequency of the desired channel divided by 10 kHz. Writing a new channel frequency value to the frequency control word ch_freq[23:0] takes effect after the next frequency synthesizer calibration phase. The frequency synthesizer is calibrated by default during the transition into the PHY_RDY from the idle state as well as in the TX, RX and CCA states. Refer to the RF Frequency Synthesizer Calibration, Transmitter, and Receiver sections for further details. To facilitate fast channel frequency changes, a new frequency control word can be written in the RX state before a packet has been received. The next RC_RX o RC_TX command initiates the required frequency synthesizer calibration and settling cycle. Similarly, a new frequency control word can be written after a packet has been transmitted while in the TX state and the next RC_RX or RC_TX command initiates the frequency synthesizer calibration and settling cycle. REFERENCE CRYSTAL OSCILLATOR The on-chip crystal oscillator generates the reference frequency for the frequency synthesizer and system timing. The oscillator operates at a frequency of 26 MHz. The crystal oscillator is amplitude controlled to ensure a fast start-up time and stable operation under different operating conditions. The crystal and associated external components should be chosen with care because the accuracy of the crystal oscillator can have a significant impact on the performance of the communication system. Apart from the accuracy and drift specification, it is important to consider the nominal loading capacitance of the crystal. Crystals with a high loading capacitance are less sensitive to frequency pulling due to tolerances of external capacitors and the printed circuit board parasitic capacitances. When selecting a crystal, these advantages should be balanced against the higher current consumption, longer start-up time, and lower trimming range resulting from a larger loading capacitance. The total loading capacitance must be equal to the specified load capacitance of the crystal and comprises the external parallel loading capacitors, the parasitic capacitances of the XOSC26P and XOSC26N pins, as well as the parasitic capacitance of tracks on the printed circuit board. The ADF7242 has an integrated crystal oscillator tuning capacitor that facilitates the compensation of systematic production tolerance and temperature drift. The tuning capacitor is con- trolled with Register xto26_trim _cal, Field xto26_trim (0x371). The tuning range provided by the tuning capacitor depends on the loading capacitance of a specific crystal. The total tuning range is typically 25 ppm

• IEEE 802.15.4-2006 packet mode
• IEEE 802.15.4-2006 SPORT mode
• GFSK/FSK packet mode
• GFSK/FSK SPORT mode The desired mode of operation is selected via Register rc_cfg, Field rc_mode. The ADF7242 supports GFSK/FSK modulation with the data rates listed in Table 22. The ADF7242 also fully supports user-defined data rates between 50 kbps and 2 Mbps for FSK mode of operation. The data rate, DR, is set with Register dr0, Field data_rate_high and Register dr1, Field data_rate_low according to the following equation: DR = (data_rate_high × 256 + data_rate_low) × 100 bps The default values of the dr0 and dr1 registers configure the device for IEEE 802.15.4-2006 mode. For GFSK/FSK data rates greater than 250 kbps and IEEE 802.15.4- 2006 mode, the modulator preemphasis filter must be enabled with Register tx_m, Field preemp_filt = 1. The modulator of the ADF7242 has an optional Gaussian symbol filter that can be enabled with Configuration Register tx_m, Field gauss_filt = 1. The BT product of the Gaussian symbol filter is fixed at 0.5. This can be used for improved spectral efficiency. Gaussian filtering must be disabled for IEEE 802.15.4-2006 mode. The deviation frequency (f DEV) of the modulator is programma- ble with Register tx_fd, Field tx_freq_dev in steps of 10 kHz. Refer to the Device Configuration section for recommended settings for Register tx_fd, Field tx_freq_dev corresponding with the recommended modulation parameters listed in Table 22. The default value of Register tx_fd, Field tx_freq_dev configures the correct setting for IEEE 802.15.4-2006 mode. If the user requires a different modulation scheme or data rate from those listed in Table 22, it is recommended, for optimum device performance, to choose a frequency deviation for the required data rate that gives a modulation index close to those recom- mended in Table 22 TRANSMITTER IN IEEE 802.15.4-2006 MODE IEEE 802.15.4-2006 Transmission IEEE 802.15.4-2006-compatible mode with packet manager support is selected with Register rc_cfg, Field rc_mode = 0 (0x13E). In this mode, the ADF7242 packet manager automati- cally generates the IEEE 802.15.4-2006-compatible preamble and SFD. There is also an option to use a nonstandard SFD by programming Register sfd_15_4 with the desired alternative SFD. Refer to the IEEE 802.15.4-2006 Programmable SFD subsection of the Receiver in IEEE 802.15.4-2006 Mode section for further details. There are 256 bytes of dedicated RAM (packet RAM), which constitute TX_BUFFER and RX_BUFFER, available to store transmit and receive packets. The packet header must be the first byte written to TX_BUFFER. The address of the first byte of TX_BUFFER is stored in Register txpb, Field tx_pkt_base. If the automatic FCS field generation has been disabled (Register pkt_cfg, Field auto_fcs_off = 1), the full frame including FCS must be written to TX_BUFFER. In this case, the number of bytes written to TX_BUFFER must be equal to the length specified in the PHR field. If automatic FCS field generation has been enabled (Register pkt_cfg, Field auto_fcs_off = 0), the FCS is automatically appended to the frame in TX_BUFFER. In this case, the number of bytes written to TX_BUFFER must be equal to the length specified in the PHR field minus two. The format of the frame in TX_BUFFER, both with automatic FCS field generation enabled and with it disabled, is shown in Figure 73. Details of how to configure IEEE 802.15.4-2006 TX SPORT mode are given in the SPORT Interface section.

Table 22. Recommended Modulation Schemes

62.5 GFSK/FSK fDEV = ±60 kHz

125 GFSK/FSK fDEV = ±60 kHz

250 GFSK/FSK fDEV = ±130 kHz

500 GFSK/FSK fDEV = ±250 kHz

1000 GFSK/FSK fDEV = ±250 kHz

2000 GFSK/FSK fDEV = ±500 kHz

RC_PHY_RDY , or RC_RX command. optionally calculate and transmit a CRC word. The preamble is a 0xAA sequence, with a programmable length. required preamble length depends on the radio configuration. length for some examples of different configurations. pad the SWD (see the Sync Word (SWD) section for details). end of sync word to the start of the CRC. Table 23. Description of Fields Applicable to GFSK/FSK Packet Transmission

power-down pin and/or have a high power-down current. between PAVSUP_ATB3 and VDD_BAT is open. between PAVSUP_ATB3 and VDD_BAT is open. with increasing voltage at the PABIAOP_ATB4 output. decreasing voltage at the PABIAOP_ATB4 output. Figure 81. Typical External PA Applications Circuit Table 26. PA Interface

1 VDD_BAT to PAVSUP_ATB3 Switch Function of Pin PABIAOP_ATB4

1 Autoenabled when Register ext_ctrl, Field extpa_auto_en = 1. Figure 82. Details of External PA Interface circuit

Rev. 0 | Page 48 of 108 RECEIVER RECEIVE OPERATING MODES The four primary receiver operating modes are

• IEEE 802.15.4-2006 packet manager mode
• IEEE 802.15.4-2006 SPORT mode
• GFSK/FSK packet manager mode
• GFSK/FSK SPORT mode The desired operating mode is selected with Register rc_cfg, Field rc_mode. The SPORT modes are explained in more detail in the SPORT Interface section. The data rate is set with Register dr0, Field data_rate_high and Register dr1, Field data_rate_low as documented in the Transmitter section. The data rate is automatically configured in IEEE 802.15.4-2006 mode. RECEIVER IN IEEE 802.15.4-2006 MODE IEEE 802.15.4-2006 Reception When IEEE 802.15.4-2006 mode is selected, the output of the post demodulator filter is fed into a bank of correlators, which compare the incoming data sequences to the expected receiver block operates in three primary states.
• Preamble qualification
• Symbol timing recovery
• Data symbol reception During preamble qualification, the correlators check for the pres- ence of preamble. When preamble is qualified, the device enters symbol timing recovery mode. The device symbol timing is achieved once a valid SFD is detected. The ADF7242 supports programmable SFDs. Refer to the IEEE 802.15.4-2006 Programmable SFD section for further details. The received symbols are then passed to the packet manager in packet mode or the SPORT interface in SPORT mode. In SPORT mode, four serial clocks are output on Pin TRCLK_CKO_GP3, and four data bits are shifted out on Pin DR_GP0 for each received symbol. Refer to the SPORT Interface section for further details. If in packet mode, when the packet manager determines the end of a packet, the ADF7242 automatically transitions to PHY_ RDY or TX or remains in RX, depending on the setting in Register buffercfg, Field rx_buffer_mode (see IEEE 802.15.4- 2006 Receiver Configuration in Packet Mode section). If in SPORT mode, the part remains in RX until the user issues a command to change to another state. IEEE 802.15.4-2006 Programmable SFD An alternative to the standard IEEE 802.15.4-2006 SFD byte can optionally be selected by the user. The default setting of Register sfd_15_4, Field sfd_symbol_1 and Field sfd_symbol_2 (0x3F4[7:0]) is the standard IEEE 802.15.4-2006 SFD. If the user programs this register with an alternative value, this is used as the SFD in receive and transmit in IEEE 802.15.4-2006 mode. The requirements are as follows:
• The value must not be a repeated symbol (for example, not 0x11 or 0x22).
• The value must not be similar to the preamble symbol (that is, not Symbol 0x0 or Symbol 0x8). IEEE 802.15.4-2006 Receiver Configuration in Packet Mode IEEE 802.15.4-2006 mode with packet management support is selected when Register rc_cfg, Field rc_mode = 0 (0x13E[7:0]). RX_BUFFER is overwritten when the ADF7242 enters the RX state following an RC_RX command and an SFD is detected. The SFD is stripped off the incoming frame, and all data following and including the frame length (PHR) is written to RX_BUFFER. If Register pkt_cfg, Field auto_fcs_off = 1, the FCS of the incoming frame is stored in RX_BUFFER. When the entire frame has been received, an rx_pkt_rcvd interrupt is asserted irrespective of the correctness of the FCS. If auto_fcs_off = 0, the radio controller calculates the FCS of the incoming frame according to the FCS polynomial defined in the IEEE 802.15.4-2006 standard (see Equation 1), and compares the result against the FCS of the incoming frame. An rx_pkt_rcvd interrupt is asserted only if both FCS fields match. The FCS is not written to RX_BUFFER but is replaced with the measured RSSI and signal quality indicator (SQI ) values of the received frame (see Figure 83). 1) ( 5 12 16 The behavior of the radio controller following the reception of a frame can be configured with Register buffercfg, Field rx_ buffer_mode (0x107[1:0]). With the default setting rx_buffer_ mode = 0, the part reverts automatically to PHY_RDY when an rx_pkt_rcvd interrupt condition occurs. This mode prevents RX_BUFFER from being overwritten by the next frame before the host MCU can read it from the ADF7242. This is because a new frame is always written to RX_BUFFER starting from the address stored in Register rxpb, Field rx_pkt_base (0x315[7:0]). Note that reception of the next frame is inhibited until the MAC delay following an RC_RX command has elapsed. If Register buffercfg, Field rx_buffer_mode = 1 (0x107[1:0]), the part remains in the RX state, and the reception of the next packet is enabled one MAC delay period after the frame has been written to RX_BUFFER. Depending on the network setup, this mode can cause an unnoticed violation of RX_BUFFER integrity if a frame arrives prior to the MCU having read the frame from RX_BUFFER. If Register buffercfg, Field rx_buffer_mode = 2 (0x107[1:0]), the reception of frames is disabled. This mode is useful for RSSI measurements and CCA, if the contents of RX_BUFFER are to be preserved.

Rev. 0 | Page 52 of 108 LINK QUALITY INDICATION (LQI) The link quality indication (LQI) is defined in the IEEE 802.15.4- 2006 standard as a measure of the signal strength and signal quality of a received IEEE 802.15.4-2006 frame. The ADF7242 makes several measurements available from which an IEEE 802.15.4-2006- compliant LQI value can be calculated in the MCU. The first parameter is the RSSI value (see the Automatic Gain Control (AGC) and Receive Signal Strength Indicator (RSSI) subsection of the Receiver Radio Blocks section). The second parameter required for the LQI calculation can be read from Register lrb, Field sqi_readback (0x30D[7:0]), which contains an 8-bit value representing the quality of a received IEEE 802.15.4-2006 frame. It increases monotonically with the signal quality and must be scaled to comply with the IEEE 802.15.4-2006 standard. If the ADF7242 is operating in IEEE 802.15.4-2006 packet mode (Register rc_cfg, Field rc_mode = 0 (0x13E[7:0])), and Register pkt_cfg, Bit auto_fcs_off = 0 (0x108[0]), the SQI of a received frame is measured and stored together with the frame in RX_BUFFER. The SQI is measured over the entire packet and stored in place of the second byte of the FCS of the received frame in RX_BUFFER.

Figure 90. Automatic CSMA/CA Transmit Operation (with CCA)

upon receiving a qualified preamble, sync word, or valid FCS. of the packet manager in receive mode. the packet manager in RX_BUFFER. detection circuit tracks the received frame as a sliding window. Field fsk_preamble_match_level, as shown in Table 28. the preamble and restarts the detection. lock_after_preamble to 1 (0x111[5]). Table 28. Preamble Detection Tolerance Table 29. Description of Fields Applicable to GFSK/FSK Packet Reception Figure 91. GFSK/FSK Packet Fields stored by the Packet Manager in RX_BUFFER

Figure 92. Search for Preamble and Search for Sync Word Routine be one bit to 24 bits in length. Table 30. On reception of a valid sync word, the chip processor automatically writes the receive payload to the packet RAM. details on packet RAM, refer to the Memory Map section. Table 30. Sync Word Detection Tolerance (sync_config, rx_pkt_rcvd interrupt in Register irq1_en1 or Register irq2_en1.

ported in GFSK/FSK mode only. Register afc_cfg, Field afc_mode = 2. selection of data rates is given in Table 31. postdemodulator filter settings and for example data rates. formats are described in the AN-915 Application Note. within five symbol transitions of preamble. Table 31. Example AFC Performance

the analog and digital filters. time-varying offset voltages present in the zero-IF receiver path. pertaining to the offset correction loop. Table 32. Analog and Digital Filter Parameters

Rev. 0 | Page 62 of 108 Automatic Gain Control (AGC) and Receive Signal Strength Indicator (RSSI) The ADF7242 AGC circuit features fast overload recovery using dynamic bandwidth adjustments for fast preamble acquisition and optimum utilization of the dynamic range of the receiver path. The radio controller automatically enables the AGC after an offset correction phase, which is carried out when the trans- ceiver enters the RX state. The optimum AGC configuration parameters depend on the selected data rate, the modulation format, and the configuration of the receiver offset correction loop. The recommended settings for the AGC configuration registers based on the modulation parameters, shown in Table 22, are given in the Device Configuration section. In GFSK/FSK mode, it is possible to lock the AGC and prevent further gain updates after the reception of the preamble using Register fsk_preamble_config, Field fsk_agc_lock_after_ preamble. The RSSI readback value is continuously updated while the ADF7242 is in the RX state. The result is provided in Register rrb, Field rssi_readback (0x30C[7:0]) in decibels relative to 1 mW (dBm) using signed twos complement notation. The RSSI averaging window is synchronized with the start of the active RX phase at the end of the MAC delay following an RC_RX command. The RSSI averaging time is programmable with Register agc_cfg5, Field rssi_avg_time (0x3B9[1:0]), and depends on the AGC update rate according to the following formula: T_avg_rssi = 77 ns × 2α where α = 2 + (Register agc_cfg5, Field agc_filt2_tavg1) +(Register agc_cfg6, Field agc_filt2_tavg2) + (Register agc_cfg5, Field rssi_avg_time) In IEEE 802.15.4-2006 mode, the default RSSI averaging period of 128 μs, or eight symbol periods, must be used for compliance with the IEEE 802.15.4-2006 standard. If the ADF7242 is operating in the IEEE 802.15.4-2006 packet mode, the RSSI of received frames is measured and stored together with the frame in RX_BUFFER. The RSSI is measured in a window with a length of eight symbols immediately following the detected SFD. The result is then stored in place of the first byte of the FCS of the received frame in RX_BUFFER. For GFSK/FSK mode, the optimum RSSI averaging time is application dependent and the default settings should be appropriate for most applications. It is also possible to compensate for systematic errors of the measured RSSI value and/or production tolerances by adjusting the RSSI readback value by an offset value that can be programmed in Register agc_cfg5, Field rssi_offs (0x3B9[4:2]). The adjustment resolution is in 1 dB steps.

Figure 97. SPORT Operation in GFSK/FSK TX State Figure 98. Overview of SPORT Modes in GFSK/FSK RX State Table 33. GFSK/FSK Mode SPORT Interface Configurations

1 RX: not used, low

2 RX: goes high when sync

3 RX: goes high when sync

4 RX: not used, low

5 RX: goes high when sync

6 RX: goes high when sync

the SPORT interface in IEEE 802.15.4-2006 mode. gpio_config = 7 (0x32C[7:0]) to enable the symbol clock output. Table 34. IEEE 802.15.4 Mode SPORT Interface Configuration

each of the four primary modes are detailed in Table 35. the ADF7242 in the desired mode of operation. Table 35. Register Writes Required to Configure the ADF7242 1 These apply only when the user wishes to program a nonstandard SFD. 2 This register should only be written to in GFSK/FSK packet mode because the default setting of 0x05 is used in IEEE 802.15.4 packet mode.

802.15.4 AND GFSK/FSK MODES

be written to the relevant register field. Table 36. Settings Required to Select Between LNA Port 1 Table 37. Settings Common to All GFSK/FSK Configurations Table 38. Data Rate-Specific GFSK/FSK Settings

1 Mbps

2 Mbps

Transmitter in GFSK/FSK Mode section for details.

GFSK/FSK, write the values given in Table 39. Table 39. Settings for GFSK/FSK Packet and SPORT Modes Table 40 gives recommended sync word configuration values. Receiver in GFSK/FSK Mode section of the datasheet for details. Table 40. Example Sync Word Configuration for GFSK/FSK To enable the AFC, write the values given in Table 41. Table 41. AFC Configuration Settings for GFSK/FSK

2006 PACKET AND SPORT MODES

should be written to the ADF7242. Table 42. IEEE 802.15.4 Configuration Settings 2006 Programmable SFD section for details.

one of the two RF ports can be active at any one time. if the ADF7242 is connected to an external LNA and/or PA. Register rxfe_cfg, Field lna_sel (0x39B[6:4]). by setting Register rxfe_cfg, Field lna_sel = 1 (default setting). system, it is often sufficient to select the optimum antenna once. input (Register rxfe_cfg, Field lna_sel = 0). in RX state and a logic low level while in any other state. circuits based upon a single FET. dipole antenna is used. In this case, a balun is not required. Figure 99. RF Interface Configuration Options (A: Single Antenna; B: Antenna Diversity; C: External LNA/PA; D: Dipole Antenna)

temperature sensor has an operating range from −40°C to +85°C. Field battmon_voltage (0x3E6[4:0]). Table 43. Prescaler Division Factors can be enabled in Register irq1_en0 or Register irq2_en0. Figure 100. Hardware Wake-Up Timer Diagram

• The clock signal for the timer is taken from the external 32.768 kHz crystal or the internal RC oscillator. This is selectable via Register tmr_cfg1, Bit sleep_config (0x317[6:3]).
• A 3-bit prescaler, which is programmable via Register tmr_cfg0, Bit timer_prescal (0x316[2:0]) determines the tick period. This is followed by a preloadable 16-bit down counter. After the clock is selected, the reload value for the down counter (tmr_rld0 and tmr_rld1) and the prescaler values (Register tmr_cfg0, Bit timer_prescal) can be programmed. When the clock has been enabled, the counter starts to count down at the tick rate starting from the reload value. If wake-up interrupts are enabled, the timer unit generates an interrupt when the timer value reaches 0x0000. When armed, the wake-up interrupt triggers a wake-up from sleep. The reliable generation of wake-up interrupts requires the WUC timeout flag to be reset immediately after the reload value has been programmed. To do this, first write 1and then write 0 to Register tmr_ctrl, Field wake_timer_flag_reset. To enable automatic wake-up from the sleep state, arm the timer unit for wake-up operation by writing 1 to Register tmr_cfg1, Field wake_on_timeout. After writing this sequence to the ADF7242, a sleep command can be issued. Calibrating the RC oscillator The RC oscillator is not automatically calibrated. If it is desired to use the RC oscillator as the clock source for the WUC, the host MCU should initiate a calibration. This can be performed at any time in advance of entering the sleep state. To perform a calibration, the host MCU should Set Register tmr_ctrl, Field wuc_rc_osc_cal = 0
• Set Register tmr_ctrl, Field wuc_rc_osc_cal = 1 The calibration time is typically 1 ms. When the calibration is complete Register wuc_32khzosc_status, Field rc_osc_cal_ready is high. Following calibration, the host MCU can transition to the SLEEP_BBRAM_RCO sleep state, by following the full procedure given in the WUC Configuration and Operation section. TRANSMIT TEST MODES The ADF7242 has various transmit test modes that can be used in IEEE 802.15.4-2006 and GFSK/FSK SPORT modes. These test modes can be enabled by writing to Register tx_fsk_test (Location 0x3F0), as described in Table 44. A continuous packet transmission mode is also available in IEEE 802.15.4-2006 and GFSK/FSK packet modes. This mode can be enabled using the following procedure: An IEEE 80.215.4-2006 or a GFSK/FSK packet with random payload should be written to TX_BUFFER as described in the Transmitter section. It is recommended to use a packet with the maximum length of 127 bytes. Set Register buffercfg, Field trx_mac_delay = 1. 3. Set Register buffercfg, Field tx_buffer_mode = 3. 4. Set Register pkt_cfg, Field skip_synth_settle = 1. 5. Issue Command RC_TX. The transmitter continuously transmits the packet stored in TX_BUFFER. If Command RC_PHY_RDY is issued at any point after this step, all the preceding configuration registers must be rewritten to the device before reissuing Command RC_TX. Note that the transmitter momentarily transmits an RF carrier between packets due to a finite delay from when the packet handler finishes transmitting a packet in TX_BUFFER and going back to transmit the start of TX_BUFFER again.

Table 44. 0x3F0: tx_fsk_test [7:4] Reserved R/W 2 Reserved, set to default. 3 zero_only R/W 0 Transmit 0 only (fCH − fDEV) in GFSK/FSK sport mode. 2 one_only R/W 0 Transmit 1 only (fCH + fDEV) in GFSK/FSK sport mode. 1 carrier_only R/W 0 Transmits unmodulated tone at the programmed frequency fCH. 0 Reserved R/W 0 Reserved, set to default.

Table 45. Command List SPI_NOP 0xFF No operation. Use for dummy writes. Register txpb, Field tx_pkt_base (0x314[7:0]). Register rxpb, Field rx_pkt_base (0x315[7:0]). SPI_MEM_WR 0x18 + memory address[10:8] Write data to MCR or packet RAM sequentially. SPI_MEM_RD 0x38 + memory address[10:8] Read data from MCR or packet RAM sequentially. SPI_MEMR_WR 0x08 + memory address[10:8] Write data to MCR or packet RAM as a random block. SPI_MEMR_RD 0x28 + memory address[10:8] Read data from MCR or packet RAM as a random block. SPI_PRAM_WR 0x1E Write data to the program RAM. Table 46. SPI Status Word 7 SPI_READY 0: SPI is not ready for access. 6 IRQ_STATUS 0: no pending interrupt condition. 5 RC_READY 0: radio controller is not ready to accept RC_xx command strobe. 1: radio controller is ready to accept new RC_xx command strobe. 4 CCA_RESULT 0: channel busy. Valid when Register irq_src1, Bit cca_complete (0x3CC[0]) is asserted.

these variables are 11 bits in length. MCR are not retained in the sleep state. Figure 104. The rx_pkt_base value should be chosen to ensure maximum receiver payload length.

256 BYTES

64 BYTES

Figure 103. ADF7242 Memory Map

Figure 104. Example Packet RAM Configurations Using the Transmit Packet and Receive Packet Address Pointers

any radio controller state including during state transition.

5 BITS MEMORY ADDRESS

Figure 105. SPI Memory Access Command/Address Format Table 47. Summary of SPI memory access commands Register txpb, Field tx_pkt_base (0x314[7:0]). Register rxpb, Field rx_pkt_base (0x315[7:0]). command (xxxb). This command is followed by the remaining eight bits of the address. is subsequently followed by the appropriate number of SPI_NOP commands. Write data to BBRAM/MCR or packet RAM at random. Read data from BBRAM/MCR or packet RAM at random. SPI_PRAM_WR =0x1E (program RAM) Write data to program RAM. the MOSI line when performing a memory read.

Rev. 0 | Page 77 of 108 WRITING TO THE ADF7242 Block Write Packet RAM memory locations can be written to in block format using the SPI_PKT_WR. The SPI_PKT_WR command is 0x10. This command provides pointer-based write access to the packet RAM. The address of the location written to is calcu- lated from the base address in Register txpb, Field tx_pkt_base (0x314[7:0]) plus an index. The index is zero for the first data word following the command word, and is auto-incremented for each consecutive data word written. The first data word follow- ing an SPI_PKT_WR command is thus stored in the location with Address txpb, Field tx_pkt_base (0x314[7:0]), the second in packet RAM location with Address txpb, Field tx_pkt_base + 1, and so on. This feature makes this command efficient for bulk writes of data that recurrently begin at the same address. Figure 106 shows the access sequence for Command SPI_PKT_WR. The MCR, BBRAM, and packet RAM memory locations can be written to in block format using the SPI_MEM_WR command. The SPI_MEM_WR command code is 00011xxxb, where xxxb represent Bits[10:8] of the first 11-bit address. If more than one data byte is written, the write address is automatically incre- mented for every byte sent until CS is set high, which terminates the memory access command. See for more details. The maximum block write for the MCR, packet RAM, and BBRAM memories are 256 bytes, 256 bytes, and 64 bytes, respectively. These maximum block-write lengths should not be exceeded. Figure 107 Example Write 0x00 to the rc_cfg register (Location 0x13E).

• The first five bits of the SPI_MEM_WR command are 00011.
• The 11-bit address of rc_cfg is 00100111110.
• The first byte sent is 00011001 or 0x19.
• The second byte sent is 00111110 or 0x3E.
• The third byte sent is 0x00. Thus, 0x193F00 is written to the part. Random Address Write MCR, BBRAM, and packet RAM memory locations can be written to in random address format using the SPI_MEMR_WR command. The SPI_MEMR_WR command code is 00001xxxb, where xxxb represent Bits[10:8] of the 11-bit address. The lower eight bits of the address should follow this command and then the data byte to be written to the address. The lower eight bits of the next address are entered followed by the data for that address until all required addresses within that block are written, as shown in Figure 108. Note that the SPI_MEMR_WR command facilitates the modification of individual elements of a packet in RX_BUFFER and TX_BUFFER without the need to download and upload an entire packet. The address location of a particular byte in RX_BUFFER and TX_BUFFER in the packet RAM is determined by adding the relative location of a byte to Address Pointer rx_pkt_base (Register rxpb; 0x315[7:0]) or Address Pointer tx_pkt_base (Register txpb; 0x314[7:0]), respectively. Program RAM Write The program RAM can only be written to using the memory block write, as illustrated in Figure 109. The SPI_PRAM_WR command is 0x1E. The program RAM is organized in eight pages with a length of 256 bytes each. The code module must be stored in the program RAM starting from Address 0x0000, or Address 0x00 in Page 0. The current program RAM page is selected with Register prampg, Field pram_page (0x313[3:0]). Prior to uploading the program RAM, the radio controller code module must be divided into blocks of 256 bytes commensurate with the size of the program RAM pages. Each 256-byte block is uploaded into the currently selected program RAM page using the SPI_PRAM_WR command. Figure 109 illustrates the sequence required for uploading a code block of 256 bytes to a PRAM page. The SPI_PRAM_WR command code is followed by Address Byte 0x00 to align the code block with the base address of the program RAM page. Figure 110 shows the overall upload sequence. With the exception of the last page written to the program RAM, all pages must be filled with 256 bytes of module code. READING FROM THE ADF7242 Block Read Command SPI_PKT_RD provides pointer-based read access from the packet RAM. The SPI_PKT_RD command is 0x30. The address of the location to be read is calculated from the base address in Register rxpb, Field rx_pkt_base plus an index. The index is zero for the first readback word. It is auto-incremented for each consecutive SPI_NOP command. The first data byte following a SPI_PKT_RD command is invalid and should be ignored. Figure 111 shows the access sequence for Command SPI_PKT_RD. The SPI_MEM_RD command can be used to perform a block read of MCR, BBRAM, and packet RAM memory locations. The SPI_MEM_RD command code is 00111xxxb, where xxxb represent Bits[10:8] of the first 11-bit address. This command is followed by the remaining eight bits of the address to be read and then two SPI_NOP commands (dummy byte). The first byte available after writing the address should be ignored, with the second byte constituting valid data. If more than one data byte is to be read, the read address is automatically incremented for subsequent SPI_NOP commands sent. See Figure 112 for more details. Random Address Read MCR, BBRAM, and Packet RAM memory locations can be read from in a nonsequential manner using the SPI_MEMR_RD command. The SPI_MEMR_RD command code is 00101xxxb, where xxxb represent Bits[10:8] of the 11-bit address. This command is followed by the remaining eight bits of the address to be written and then two SPI_NOP commands (dummy byte).

Rev. 0 | Page 80 of 108 DOWNLOADABLE FIRMWARE MODULES The program RAM of the ADF7242 can be used to store firmware modules for the on-chip processor that provide extra functionality. The executable code for these firmware modules and details on their functionality are available from Analog Devices. See the Writing to the ADF7242 section for details on how to download these firmware modules to program RAM.

(0x3CB) and Register irq_src1(0x3CC). registers correspond to the different interrupts. host MCUs that may not have interrupt pins available. individually and facilitates hierarchical interrupt processing. after a power-on-reset event or wake-up from the sleep state. should be cleared during the initialization phase. Figure 114. Interrupt Controller

Table 48. Bit Locations in the Interrupt Source Register 7 Reserved Don’t care; set mask to 0. 6 Reserved Don’t care; set mask to 0. 5 Reserved Don’t care; set mask to 0. 4 tx_pkt_sent TX packet transmission complete. 3 rx_pkt_rcvd Packet received in RX_BUFFER. 2 tx_sfd SFD/SWD has been transmitted. 1 rx_sfd SFD/SWD has been detected. 0 cca_complete CCA_RESULT in status word is valid. Table 49. Bit Locations in the Interrupt Source Register 7 Reserved Don’t care; set mask to 0. 6 Reserved Don’t care; set mask to 0. 2 wakeup Timer has timed out. 1 powerup Chip is ready for access. 0 Reserved Don’t care; set mask to 0. has been received and is available in RX_BUFFER. when in IEEE 802.15.4-2006 or GFSK/FSK packet mode. the RX state in either IEEE 802.15.4 or GFSK/FSK mode. indicates that the CCA_RESULT flag in the status word is valid. of the RC_READY flag in the status word. powerup are automatically set on exit from the sleep state. being pulled low or by a timeout event.

Figure 115. Typical ADF7242 Application Circuit Using Antenna Diversity

Figure 116. Typical ADF7242 Application Circuit with DSP Using Antenna Diversity

Figure 117. Typical ADF7242 Application Circuit with External LNA and External PA

Figure 118. Typical ADF7242 Application Circuit with Discrete External PA

as RC_CONTROLLED must be programmed in the idle state only. Reset values are shown in decimal notation. Table 50. Register Map Overview 0x353 vco_band_ovrw R/W Overwrite value for the VCO frequency band. 0x354 vco_idac_ovrw R/W Overwrite value for the VCO bias current DAC.

Rev. 0 | Page 88 of 108 Address Register Name Access Mode Description 0x381 vco_idac_rb R Readback of the VCO bias current DAC after calibration 0x389 iirf_cfg R/W BB filter decimation rate 0x38B dm_cfg1 R/W Postdemodulator filter bandwidth 0x395 rxcal0 R/W Receiver baseband filter calibration word, LSB 0x396 rxcal1 R/W Receiver baseband filter calibration word, MSB 0x39B rxfe_cfg R/W Receive baseband filter bandwidth and LNA selection 0x3A7 pa_rr R/W PA ramp rate 0x3A8 pa_cfg R/W PA output stage current control 0x3A9 extpa_cfg R/W External PA bias DAC configuration 0x3AA extpa_msc R/W External PA interface circuit configuration 0x3AE adc_rbk R ADC readback 0x3B2 agc_cfg1 R/W AGC configuration parameters 0x3B4 agc_max R/W AGC configuration parameters 0x3B6 agc_cfg2 R/W AGC configuration parameters 0x3B7 agc_cfg3 R/W AGC configuration parameters 0x3B8 agc_cfg4 R/W AGC configuration parameters 0x3B9 agc_cfg5 R/W AGC configuration parameters 0x3BA agc_cfg6 R/W AGC configuration parameters 0x3BC agc_cfg7 R/W AGC configuration parameters 0x3BF ocl_cfg0 R/W OCL system parameters 0x3C4 ocl_cfg1 R/W OCL system parameters 0x3C7 irq1_en0 R/W Interrupt Mask Set Bits[7:0] of [15:0] for IRQ1 0x3C8 irq1_en1 R/W Interrupt Mask Set Bits[15:8] of [15:0] for IRQ1 0x3C9 irq2_en0 R/W Interrupt Mask Set Bits[7:0] of [15:0] for IRQ2 0x3CA irq2_en1 R/W Interrupt Mask Set Bits[15:8] of [15:0] for IRQ2 0x3CB irq1_src0 R/W Interrupt Source Bits[7:0] of [15:0] for IRQ 0x3CC irq1_src1 R/W Interrupt Source Bits[15:8] of [15:0] for IRQ 0x3D2 ocl_bw0 R/W OCL system parameters 0x3D3 ocl_bw1 R/W OCL system parameters 0x3D4 ocl_bw2 R/W OCL system parameters 0x3D5 ocl_bw3 R/W OCL system parameters 0x3D6 ocl_bw4 R/W OCL system parameters 0x3D7 ocl_bws R/W OCL system parameters 0x3E0 ocl_cfg13 R/W OCL system parameters 0x3E3 gp_drv R/W GPIO and SPI I/O pads drive strength configuration 0x3E6 bm_cfg R/W Battery monitor threshold voltage setting 0x3F0 tx_fsk_test R/W TX GFSK/FSK SPORT test mode configuration 0x3F3 preamble_num_validate R/W Preamble validation 0x3F4 sfd_15_4 R/W Option to set nonstandard SFD 0x3F7 afc_cfg R/W AFC mode and polarity configuration 0x3F8 afc_ki_kp R/W AFC ki and kp 0x3F9 afc_range R/W AFC range 0x3FA afc_read R/W AFC frequency error readback

Table 51. 0x100: ext_ctrl [7] pa_shutdown_mode R/W 0 PA shutdown mode. [6:5] Reserved R/W 0 Reserved, set to default. 4 rxen_en R/W 0 1: RXEN_GP6 is set high while in the RX state; otherwise, it is low. 3 txen_en R/W 0 1: TXEN_GP5 is set high while in the TX state; otherwise, it is low. Register gp_cfg for restrictions. 2 extpa_auto_en R/W 0 1: RC enables external PA controller while in the TX state. 0: Register pd_aux, Bit extpa_bias_en (0x31E[4]) is under user control. [1:0] Reserved R/W 0 Reserved, set to default. Table 52. 0x102: fsk_preamble 0x10E. Refer to the Transmitter in GFSK/FSK Mode section for details. Table 53. 0x105: cca1 Table 54. 0x106: cca2 [7:3] Reserved R/W 0 Reserved, set to default. 2 continuous_cca R/W 0 0: continuous CCA off. 1: generate a CCA interrupt every 128 μs. 1 rx_auto_cca R/W 0 0: automatic CCA off. 1: generate a CCA interrupt 128 μs after entering the RX state. 0 Reserved R/W 0 Reserved, set to default.

Table 55. 0x107: buffercfg 7 trx_mac_delay R/W 0 0: tx_mac_delay (0x10A[7:0]) and rx_mac_delay (0x109[7:0]) enabled. 1: tx_mac_delay (0x10A[7:0]) and rx_mac_delay (0x109[7:0]) disabled.

6 Reserved R/W 0 Reserved, set to default

[5:4] tx_buffer_mode RW 0 In IEEE 802.15.4-2006 mode. 0: return to PHY_RDY after frame in TX_BUFFER is transmitted once. 3 auto_tx_to_rx_turnaround R//W 0 0: as per tx_buffer_mode setting. 1: automatically goes to RX after TX data transmitted. 2 auto_rx_to_tx_turnaround R/W 0 0: as per rx_buffer_mode setting. 1: automatically goes to TX after RX packet received. returns to PHY_RDY state after reception of first frame. 2: new frames not written to buffer. Table 56. 0x108: pkt_cfg [7:5] Reserved R/W 0 Reserved, set to default. 4 addon_en R/W 0 0: firmware add-on module disabled. 1: firmware add-on module enabled; module must be loaded prior to setting this bit. 3 skip_synt_settle R/W 0 0: the RF frequency synthesizer calibration and settling phase is performed. Configuration and Operation section. [2:1] Reserved R/W 2 Reserved, set to default. 0 auto_fcs_off R/W 0 In IEEE 802.15.4-2006 and GFSK/FSK packet mode, the rx_pkt_rcvd interrupt is asserted. 1: receive operation—received FCS is stored in RX_BUFFER without validation. Transmit operation—FCS field in TX_BUFFER is transmitted. 0: receive operation—CRC automatically validated. 1: receive operation—received CRC is stored in RX_BUFFER without validation. Transmit operation—CRC field in TX_BUFFER is transmitted. Table 57. 0x109: delaycfg0 SFD search and for start of RSSI measurement window. GFSK mode: programmable delay from issue of RC_RX command to SWD search. Programmable in steps of 1 μs in both modes.

Table 58. 0x10A: delaycfg1 of RC_TX command to entering TX state. Programmable in steps of 1 μs in both modes. Table 59. 0x10B: delaycfg2 [7:0] mac_delay_ext R/W 0 Programmable MAC delay extension. Programmable in steps of 4 μs. Table 60. 0x10C: sync_word0 Table 61. 0x10D: sync_word1 Table 62. 0x10E: sync_word2 Table 63. 0x10F: sync_config 7 Reserved R/W 0 Reserved, set to default. [6:5] sync_tol R/W 0 Number of bit mismatches allowed: 0 to 3. [4:0] sync_len R/W 24 Synchronization word length, which can be from 0 to 24. 0: sync word detection disabled. Table 64. 0x111: fsk_preamble_config 6 skip_syncword_detect_sport R/W 0 Bypass SFD detection (GFSK/FSK SPORT mode only). 0: perform sync word detection. 1: skip sync word detection. 5 fsk_agc_lock_after_preamble R/W 0 Lock AGC after preamble (GFSK/FSK packet/SPORT modes only). 4 skip_preamble_detect_qual R/W 0 Bypass preamble detection and qualification; only search for SWD . 0: enable preamble detection + qualification. 1: disable preamble detection + qualification. 0xC Enabled. 0 bit-pairs in error allowed in 12 bit-pairs. 0xB Enabled. 1 bit-pair in error allowed in 12 bit-pairs. 0xA Enabled. 2 bit-pairs in error allowed in 12 bit-pairs. 0x9 Enabled. 3 bit-pairs in error allowed in 12 bit-pairs. 0x1 Enabled. 11 bit-pairs in error allowed in 12 bit-pairs. 0x0 Preamble qualification disabled.

Table 65. 0x13E: rc_cfg 2: IEEE 802.15.4-2006 receive SPORT mode. Table 66. 0x300: ch_freq0 Table 67. 0x301: ch_freq1 Table 68. 0x302: ch_freq2 Table 69. 0x304: tx_fd [7:6] Reserved R/W 0 Reserved, set to default. [5:0] tx_freq_dev R/W 50 Transmit frequency deviation = tx_freq_dev × 10 kHz. IEEE 802.15.4: use default setting of 50. Table 70. 0x305: dm_cfg0 [7] Reserved R/W 0 Reserved, set to default.

Table 71. 0x306: tx_m [7:2] RC_CONTROLLED R/W 0 Controlled by radio controller. 1 gauss_filt R/W 0 1: GFSK, 0: FSK. Table 72. 0x30C: rrb [7:0] rssi_readback R 0 Receive input power in dBm; signed twos complement. Table 73. 0x30D: lrb [7:0] sqi_readback R 0 Signal quality indicator readback value. Table 74. 0x30E: dr0 [7:0] data_rate_high R/W 78 Data rate: 256 × data_rate_high × 100 bps + dr1. Table 75. 0x30F: dr1 [7:0] data_rate_low R/W 32 Data rate: data_rate_low × 100 bps + dr0. Table 76. 0x313: prampg [7:4] Reserved R/W 0 Reserved, set to default. [3:0] pram_page R/W 0 Program PRAM page. Table 77. 0x314: txpb [7:0] tx_pkt_base R/W 128 Base address of TX_BUFFER in packet RAM. Table 78. 0x315: rxpb [7:0] rx_pkt_base R/W 0 Base address of RX_BUFFER in packet RAM.

Table 79. 0x316: tmr_cfg0 [7:3] Reserved R/W 0 Reserved, set to default. [2:0] timer_prescal R/W 0 Divider factor for XTO32K or RCO. Table 80. 0x317: tmr_cfg1 7 Reserved R/W 0 Reserved, set to default. Refer to note in Register tmr_cfg0. [2:1] Reserved R/W 0 Reserved, set to default. 0 wake_on_timeout R/W 0 1: enable, 0: disable wake-up on timeout event. Table 81. 0x318: tmr_rld0 [7:0] timer_reload[15:8] R/W 0 Timer reload value, Bits[15:8] of [15:0]. Table 82. 0x319: tmr_rld1 [7:0] timer_reload[7:0] R/W 0 Timer reload value, Bits[7:0] of [15:0]. Refer to note in Register tmr_rld0. Table 83. 0x31A: tmr_ctrl [7:2] Reserved R/W 0 Reserved, set to default. 1 wuc_rc_osc_cal R/W 0 1: enable. 0: disable 32 kHz RC oscillator calibration. 0 wake_timer_flag_reset R/W 0 Timer flag reset.

Table 84. 0x31B: wuc_32khzosc_status [7:6] Reserved R 0 Reserved, set to default. 4 xosc32_ready R 0 32 kHz crystal oscillator (only valid if sleep_config (0x317[6:3])= 4 or 5). 3 Reserved R 0 Reserved, set to default. 2 wuc_porflag R 0 Chip cold start event registration. 0 Reserved R 0 Reserved, set to default. Table 85. 0x31E: pd_aux 7 Reserved R/W 0 Reserved, set to default. 6 RC_CONTROLLED R/W 0 Controlled by radio controller. 5 battmon_en R/W 0 1: enable. 4 extpa_bias_en R/W 0 1: enable. 0: disable external PA biasing circuit. [3:0] RC_CONTROLLED R/W 0 Controlled by radio controller. Table 86. 0x32C: gp_cfg [7:0] gpio_config R/W 0 0: IRQ1, IRQ2 functionality. Register gp_out, Bit gpio_dout[6] controls RXEN output. Register gp_out, Bit gpio_dout[5] controls TXEN output. 1, 4: TRCLK and Data pins active in RX, without gating by frame detection. 2, 5: TRCLK and Data pins activity gated by preamble detection. 3, 6: TRCLK and Data pins activity gated by synchronization word detection. Register gp_out, Bit gpio_dout[5] controls TXEN output. 103: IRQ1, DR, DT, IRQ2, TRCLK functionality. Register gp_out, Bit gpio_dout[6] controls RXEN output. Register gp_out, Bit gpio_dout[5] controls TXEN output.

Table 87. 0x32D: gp_out [7:0] gpio_dout R/W 0 GPIO output value if Register gp_cfg, Field gpio_config = 4. gpio_dout[7:0] = GP7 to GP0. Bit gpio_dout[6] is controlled by radio controller. Bit gpio_dout[5] is controlled by radio controller. Table 88. 0x335: synt [7:0] lock_time R/W 23 Synthesizer locking timeout period (46 μs). 1 LSB = 2 μs. Table 89. 0x33D: rc_cal_cfg [7:2] Reserved R/W 15 Reserved, set to default. Table 90. 0x353: vco_band_ovrw 1 and Register vco_cal_cfg, Field skip_vco_cal = 15. Table 91. 0x354: vco_idac_ovrw Field skip_vco_cal = 15 and vco_idac_ovrw_en = 1. Table 92. 0x355: vco_ovrw_cfg [7:2] Reserved R/W 2 Reserved, set to default. Table 93. 0x36E: pa_bias 7 Reserved R/W 0 Reserved, set to default. [6:1] pa_bias_ctrl R/W 55 Set to 63 if maximum PA output power of 4.8 dBm is required. 0 Reserved R/W 1 Reserved, set to default.

Table 94. 0x36F: vco_cal_cfg [7:4] Reserved R/W 0 Reserved, set to default. [3:0] skip_vco_cal R/W 9 9: do not skip VCO calibration. Table 95. 0x371: xto26_trim_cal [7:6] Reserved R/W 0 Reserved, set to default. [2:0] Reserved R/W 0 Reserved, set to default. Table 96. 0x381: vco_band_rb Table 97. 0x381: vco_idac_rb Table 98. 0x389: iirf_cfg [7:5] Reserved R/W 0 Reserved, set to default. For IEEE 802.15.4-2006: set to default. fs1 = 13 MHz/(2iir_stage1_bw). For IEEE 802.15.4-2006: set to default.

Table 99. 0x38B: dm_cfg1 [7:0] postdemod_bw R/W 200 Post demodulator filter BW= postdemod_bw × 15 kHz. Table 100. 0x395: rxcal0 [7:0] dcap_ovwrt_low R/W 0 RXBB filter tuning overwrite word, LSB. Table 101. 0x396: rxcal1 [7:2] Reserved R/W 2 Reserved, set to default. 1 dcap_ovwrt_en R/W 0 RXBB filter tuning overwrite word enable. 0 dcap_ovwrt_high R/W 0 RXBB filter tuning overwrite word, MSB. Table 102. 0x39B: rxfe_cfg [7:5] Reserved R/W 0 Reserved, set to default. For IEEE 802.15.4-2006 mode: set to default. 62.5 kbps to 1000 kbps: set to 6. Table 103. 0x3A7: pa_rr [7:3] Reserved R/W 0 Reserved, set to default. 2pa_rr.pa_ramp_rate × 2.4 ns per PA power step.

Table 104. 0x3A8: pa_cfg 7 Reserved R/W 0 Reserved, set to default. [6:5] Reserved R/W 0 Set to default. [4:0] pa_bridge_dbias R/W 13 Set to 21 if output power of 4.8 dBm is required from PA. Table 105. 0x3A9: extpa_cfg [7:5] Reserved R/W 0 Reserved, set to default. PABIAOP_ATB4 pin DAC current = 80 μA − 2.58 μA × extpa_bias. PAVSUP_ATB3 pin servo current set point = 22 mA − 0.349 mA × extpa_bias. Table 106. 0x3AA: extpa_msc Nominal power step size 2 dB per LSB. 3 extpa_bias_src R/W 0 0: select RBIAS-referred reference current. 1: select band gap-referred reference current. 0: PAVSUP_ATB3 = on; PABIAOP_ATB4 = floating. 1: PAVSUP_ATB3 = on; PABIAOP_ATB4 = current source. 2: PAVSUP_ATB3 = on; PABIAOP_ATB4 = current sink. 3: PAVSUP_ATB3 = off; PABIAOP_ATB4 = current source. 4: PAVSUP_ATB3 = off; PABIAOP_ATB4 = current sink. 5: PAVSUP_ATB3 = on; PABIAOP_ATB4 = positive servo output. 6: PAVSUP_ATB3 = on; PABIAOP_ATB4 = negative ser vo output. Table 107. 0x3AE: adc_rbk [5:0] adc_out R 0 ADC output code. Table 108. 0x3B2: agc_cfg1 7 Reserved R/W 0 Reserved, set to default. [6:5] agc_lna_hyst R/W 1 Hysteresis in terms of PGA attenuation steps for LNA gain transitions. [4:1] agc_lna_thres R/W 8 Sets number of PGA attenuation steps prior to first LNA attenuation step. 0 agc_lock R/W 0 0: enable, 1: freeze AGC. Table 109. 0x3B4: agc_max [7:6] Reserved R/W 2 Reserved, set to default. mode when this threshold is exceeded. [2:0] Reserved R/W 0 Reserved, set to default.

Table 110. 0x3B6: agc_cfg2 7 Reserved R/W 0 Reserved, set to default. [6:0] agc_thres_hi R/W 46 AGC upper RSSI trigger threshold. For IEEE 802.15.4-2006: set to default. Table 111. 0x3B7: agc_cfg3 7 Reserved R/W 0 Reserved, set to default. [6:0] agc_target R/W 35 AGC RSSI active state target value. For IEEE 802.15.4-2006: set to default. Table 112. 0x3B8: agc_cfg4 7 Reserved R/W 0 Reserved, set to default. [6:0] agc_thres_lo R/W 24 AGC lower RSSI trigger threshold. For IEEE 802.15.4-2006: set to default. Table 113. 0x3B9: agc_cfg5 [7:5] Reserved R/W 0 Set to 0. [4:2] rssi_offs R/W 4 RSSI offset adjust, rssi_offs is added to Register rrb, Field rssi_readback. section for further details. Table 114. 0x3BA: agc_cfg6 [7:6] Reserved R/W 0 Reserved, set to default. [5:3] agc_filt2_tavg2 R/W 5 AGC postfilter averaging time. For IEEE 802.15.4-2006: per default. [2:0] agc_filt2_tavg1 R/W 5 AGC postfilter averaging time for LNA transition. For IEEE 802.15.4-2006: per default. Table 115. 0x3BC: agc_cfg7 7 Reserved R/W 0 Reserved, set to default. [6:3] agc_ndelay_steady R/W 15 AGC agc_steady delay counter. [2:0] agc_egain_exp R/W 1 AGC integrator gain.

Table 116. 0x3BF: ocl_cfg0 [7:2] Reserved R/W 0 Reserved, set to default. 0: disable OCL wide bandwidth mode after LNA gain changes. 0 Reserved R/W 0 Reserved, set to default. Table 117. 0x3C4: ocl_cfg1 [7:0] ocl_fsk_lock_timeout R/W 5 For IEEE 802.15.4-2006: per default. For GFSK/FSK: set to 7. Table 118. 0x3C7: irq1_en0 5 batt_alert R/W 0 Battery monitor interrupt. 4 por R/W 0 Power-on reset event. 3 rc_ready R/W 0 Radio controller ready to accept new command. 2 wakeup R/W 0 Timer has timed out. 1 powerup R/W 1 Chip is ready for access. Table 119. 0x3C8: irq1_en1 4 tx_pkt_sent R/W 0 Packet transmission complete. 3 rx_pkt_rcvd R/W 0 Packet received in RX_BUFFER. 2 tx_sfd R/W 0 SFD/SWD was transmitted. 1 rx_sfd R/W 0 SFD/SWD was detected. 0 cca_complete R/W 0 CCA_RESULT in status word is valid. Table 120. 0x3C9: irq2_en0 5 batt_alert R/W 0 Battery monitor interrupt. 4 por R/W 0 Power-on reset event. 3 rc_ready R/W 0 Radio controller ready to accept new command. 2 wakeup R/W 0 Timer has timed out. 1 powerup R/W 1 Chip is ready for access.

Table 121. 0x3CA: irq2_en1 4 tx_pkt_sent R/W 0 Packet transmission complete. 3 rx_pkt_rcvd R/W 0 Packet received in RX_BUFFER. 2 tx_sfd R/W 0 SFD/SWD was transmitted. 1 rx_sfd R/W 0 SFD/SWD was detected. 0 cca_complete R/W 0 CCA_RESULT in status word is valid. Table 122. 0x3CB: irq_src0 5 batt_alert R/W 0 Battery monitor interrupt. 4 por R/W 0 Power-on reset event. 3 rc_ready R/W 0 Radio controller ready to accept new command. 2 wakeup R/W 0 Timer has timed out. 1 powerup R/W 0 Chip is ready for access. Table 123. 0x3CC: irq_src1 4 tx_pkt_sent R/W 0 Packet transmission complete. 3 rx_pkt_rcvd R/W 0 Packet received in RX_BUFFER. 2 tx_sfd R/W 0 SFD/SWD was transmitted. 1 rx_sfd R/W 0 SFD/SWD was detected. 0 cca_complete R/W 0 CCA_RESULT in status word is valid. Table 124. 0x3D2: ocl_bw0 [7:5] Reserved R/W 0 Reserved, set to default. [4:0] ocl_bw0 R/W 27 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 26. Table 125. 0x3D3: ocl_bw1 [7:5] Reserved R/W 0 Reserved, set to default. [4:0] ocl_bw1 R/W 26 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 25. Table 126. 0x3D4: ocl_bw2 [7:5] Reserved R/W 0 Reserved, set to default. [4:0] ocl_bw2 R/W 2 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 30.

Table 127. 0x3D5: ocl_bw3 [7:5] Reserved R/W 0 Reserved, set to default. [4:0] ocl_bw3 R/W 3 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 30. Table 128. 0x3D6: ocl_bw4 [7:5] Reserved R/W 0 Reserved, set to default. [4:0] ocl_bw4 R/W 2 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 30. Table 129. 0x3D7: ocl_bws [7:5] Reserved R/W 0 Reserved, set to default. [4:0] ocl_bw R/W 0 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 0. Table 130. 0x3E0: ocl_cfg13 [7:2] Reserved R/W 60 Reserved, set to default. 1 ocl_sosi_en R/W 1 For IEEE 802.15.4-2006: set to default. For GFSK/FSK: set to 0. 0 Reserved R/W 0 Reserved, set to default. Table 131. 0x3E3: gp_drv [7:4] Reserved R/W 0 Reserved, set to default. [3:2] gpio_slew R/W 0 GPIO and SPI slew rate. [1:0] gpio_drive R/W 0 GPIO and SPI drive strength. Table 132. 0x3E6: bm_cfg 7:5] Reserved R/W 0 Reserved, set to default.

1.7 V + 62 mV × battmon_voltage; the batt_alert interrupt is asserted when

VDD_BAT drops below the trip voltage. Table 133. 0x3F0: tx_fsk_test [7:4] Reserved R/W 2 Reserved, set to default. 3 zero_only R/W 0 Transmit 0 only (fCH − fDEV) in GFSK/FSK SPORT mode. 2 one_only R/W 0 Transmit 1 only (fCH + fDEV) in GFSK/FSK SPORT mode. 1 carrier_only R/W 0 Transmits unmodulated tone at the programmed frequency fCH. 0 Reserved R/W 0 Reserved, set to default.

Table 134. 0x3F3: preamble_num_validate [7] Reserved R/W 0 Reserved, set to default. [6:0] num_preamble_bytes R/W 5 Number of preamble bytes required for preamble validation. Table 135. 0x3F4: sfd_15_4 [7:4] sfd_symbol_2 R/W 10 Symbol 2 of SFD note: IEEE 802.15.4-2006 requires SFD1 = 10. [3:0] sfd_symbol_1 R/W 7 Symbol 1 of SFD note: IEEE 802.15.4-2006 requires SFD1 = 7. Table 136. 0x3F7: afc_cfg [7:3] Reserved R/W 0 Reserved, set to default. [2] afc_polarity R/W 0 Set AFC polarity. Set to 1. [1:0] afc_mode R/W 0 00: lock AFC. 11: lock AFC on preamble detection. Table 137. 0x3F8: afc_ki_kp [7:4] afc_kp R/W 0 Sets the AFC PI controller proportional gain. [3:0] afc_ki R/W 0 Sets the AFC PI controller integral gain. Table 138. 0x3F9: afc_range bandwidth. AFC pull-in range is ±max_afc_range in kHz. Table 139. 0x3FA: afc_read [7:0] afc_freq_error R/W 0 Frequency error readback. Frequency error: 1 kHz/LSB.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 119. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Rev. 0 | Page 106 of 108 NOTES

Rev. 0 | Page 107 of 108 NOTES

Rev. 0 | Page 108 of 108 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08912-0-7/10(0)