ADF7025BCPZ

ADF7025 AD | Alldatasheet

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Technical content

Rev. A Information furnished by Analog D evices is believed to b e accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Low power, zero-IF RF transceiver Frequency bands

431 MHz to 464 MHz

862 MHz to 870 MHz

902 MHz to 928 MHz

9.6 kbps to 384 kbps, FSK 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 63 steps Receiver sensitivity −104.2 dBm at 38.4 kbps, FSK −100 dBm at 172.8 kbps, FSK −95.8 dBm at 384 kbps, FSK Low power consumption 19 mA in receive mode 28 mA in transmit mode (10 dBm output) On-chip VCO and Fractional-N PLL On-chip, 7-bit ADC and temperature sensor Digital RSSI Integrated TRx switch Leakage current < 1 µA in power-down mode

APPLICATIONS

Remote control/security systems Wireless metering Keyless entry Home automation FUNCTIONAL BLOCK DIAGRAM Tx/Rx CONTROL AGC CONTROL FSK DEMODULATOR DATA SYNCHRONIZERRSSI 7-BIT ADC GAIN DIV R SERIAL PORT RFOUT OFFSET CORRECTION OFFSET CORRECTION LNA VCO PFDCP OSC1 OSC2 DIVIDERS/ MUXING N/N+1DIV P MUX TEMP SENSOR RING OSC CLK DIV CLKOUT TEST MUX VCOIN CPOUT BIAS LDO(1:4) MUXOUTADCINRSET CREG(1:4) RLNA RFIN RFINB SLE SDATA CE DATA CLK SREAD SCLK INT/LOCK DATA I/O FSK MOD CONTROL Σ-∆ MODULATOR LP FILTER 05542-001 Figure 1.

Rev. A | Page 2 of 44 TABLE OF CONTENTS

REVISION HISTORY

2/06—Rev. 0 to Rev. A 1/06—Revision 0: Initial Version

Rev. A | Page 3 of 44 GENERAL DESCRIPTION The ADF7025 is a low power, highly integrated FSK transceiver. It is designed for operation in the license–free ISM bands of 433 MHz, 863 MHz to 870 MHz, and 902 MHz to 928 MHz. The ADF7025 can be used for applications operating under the European ETSI EN300-220 or the North American FCC (Part 15) regulatory standards. The ADF7025 is intended for wideband, high data rate applications with deviation frequencies from 100 kHz to 750 kHz and data rates from 9.6 kbps to 384 kbps. A complete transceiver can be built using a small number of external discrete components, making the ADF7025 very suitable for price-sensitive and area-sensitive applications. The transmit section contains a VCO and low noise Fractional-N PLL with output resolution of <1 ppm. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 0.3 dB steps from −16 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A zero-IF architecture is used in the receiver, minimizing power consumption and the external component count, while avoiding the need for image rejection. The baseband filter (low-pass) has programmable bandwidths of ±300 kHz, ±450 kHz, and ±600 kHz. A high-pass pole at ~60 kHz eliminates the problem of dc offsets that is characteristic of zero-IF architecture. The ADF7025 supports a wide variety of programmable features, including Rx linearity, sensitivity, and filter bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. An on-chip ADC provides readback of an integrated tempera- ture sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

Rev. A | Page 4 of 44 SPECIFICATIONS VDD = 2.3 V to 3.6 V , GND = 0 V , TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V , TA = 25°C. All measurements are performed using the EV AL-ADF7025DB1 using PN9 data sequence, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions RF CHARACTERISTICS Frequency Ranges (Direct Output) 862 870 MHz VCO adjust = 0, VCO bias = 10 902 928 VCO adjust = 3, VCO bias = 12 Frequency Ranges (Divide-by-2 Mode) 431 464 MHz See conditions for direct output Phase Frequency Detector Frequency RF/256 24 MHz TRANSMISSION PARAMETERS Data Rate FSK 9.6 384 kbps FSK Frequency Deviation 100 311.89 kHz PFD = 10 MHz, direct output 100 748.54 kHz PFD = 24 MHz, direct output 100 374.27 kHz PFD =24MHz, divide-by-2 mode Deviation Frequency Resolution 221 Hz PFD = 3.625 MHz Gaussian Filter BT 0.5 Transmit Power1 −20 +13 dBm VDD = 3.0 V, TA = 25°C Transmit Power Variation vs. Temperature ±1 dB From −40°C to +85°C Transmit Power Variation vs. VDD ±1 dB From 2.3 V to 3.6 V at 915 MHz, TA = 25°C Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz, 3 V, TA = 25°C Programmable Step Size −20 dBm to +13 dBm 0.3125 dB Spurious Emissions Integer Boundary −55 dBc 50 kHz loop B/W Reference −65 dBc Harmonics Second Harmonic −27 dBc Unfiltered conductive Third Harmonic −21 dBc All Other Harmonics −35 dBc VCO Frequency Pulling 30 kHz rms DR = 9.6 kbps Optimum PA Load Impedance 39 + j61 Ω FRF = 915 MHz 48 + j54 Ω FRF = 868 MHz 54 + j94 Ω FRF = 433 MHz RECEIVER PARAMETERS FSK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz, LNA and PA matched separately2 Sensitivity at 38.4 kbps −104.2 dBm FDEV = 200 kHz, LPF B/W = ±300kHz Sensitivity at 172.8 kbps −100 dBm FDEV = 200 kHz, LPF B/W = ±450kHz Sensitivity at 384 kbps −95.8 dBm FDEV = 450kHz, LPF B/W = ±600kHz Baseband Filter (Low-Pass) Bandwidths Programmable ±300 kHz ±450 kHz ±600 kHz LNA and Mixer, Input IP3 Enhanced Linearity Mode +6.8 dBm Low Current Mode −3.2 dBm High Sensitivity Mode −35 dBm Pin = −20 dBm, 2 CW interferers FRF = 915 MHz, f1 = FRF + 3 MHz F2 = FRF + 6 MHz, maximum gain Rx Spurious Emissions3 −57 dBm <1 GHz at antenna input −47 dBm >1 GHz at antenna input

Rev. A | Page 5 of 44 Parameter Min Typ Max Unit Test Conditions CHANNEL FILTERING Adjacent Channel Rejection (Offset = ±1 × LP Filter BW Setting) 27 dB Second Adjacent Channel Rejection (Offset = ±2 × LP Filter BW Setting) 40 dB Desired signal (38.4 kbps DR, 200 kHz FDEV, ±300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3 Third Adjacent Channel Rejection (Offset = ±3 × LP Filter BW Setting) 43 dB Co-Channel Rejection −2 +24 dB Maximum rejection measured with CW interferer at center of channel Wideband Interference Rejection 70 dB Swept from 100 MHz to 2 GHz, measured as channel rejection BLOCKING ±1 MHz dB ±2 MHz 51 dB ±10 MHz 64 dB Desired signal (38.4 kbps DR, 200 kHz FDEV, ±300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3 Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10−3 LNA Input Impedance 24 − j60 Ω FRF = 915 MHz, RFIN to GND 26 − j63 Ω FRF = 868 MHz 71 − j128 Ω FRF = 433 MHz RSSI Range at Input −100 to −36 dBm Linearity ±2 dB Absolute Accuracy ±3 dB Response Time 150 µs PHASE-LOCKED LOOP VCO Gain 65 MHz/V 902 MHz to 928 MHz band, VCO adjust = 3, VCO_BIAS_SETTING = 12

83 MHz/V 862 MHz to 870 MHz band,

VCO adjust = 0, VCO_BIAS_SETTING = 10 Phase Noise (In-Band) −89 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 868 MHz, VCO_BIAS_SETTING = 10 Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 868MHz PLL Settling Time 40 µs Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50kHz REFERENCE INPUT Crystal Reference 3.625 24 MHz External Oscillator 3.625 24 MHz Load Capacitance 33 pF Crystal Start-Up Time 1.0 ms Using 33 pF load capacitors Input Level CMOS levels TIMING INFORMATION Chip Enabled to Regulator Ready 10 µs CREG = 100 nF Crystal Oscillator Startup Time 1 ms With 19.2 MHz XTAL Tx to Rx Turnaround Time 150 µs + (5 × TBIT) Time to synchronized data, includes AGC settling

Rev. A | Page 6 of 44 Parameter Min Typ Max Unit Test Conditions LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 µA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH DVDD − 0.4 V IOH = 500 µA Output Low Voltage, VOL 0.4 V IOL = 500 µA CLKOUT Rise/Fall 5 ns CLKOUT Load 10 pF TEMPERATURE RANGE, TA −40 +85 °C POWER SUPPLIES Voltage Supply VDD 2.3 3.6 V All VDD pins must be tied together Transmit Current Consumption FRF = 915 MHz, VDD = 3.0 V, PA is matched in to 50 Ω −20 dBm 14.6 mA −10 dBm 15.8 mA 0 dBm 19.3 mA 10 dBm 28 mA Receive Current Consumption Low Current Mode 19 mA High Sensitivity Mode 21 mA Power-Down Mode Low Power Sleep Mode 0.1 1 µA 1 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 2 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. 3 Follow the matching and layout guidelines in the LN section to achieve the relevant FCC/ETSI specifications. A/PA Matching

Figure 4. RxData/RxCLK Timing Diagram

Rev. A | Page 9 of 44 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND1 −0.3 V to +5 V Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 125°C MLF θJA Thermal Impedance 26°C/W Lead Temperature Soldering Vapor Phase (60 sec) 235°C Infrared (15 sec) 240°C 1 GND = CPGND = RFGND = DGND = AGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance, RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION ESD (elec trostatic dischar ge) se nsitive devic e. Electrostatic char ges as high as 4000 V r eadily ac cumulate on the human body and t est eq uipment and can dischar ge without det ection. Although this product f eatures proprietary ESD pr otection cir cuitry, permanen t dama ge may oc cur on dev ices sub jected to high ener gy electrostatic discharges. Therefore, proper ESD precautions a re recommended to a void per formance degradation or loss of functionality.

Figure 5. Pin Configuration Table 4. Pin Function Descriptions 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. and ground for regulator stability and noise rejection. to this pin. All VDD pins should be tied together. should be impedance-matched to the desired load using suitable components. See the Transmitter section. 5 RFGND Ground for Output Stage of Transmitter. input to ensure maximum power transfer. See the LNA/PA Matching section. 7 RFINB Complementary LNA Input. See the LNA/PA Matching section. 8 RLNA External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. 9 VDD4 Voltage supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. 10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance. for regulator stability and noise rejection. 12 GND4 Ground for LNA/MIXER Block. 13 to 18 MIX/FILT Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 19, 22 GND4 Ground for LNA/MIXER Block. 20, 21, 23 FILT/TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. when CE is low, and the part must be reprogrammed once CE is brought high. of the four latches. A latch is selected using the control bits. a high impedance CMOS input. 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7025 to the microcontroller. The SCLK input is used to clock each readback bit (ADC readback) from the SREAD pin. into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. A | Page 11 of 44 Pin No. Mnemonic Description 29 GND2 Ground for Digital Section. 30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. 31 VREG2 Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 32 VDD2 Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. 33 INT/LOCK Bidirectional Pin. In output mode (interrupt mode), the ADF7025 asserts the INT/LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulator lock can be asserted with minimum delay. 34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. 35 DATA CLK In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. 36 CLKOUT A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio. 37 MUXOUT This pin provides the lock_detect signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include regulator_ready, which is an indicator of the status of the serial interface regulator. 38 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. 39 OSC1 The reference crystal should be connected between this pin and OSC2. 40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 µF capacitor. 41 VREG3 Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor. 44 to 47 GND Grounds for VCO Block. 48 CVCO A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.

Figure 18. Sensitivity vs. Mod Index (Data Rate = 38.4 kbps),

been detected, this output is high with narrow low-going pulses. circuitry are powered on, drawing a total supply current of 2 mA. have CE high and the regulator voltage must be stabilized. the PLL. A typical loop filter design is shown in Figure 22. Figure 22. Typical Loop Filter Configuration frequencies, but it can cause insufficient spurious attenuation. the close-in interference resilience of the receiver. to design loop filters for the ADF7025. PLLs. This sets the minimum integer divide value to 31. Figure 23. Fractional-N PLL 870 MHz band, PFDMIN equals 3.4 MHz. required LO frequency for the receiver.

928 MHz band, it is recommended to use a VCO bias of at least

ensure correct operation under all conditions. regulator to reduce internal noise.

the minimum bias current setting is Setting 12 (0xC).

431 MHz to 464 MHz Operation

the desired RF output frequency. Figure 24. Voltage Controlled Oscillator

1 MHz away from an integer frequency, a 100 kHz loop filter

can reduce the level to less than −45 dBc.

6 R2_DB(9:14)

Figure 25. PA Configuration Select FSK using Bits R2_DB [6:8]. Figure 26. FSK Implementation to get optimum sensitivity performance from the ADF7025.

wide, excess noise degrades the receiver’s performance. 0.75 times the user’s data rate, using Bits R4_DB [6:15]. problems that exist in more traditional FSK demodulators. frequency errors of up to ±2%. frequency that is used by the FSK transmitter. Table 6. Register Settings

on the www.analog.com website. Figure 33. Typical Format of a Transmit Protocol the received bit stream in the receiver. Manchester coding can be used for the entire transmit protocol. six bits without any performance degradation. output to be frozen after preamble acquisition. the ADF7025 in either Tx or Rx mode after CE is brought high. particular application, such as setting up sync byte detection. Table 7. Minimum Register Writes Required for Tx/Rx Setup

1 Register 9 should be programmed in receive mode in order to set the

recommended AGC threshold settings (low = 15, high = 79). Figure 34. ADuC84X to ADF7025 Connection Diagram Figure 35. BF533 to ADF7025 Connection Diagram

Figure 36. Rx Programming Sequence and Timing Diagram Table 8. Power-Up Sequence Description type and the load capacitance specified. 32 × 1/SPI_CLK Time to write to a single register. Maximum SPI_CLK is 25 MHz. between phase noise performance and power-up time. 5-bit transitions to acquire sync and is usually covered by the preamble. T11 Packet length Number of bits in payload by the bit period.

Figure 37. Tx Programming Sequence and Timing Diagram

consists of a level shifter, a 32-bit shift register, and 11 latches. in Figure 2. Data can also be read back on the SREAD pin. SREAD pin, as shown in Figure 38, starting with the MSB first. The RSSI readback operation yields valid results in Rx mode. accordance with the definitions in Register 9—AGC Register. value, as outlined in the RSSI/AGC section. Figure 38. Readback Value Table

0 TRANSMIT

0 REGULATOR READY (DEFAULT)

0 R DIVIDER OUTPUT

0 N DIVIDER OUTPUT

0 DIGITAL LOCK DETECT

1 ANALOG LOCK DETECT

1 THREE-STATE

0 PLL OFF

1 PLL ON

Figure 39. Register 0—N Register

• The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.
• )2( 15 NFractionalNIntegerR XTALFOUT +×=
• If operating in 433 MHz band with the VCO band bit set, the desired frequency, FOUT, should be programmed to be twice the desired operating frequency, due to removal of the divide-by-2 stage in feedback path.

0 OFF

Figure 40. Register 1—Oscillator/Filter Register

• The VCO Adjust Bits R1_DB[20:21] should be set to 0 for operation in the 862 MHz to 870 MHz band and set to 3 for operation in the 902 MHz to 928 MHz band.
• VCO bias setting should be 0xA for operation in the 862 MHz to 870 MHz band and 0xC for operation in the 902 MHz to 928 MHz band. All VCO gain numbers are specified for these settings.

Figure 41. Register 2—Transmit Modulation Register

• FSTEP = PFD/1214.
• When operating in the 431 MHz to 464 MHz band, FSTEP = PFD/1215.
• PA bias default = 9 µA.

Figure 42. Register 3—Receiver Clock Register

• Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where: DIVIDECLKBBOS XTALCLKBBOS ___ =
• The demodulator clock (DEMOD_CLK) must be < 12 MHz, where: DIVIDECLKDEMOD XTALCLKDEMOD ___ =
• Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where: DIVIDECLKCDR CLKDEMODCLKCDR __ __ = Note that this can affect the choice of XTAL, depending on the desired data rate.
• The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz. DIVIDECLKSEQ XTALCLKSEQ ___ =

Figure 43. Register 4—Demodulator Setup Register

• Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to allow the ADF7025 to demodulate data-encoding schemes that have run-length constraints greater than 7.
• Post_Demod_BW = DEMOD_CLK Fπ2 CUTOFF 11 ×× , where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate.
• For Mode 5, the Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3—Receiver Clock Register section.

12 BITS

16 BITS

20 BITS

24 BITS

0 ERRORS

1 ERROR

2 ERRORS

3 ERRORS

Figure 44. Register 5—Sync Byte Register

• Sync byte detect is enabled by programming Bits R4_DB [25:23] to 010 or 011.
• This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync byte has been detected in Rx mode. Once the sync word detect signal has gone high, it goes low again after nine data bits.
• The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.
• Choose a sync byte pattern that has good autocorrelation properties.

Figure 45. Register 6—Correlator/Demodulator Register

• See the FSK Correlator/Demodulator section for an example of how to determine register settings.
• Nonadherence to correlator programming guidelines results in poor sensitivity.
• The filter clock is used to calibrate the LP filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is XTAL/FILTER_CLOCK_DIVIDE.
• The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high.
• Discriminator_BW = DEMOD_CLK/(4 × DEVIATION_Frequency). See the FSK Correlator/Demodulator section. Maximum value = 600.
• When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when linearity is a concern. See the Readback Format section for details of the different Rx modes.

Figure 46. Register 7—Readback Setup Register

• Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, the temperature sensor, and the voltage at the external pin is not available in Rx mode if AGC is enabled.
• Readback of the ADC value is valid in Tx mode only if the log amp/RSSI has not been disabled through the Power-Down Bit R8_DB10. The log amp/RSSI section is active by default upon enabling Tx mode.
• See the Readback Format section for more information.

Figure 47. Register 8—Power-Down Test Register

• For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.
• It is not necessary to write to this register under normal operating conditions.

Figure 48. Register 9—AGC Register

• The recommended AGC threshold settings are AGC_LOW_THRESHOLD = 15, AGC_HIGH_THRESHOLD = 79. The default settings (that is, if this register is not programmed) are AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details.
• AGC high and low settings must be more than 30 apart to ensure correct operation.
• LNA gain of 30 is available only if LNA mode, R6_DB15, is set to 0.

Figure 49. Register 10—AGC 2 Register

• Register 10 is not used under normal operating conditions.
• If adjusting AGC Delay or Leak Factor, clear Bit DB31 to Bit DB16.

Figure 50. Register 12—Test Register

• Monitor the signals at the FSK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality.
• Provide analog FM demodulation. While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that, although the test DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists. Programming the test register, Register 12, enables the test DAC. Both the linear and correlator/demodulator outputs can be multiplexed into the DAC. Register 13 allows a fixed offset term to be removed from the signal in the case where there is an error in the received signal frequency. If there is a frequency error in the signal, the user should program half this value into the offset removal field. It also has a signal gain term to allow usage of the maximum dynamic range of the DAC. Setting Up the Test DAC
• Digital test modes = 7: enables the test DAC, with no offset removal (0x0001C00C).
• Digital test modes = 10: enables the test DAC, with offset removal. The output of the active demodulator drives the DAC; that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC.

Figure 51. Register 13—Offset Removal and Signal Gain Register DAC_Input = (2^ Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096).

0.50 BSC

0.20 REF

0.80 MAX

0.05 MAX

0.02 NOM

0.60 MAX

0.60 MAX PIN 1

0.25 MIN

Figure 52. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. A | Page 42 of 44 NOTES

Rev. A | Page 43 of 44 NOTES

Rev. A | Page 44 of 44 NOTES ©2006 Analo g Devi ces, Inc. All rights reserved. Tra demarks and registered tra demarks are the prop erty of their respective o wners. D05542-0-2/06(A)