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High Performance, Narrow-Band Transceiver IC ADF7021-V Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

High performance, low power, narrow-band transceiver Enhanced performance ADF7021-N with external VCO Frequency bands using external VCO: 80 MHz to 960 MHz Improved adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N Programmable IF filter bandwidths: 9 kHz, 13.5 kHz, and 18.5 kHz Modulation schemes: 2FSK, 3FSK, 4FSK, MSK Spectral shaping: Gaussian and raised cosine filtering Data rates: 0.05 kbps to 24 kbps Power supply: 2.3 V to 3.6 V Programmable output power: −16 dBm to +13 dBm in 63 steps Automatic power amplifier (PA) ramp control Receiver sensitivity −125 dBm at 250 bps, 2FSK −122 dBm at 1 kbps, 2FSK Patent pending, on-chip image rejection calibration On-chip fractional-N PLL On-chip, 7-bit ADC and temperature sensor Fully automatic frequency control (AFC) loop Digital received signal strength indication (RSSI) Integrated Tx/Rx switch Leakage current in power-down mode: 0.1 μA

APPLICATIONS

Narrow-band, short-range device (SRD) standards ETSI EN 300 220 500 mW output power capability in 869 MHz g3 subband with external PA High performance receiver rejection, blocking, and adjacent channel power (ACP) FCC Part 90 (meets Emission Mask D requirements) FCC Part 95 ARIB STD-T67 Wireless metering Narrow-band wireless telemetry FUNCTIONAL BLOCK DIAGRAM 2FSK 3FSK 4FSK DEMODULATOR CLOCK AND DATA RECOVERY 7-BIT ADC GAIN DIV R RFOUT LNA PFDCP BUFFER OSC1 OSC2 N/N + 1DIV P OSC CLKOUT TEST MUX CPOUT LDO[1:4] MUXOUTRSET CREG[1:4]CE ADF7021-V TxRxCLK SWD TxRxDATA SLE SDATA SREAD SCLK IF FILTER PA RAMP MUX 2FSK 3FSK 4FSK MOD CONTROL GAUSSIAN/ RAISED COSINE FILTER 3FSK ENCODING ÷1/÷2 08635-001 CLK DIV Σ-Δ MODULATOR SERIAL PORT Tx/Rx CONTROL AGC CONTROL AFC CONTROL TEMP SENSOR RSSI/ LOG AMP RLNA RFIN RFIN Figure 1.

Rev. 0 | Page 2 of 60 TABLE OF CONTENTS

REVISION HISTORY

4/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 60 GENERAL DESCRIPTION The ADF7021-V is a high performance, low power, narrow-band RF transceiver based on the ADF7021-N. The architecture of the ADF7021-V transceiver is similar to that of the ADF7021-N except that an external VCO is used by the on-chip RF synthesizer for applications that require improved phase noise performance. The ADF7021-V is designed to operate in both the license-free ISM bands and in the licensed bands from 80 MHz to 960 MHz. To minimize RF feedthrough and spurious emissions, the external VCO operates at 2× or 4× the desired RF frequency; the ADF7021-V supports a maximum VCO frequency operation of 1920 MHz. The 4× VCO operation is programmable by enabling an additional on-chip divide-by-2 outside the RF synthesizer loop and offers improved phase noise performance. As with the ADF7021-N receiver, the IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz are supported, making the ADF7021-V ideally suited to worldwide narrow-band telemetry applications. The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the following:

  • European ETSI EN 300 220
  • North American FCC Part 15, Part 90, and Part 95
  • Japanese ARIB STD-T67
  • Korean short-range device regulations
  • Chinese short-range device regulations A complete transceiver can be built using a small number of discrete external components, making the ADF7021-V very suitable for area-sensitive, high performance driven applications. The range of on-chip FSK modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting the tight spectral efficiency requirements. The ADF7021-V also supports protocols that dynamically switch among 2FSK, 3FSK, and 4FSK to maximize communication range and data throughput. The transmit section contains a low noise fractional-N PLL with an output resolution of <1 ppm. The frequency-agile PLL allows the ADF7021-V to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO is external, which provides better phase noise and thus lower adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N. The VCO tuning range extends from 0.2 V to 2 V , which should be taken into account when choosing the external VCO. The transmitter output power is programmable in 63 steps from −16 dBm to +13 dBm and has an automatic power amplifier ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (100 kHz), which minimizes power consumption and the external component count yet avoids dc offset and flicker noise at low frequencies. The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz. The ADF7021-V supports a wide variety of pro- grammable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patented automatic frequency control (AFC) loop with programmable pull-in range that allows the PLL to remove the frequency error in the incoming signal. The receiver achieves an image rejection performance of 50 dB using a patent-pending IR calibration scheme that does not require the use of an external RF source. An on-chip ADC provides readback of the integrated temper- ature sensor, external analog input, battery voltage, and RSSI signal, which can eliminate the need for an external ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by performing a one-point cali- bration at room temperature and storing the result in memory.

Rev. 0 | Page 4 of 60 SPECIFICATIONS VDD = 2.3 V to 3.6 V , GND = 0 V , TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V , TA = 25°C. All measurements are performed with the EV AL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth. RF AND PLL SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments RF CHARACTERISTICS Phase Frequency Detector (PFD) Frequency RF/256 24 MHz Maximum usable PFD at a particular RF frequency is limited by the minimum N divider value PHASE-LOCKED LOOP (PLL) Normalized In-Band Phase Noise Floor1 −203 dBc/Hz PLL Settling 155 μs Measured for a 100 kHz frequency step to within 5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz EXTERNAL VCO Tuning Range 0.2 2 V Pin L2 Input Sensitivity 0 dBm VCO frequency < 1920 MHz REFERENCE INPUT Crystal Reference2 3.625 24 MHz External Oscillator2, 3 3.625 24 MHz Crystal Start-Up Time4 10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V XTAL Bias = 20 μA 0.930 ms XTAL Bias = 35 μA 0.438 ms Input Level for External Oscillator OSC1 Pin 0.8 V p-p Clipped sine wave OSC2 Pin CMOS levels V ADC PARAMETERS VDD = 2.3 V to 3.6 V, TA = 25°C Integral Nonlinearity (INL) ±0.4 LSB Differential Nonlinearity (DNL) ±0.4 LSB 1 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the power amplifier (PA) output: −203 + 10 log(fPFD) + 20 logN. 2 Guaranteed by design. Sample tested to ensure compliance. 3 A TCXO, VCXO, or OCXO can be used as an external oscillator. 4 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.

Rev. 0 | Page 5 of 60 TRANSMISSION SPECIFICATIONS LBW = loop bandwidth. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DATA RATE Limited by the loop bandwidth 2FSK 0.05 18.5 kbps LBW must be ≥1.25 × data rate for correct operation 3FSK 0.05 18.5 kbps LBW = 18.5 kHz 4FSK 0.05 24 kbps LBW = 18.5 kHz MODULATION Frequency Deviation (fDEV) 0.056 28.26 kHz PFD = 3.625 MHz 0.306 156 kHz PFD = 20 MHz Frequency Deviation Resolution 56 Hz PFD = 3.625 MHz Gaussian Filter Bandwidth Time (BT) 0.5 Raised Cosine Filter Alpha 0.5/0.7 Programmable TRANSMIT POWER Maximum Transmit Power1 13 dBm VDD = 3.0 V, TA = 25°C Transmit Power Variation vs. Temperature ±1 dB TA = −40°C to +85°C Transmit Power Variation vs. VDD ±1 dB VDD = 2.3 V to 3.6 V at 915 MHz, TA = 25°C Transmit Power Flatness ±1 dB 902 MHz to 928 MHz, VDD = 3 V, TA = 25°C Programmable Step Size 0.3125 dB −16 dBm to +13 dBm ADJACENT CHANNEL POWER (ACP) Gaussian 2FSK modulation, 13 dBm output power, PFD = 19.68 MHz, LBW = 6 kHz

460 MHz

12.5 kHz Channel Spacing −47 dBm Measured in a ±8.5 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, fDEV = 1.2 kHz 25 kHz Channel Spacing −53 dBm Measured in a ±16 kHz bandwidth at ±25 kHz offset, 4.8 kbps PN9 data, fDEV = 2.4 kHz

868 MHz Compliant with ETSI EN 300 220

12.5 kHz Channel Spacing −44 dBm Measured in a ±8.5 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, f DEV = 1.2 kHz 25 kHz Channel Spacing −49 dBm Measured in a ±16 kHz bandwidth at ±25 kHz offset, 4.8 kbps PN9 data, fDEV = 2.4 kHz MODULATION BANDWIDTH 869.525 MHz, Gaussian 2FSK modulation, 4.8 kbps, f DEV = 2.4 kHz, 10 dBm output power,2 compliant with ETSI EN 300 220, LBW = 6 kHz 125 kHz Offset −74.5 dBm/1 kHz 125 kHz + 200 kHz −79 dBm/1 kHz 125 kHz + 400 kHz −69.5 dBm/10 kHz 125 kHz + 1 MHz −62 dBm/100 kHz EMISSION MASK FCC Part 90 Emission Mask D, 100 Hz resolution bandwidth, Gaussian 2FSK modulation, LBW = 6 kHz, 10 dBm output power, 2.4 kbps PN9 data, fDEV = 1.2 kHz 12.5 kHz Offset

460 MHz −77 dBc

OCCUPIED BANDWIDTH 99.0% of total mean power, LBW = 6 kHz, 10 dBm output power 2FSK, Gaussian Data Filtering 12.5 kHz Channel Spacing 4.0 kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz 25 kHz Channel Spacing 8.5 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz 2FSK, Raised Cosine Data Filtering 12.5 kHz Channel Spacing 4.5 kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz 25 kHz Channel Spacing 9.6 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz

Rev. 0 | Page 6 of 60 Parameter Min Typ Max Unit Test Conditions/Comments 3FSK, Raised Cosine Filtering 12.5 kHz Channel Spacing 4.3 kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz 25 kHz Channel Spacing 8.5 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz 4FSK, Raised Cosine Filtering 25 kHz Channel Spacing 11.3 kHz 9.6 kbps PN9 data, fDEV = 1.2 kHz SPURIOUS EMISSIONS Reference Spurs −65 dBc LBW = 8 kHz HARMONICS3 13 dBm output power Second Harmonic −35/−52 dBc Unfiltered conductive/filtered conductive Third Harmonic −43/−60 dBc Unfiltered conductive/filtered conductive All Other Harmonics −36/−65 dBc Unfiltered conductive/filtered conductive OPTIMUM PA LOAD IMPEDANCE fRF = 915 MHz 39 + j61 Ω fRF = 868 MHz 48 + j54 Ω fRF = 470 MHz 97.5 + j64.4 Ω fRF = 450 MHz 98 + j65 Ω fRF = 426 MHz 100 + j65 Ω fRF = 315 MHz 129 + j63 Ω fRF = 175 MHz 173 + j49 Ω fRF = 169 MHz 74.5 + j48.5 Ω 1 Measured as maximum unmodulated power. 2 Suitable for ETSI 500 mW Tx requirements. 3 Conductive filtered harmonic emissions measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). RECEIVER SPECIFICATIONS LBW = loop bandwidth and IFBW = IF filter bandwidth. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DATA RATE Limited by the IF filter bandwidth1 2FSK 0.05 9.0 kbps IFBW = 9 kHz 0.05 13.5 kbps IFBW = 13.5 kHz 0.05 18.5 kbps IFBW = 18.5 kHz 3FSK 0.05 18.5 kbps IFBW = 18.5 kHz 4FSK 0.05 24 kbps IFBW = 18.5 kHz SENSITIVITY Bit error rate (BER) = 10−3 2FSK Sensitivity at 0.25 kbps −125 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 1 kbps −122 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 2.4 kbps −119 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 4.8 kbps −116 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 9.6 kbps −114 dBm fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz Gaussian 2FSK Sensitivity at 0.25 kbps −125 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 1 kbps −122 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 2.4 kbps −120 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 4.8 kbps −117 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 9.6 kbps −114 dBm fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz GMSK Sensitivity at 4.8 kbps −114.5 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz

Rev. 0 | Page 7 of 60 Parameter Min Typ Max Unit Test Conditions/Comments Raised Cosine 2FSK Sensitivity at 0.25 kbps −125 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 1 kbps −121 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 2.4 kbps −120 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 4.8 kbps −115 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz Sensitivity at 9.6 kbps −114 dBm fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz 3FSK Sensitivity at 4.8 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 18.5 kHz, Viterbi detection on Raised Cosine 3FSK Sensitivity at 4.8 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 13.5 kHz, alpha = 0.5, Viterbi detection on 4FSK Sensitivity at 4.8 kbps −112 dBm fDEV (inner)2 = 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz Raised Cosine 4FSK Sensitivity at 4.8 kbps −109 dBm fDEV (inner)2 = 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz, alpha = 0.5 INPUT IP3 Two-tone test, fLO = 860 MHz, f1 = fLO + 100 kHz, f2 = fLO − 800 kHz Low Gain, Enhanced Linearity Mode −3 dBm LNA_GAIN = 3, MIXER_LINEARITY = 1 Medium Gain Mode −13.5 dBm LNA_GAIN = 10, MIXER_LINEARITY = 0 High Sensitivity Mode −24 dBm LNA_GAIN = 30, MIXER_LINEARITY = 0 ADJACENT CHANNEL REJECTION (ACR)

868 MHz Desired signal is 3 dB above the sensitivity point of

−109.5 dBm as per EN 300 220; rejection is measured as the level of an unmodulated interferer to cause a BER of 10−2 for the desired signal 12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz 25 kHz Channel Spacing −39 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz 12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz 25 kHz Channel Spacing −40 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz 12.5 kHz Channel Spacing −59.5 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz 25 kHz Channel Spacing −42 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz 12.5 kHz Channel Spacing −63 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz 25 kHz Channel Spacing −45 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz 25 kHz Channel Spacing −57 dBm IFBW = 18.5 kHz, data rate = 9.6 kbps, fDEV = 4.8 kHz, LBW = 6 kHz 460 MHz Desired signal is at −106.5 dBm; rejection is measured as the level of an unmodulated interferer to cause a BER of 10−2 for the desired signal 12.5 kHz Channel Spacing −59.5 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz 25 kHz Channel Spacing −37.5 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz 12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz 25 kHz Channel Spacing −41 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz 12.5 kHz Channel Spacing −62 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz 25 kHz Channel Spacing −43 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz 12.5 kHz Channel Spacing −61.5 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz 25 kHz Channel Spacing −44.5 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz 25 kHz Channel Spacing −56 dBm IFBW = 18.5 kHz, data rate = 9.6 kbps, fDEV = 4.8 kHz, LBW = 6 kHz COCHANNEL REJECTION Desired signal is 3 dB above the sensitivity point of −109.5 dBm; rejection is measured as the level of an interferer to cause a BER of 10−2 for the desired signal 868 MHz −5 dB IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz

Rev. 0 | Page 8 of 60 Parameter Min Typ Max Unit Test Conditions/Comments IMAGE CHANNEL REJECTION Desired signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 3 dB above the sensitivity point (BER = 10−2); modulated inter- ferer (2FSK, 9.6 kbps, ±4 kHz deviation) is placed at the image frequency of f RF − 200 kHz; the interferer level is increased until BER = 10−2 868 MHz 26/39 dB Uncalibrated/calibrated,3 VDD = 3.0 V, TA = 25°C 460 MHz 29/50 dB Uncalibrated/calibrated,3 VDD = 3.0 V, TA = 25°C BLOCKING Desired signal is 3 dB above the sensitivity point of −109.5 dBm; rejection is measured as the level of an unmodulated interferer to cause a BER of 10 −2 for the desired signal; as per ETSI EN 300 220-1 ±1 MHz −29.5 dBm ±2 MHz −26.5 dBm ±5 MHz −26 dBm ±10 MHz −25.5 dBm SATURATION (MAXIMUM INPUT LEVEL) 12 dBm 2FSK mode, BER = 10−3 RECEIVED SIGNAL STRENGTH INDICATION (RSSI) Input Power Range4 −120 to −47 dBm Linearity ±2 dB Input power range = −100 dBm to −47 dBm Absolute Accuracy ±3 dB Input power range = −100 dBm to −47 dBm Response Time 333 μs As per AGC gain stage, AGC clock = 3 kHz AUTOMATIC FREQUENCY LOOP (AFC) Pull-In Range, Minimum 0.5 kHz Range is programmable in Register 10 (Bits[DB31:DB24]) Pull-In Range, Maximum 1.5 × IF_ FILTER_BW kHz Range is programmable in Register 10 (Bits[DB31:DB24]) Response Time 96 Bits Dependent on modulation index Accuracy 0.5 kHz Input power range = −100 dBm to +12 dBm Rx SPURIOUS EMISSIONS5 External 920 MHz VCO −54/−88 dBm <1 GHz at antenna input, unfiltered conductive/filtered conductive External 920 MHz VCO −45/−66 dBm >1 GHz at antenna input, unfiltered conductive/filtered conductive External 1738 MHz VCO −85/−85 dBm <1 GHz at antenna input, unfiltered conductive/filtered conductive External 1738 MHz VCO −39/−52 dBm >1 GHz at antenna input, unfiltered conductive/filtered conductive LNA INPUT IMPEDANCE RFIN to RFGND; refer to the AN-859 Application Note for other frequencies fRF = 915 MHz 24 − j60 Ω fRF = 868 MHz 26 − j63 Ω fRF = 470 MHz 58 − j124 Ω fRF = 450 MHz 63 − j129 Ω fRF = 426 MHz 68 − j134 Ω fRF = 315 MHz 96 − j160 Ω fRF = 175 MHz 178 − j190 Ω fRF = 169 MHz 182.5 − j194 Ω 1 Using Gaussian or raised cosine filtering. The frequency deviation should be chosen to ensure that the transmit-occupied signal bandwidth is within the receiver IF filter bandwidth. 2 4FSK fDEV is defined as the frequency spacing from the RF carrier to +fDEV or −fDEV. It is also equal to half the frequency spacing between adjacent symbols. 3 Calibration of the image rejection used an external RF source. 4 For received signal levels < −100 dBm, it is recommended that the RSSI readback value be averaged over a number of samples to improve RSSI accuracy at low input power. 5 Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor).

Rev. 0 | Page 9 of 60 DIGITAL SPECIFICATIONS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments TIMING INFORMATION Chip Enabled to Regulator Ready 50 μs CREG[1:4] = 100 nF Chip Enabled to Tx Mode 32-bit register write time = 50 μs TCXO Reference 1 ms Depends on VCO settling XTAL 2 ms Depends on VCO settling Chip Enabled to Rx Mode 32-bit register write time = 50 μs, IF filter coarse calibration only TCXO Reference 1.2 ms Depends on VCO settling XTAL 2.2 ms Depends on VCO settling Tx-to-Rx Turnaround Time AGC settling + (5 × tBIT) ms Time to synchronized data output; includes AGC settling (three AGC levels) and CDR synchronization; t BIT = data bit period; AFC settling not included LOGIC INPUTS Input High Voltage, VINH 0.7 × V DD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 μA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH VDD2 − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA CLKOUT Rise/Fall Time 5 ns CLKOUT Load 10 pF

Rev. 0 | Page 10 of 60 GENERAL SPECIFICATIONS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments TEMPERATURE RANGE (TA) −40 +85 °C POWER SUPPLIES Voltage Supply, VDD 2.3 3.6 V All VDDx pins must be tied together TRANSMIT CURRENT CONSUMPTION1, 2 V DD = 3.0 V, PA is matched into 50 Ω

868 MHz

0 dBm 17.6 mA 5 dBm 20.8 mA 10 dBm 27.1 mA 0 dBm 13.8 mA 5 dBm 17 mA 10 dBm 23 mA RECEIVE CURRENT CONSUMPTION2 V DD = 3.0 V Low Current Mode 19.3 mA High Sensitivity Mode 21.7 mA Low Current Mode 16.3 mA High Sensitivity Mode 18.3 mA POWER-DOWN CURRENT CONSUMPTION2 Low Power Sleep Mode 0.1 1 μA CE low 1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards. Improved PA efficiency is achieved by using a separate PA matching network. 2 Device current only. VCO and TCXO currents are excluded. TIMING CHARACTERISTICS VDD = 3 V ± 10%, GND = 0 V , TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested. Table 6. Parameter Limit at T MIN to TMAX Unit Description t1 >10 ns SDATA to SCLK setup time t2 >10 ns SDATA to SCLK hold time t3 >25 ns SCLK high duration t4 >25 ns SCLK low duration t5 >10 ns SCLK to SLE setup time t6 >20 ns SLE pulse width t8 <25 ns SCLK to SREAD data valid, readback t9 <25 ns SREAD hold time after SCLK, readback t10 >10 ns SCLK to SLE disable time, readback t11 5 < t11 < (¼ × tBIT) ns TxRxCLK negative edge to SLE t12 >5 ns TxRxDATA to TxRxCLK setup time (Tx mode) t13 >5 ns TxRxCLK to TxRxDATA hold time (Tx mode) t14 5 < t14 < (¼ × tBIT) μs TxRxCLK negative edge to SLE t15 >¼ × tBIT μs SLE positive edge to positive edge of TxRxCLK (Rx mode)

Rev. 0 | Page 14 of 60 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Parameter Rating VDD to GND1 −0.3 V to +5 V Analog I/O Voltage to GND1 −0.3 V to VDDx + 0.3 V Digital I/O Voltage to GND1 −0.3 V to VDDx + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C MLF θJA Thermal Impedance 26°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec This device is a high performance RF integrated circuit with an ESD rating of <2 kV , and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION 1 GND = GND1 = GND2 = GND4 = RFGND = 0 V.

  1. THE EXPOSED PADDLE MUST BE CONNECTED

Figure 10. Pin Configuration Table 8. Pin Function Descriptions ground for regulator stability and noise rejection. pin. Tie all VDDx pins together. output should be impedance matched to the desired load using suitable components. 5 RFGND Ground for Output Stage of Transmitter. Tie all GND pins together. input to ensure maximum power transfer. 7 RFIN Complementary LNA Input. 8 R LNA External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. regulator stability and noise rejection. 12, 19, 22 GND4 Ground for LNA/Mixer Block. Tie all GND pins together. 23 TEST_A Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected. when CE is low, and the part must be reprogrammed after CE is brought high. the 16 latches. A latch is selected using the control bits.

Rev. 0 | Page 16 of 60 Pin No. Mnemonic Description 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7021-V to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin. 28 SCLK Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into the 32-bit shift register on the SCLK rising edge. This pin is a digital CMOS input. 29 GND2 Ground for Digital Block. Tie all GND pins together. 30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is through the SREAD pin. 31 CREG2 Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. 32 VDD2 Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie all VDDx pins together. 33 SWD Sync Word Detect. The ADF7021-V asserts this pin when it finds a match for the sync word sequence. This provides an interrupt for an external microcontroller, indicating that valid data is being received. 34 TxRxDATA Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In UART/SPI receive mode, this pin provides an output for the received data. In UART/SPI transmit mode, this pin is high impedance. 35 TxRxCLK Outputs the data clock in both receive and transmit modes. This is a digital pin, and normal CMOS levels apply. The positive clock edge is matched to the center of the received data. In standard transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. In UART/SPI transmit mode, this pin is used to input the transmit data. In UART/SPI receive mode, this pin is high impedance. 36 CLKOUT Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark/space ratio and is inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the pin in applications where the CLKOUT feature is used. 37 MUXOUT Provides the DIGITAL_LOCK_DETECT signal. This signal is used to determine whether the PLL is locked to the correct frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of the status of the serial interface regulator. 38 OSC2 Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the internal crystal oscillator. 39 OSC1 Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this pin with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator. 40 VDD3 Voltage Supply for Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins together. 41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. 42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 43 VDD Voltage Supply for RF Circuitry. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie all VDDx pins together. 44 L2 VCO Buffer Input. 45 GND Ground. Tie all GND pins together. 46 L1 Do not connect. 47 GND1 Ground. Tie all GND pins together. 48 CVCO Do not connect. EP Exposed Paddle The exposed paddle must be connected to the ground plane.

Figure 17. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes Figure 18. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes Figure 19. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes

256 CODES/BIT

128 CODES/BIT

64 CODES/BIT

32 CODES/BIT

Figure 20. Output Spectrum in Maximum Hold Figure 21. 2FSK Sensitivity vs. VDD and Temperature at 868 MHz Figure 22. 2FSK Sensitivity vs. VDD and Temperature at 460 MHz

Design Studio website (www.analog.com/adisimsrd) for details).

870 MHz band, PFD

Figure 35. Fractional-N PLL voltages to the part. The nominal regulator voltage is 2.3 V . using the REGULATOR_READY signal from the MUXOUT pin. MUXOUT is high, programming of the ADF7021-V can begin. Figure 36. MUXOUT Circuit a microcontroller to signal the end of the IF filter calibration. DIGITAL_LOCK_DETECT indicates when the PLL has locked. receive mode. When in transmit mode, this signal is low. control an external Tx/Rx switch.

when the part is fully powered up in transmit or receive mode. The VCO tuning range of the external VCO must be 0.2 V to 2 V .

320 MHz VCO could be used with the RF_DIVIDE_BY_2 bit

320 MHz design using the additional divide-by-2 should result

and image rejection in the receiver. choose a suitable reference frequency. maximize the ACR and blocking resilience of the receiver. Figure 37. Voltage Controlled Oscillator (VCO)

maximum frequency of 960 MHz.

6 REGISTER 2,

Figure 38. PA Configuration a wide range of antennas, such as loop or monopole antennas. See the LNA/PA Matching section for more information. impedance momentarily disturbs the VCO output frequency. on and off, PA transient spurs are minimized. as a certain number of PA setting codes per one data bit period. Bits[DB10:DB8] in Register 2. Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off. Figure 39. PA Ramping Settings The ADF7021-V supports 2FSK, 3FSK, and 4FSK modulation. Figure 40. Transmit Modulation Implementation

energy in both RF sidebands. Table 9. Three-Level Signal Mapping of the Convolutional equal to the data rate presented at the transmit data input. equal to half the frequency spacing between adjacent symbols. mapping for 4FSK is gray coded and is shown in Figure 43. Figure 43. 4FSK Bit-to-Symbol Mapping set to three times the inner deviation frequency. at 32 times the programmed rate. filtering (bandwidth time [BT] = 0.5) on 2FSK modulation. that is very stable over temperature and supply variation. data. The BT product of the Gaussian filter used is 0.5. is selected by setting Register 2, Bits[DB6:DB4] to 001. 2FSK, 3FSK, and 4FSK modulation. Bits[DB6:DB4] as shown in Table 10.

ADF7021-V are described in Table 10. Table 10. Modulation and Filtering Options 1 MSK is 2FSK modulation with a modulation index = 0.5.

2 Offset quadrature phase shift keying (OQPSK) with half sine baseband

shaping is spectrally equivalent to MSK. 3 GMSK is GFSK with a modulation index = 0.5. the TxRxCLK signal appears at RF. 0.5 bit latency can be added to all values in Table 11. Table 11. Bit/Symbol Latency in Transmit Mode for Various that can be used to facilitate radio link setup or RF measurement. A full list of the supported test patterns is shown in Table 12. Table 12. Transmit Test Pattern Generator Options

frequency between 1 MHz and 2 MHz. where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32. priate LNA and filter gain settings for the measured RSSI level. SEQ_CLK_DIVIDE = 100 kHz (Register 3, Bits[DB25:DB18]). 33, which allows a settling time of 333 μs for each gain change. register (see Figure 57 and the Readback Format section). Gain Mode Correction is given by the values in Table 13. Table 13. Gain Mode Correction in the front-end-matching network/antenna. Table 14. LNA/Mixer Modes (Register 9 Settings)

Rev. 0 | Page 31 of 60 2FSK Bit Slicer/Threshold Detection 2FSK demodulation can be implemented using the correlator FSK demodulator or the linear FSK demodulator. In both cases, threshold detection is used for data recovery at the output of the postdemodulator filter. The output signal levels of the correlator demodulator are always centered about 0. Therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery that does not suffer from the classic baseline wander problems that exist in more traditional FSK demodulators. When the linear demodulator is used for 2FSK demodulation, the output of the envelope detector is used as the slicer threshold, and this output tracks frequency errors that are within the IF filter bandwidth. 3FSK and 4FSK Threshold Detection 4FSK demodulation is implemented using the correlator demodulator followed by the postdemodulator filter and threshold detection. The output of the postdemodulator filter is a four-level signal that represents the transmitted symbols (−3, −1, +1, +3). Threshold detection of 4FSK requires three threshold settings: one that is always fixed at 0 and two that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). 3FSK demodulation is implemented using the correlator demod- ulator, followed by a postdemodulator filter. The output of the postdemodulator filter is a three-level signal that represents the transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be implemented using threshold detection or Viterbi detection. Threshold detection is implemented using two thresholds that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). 3FSK Viterbi Detection Viterbi detection of 3FSK operates on a four-state trellis and is implemented using two interleaved Viterbi detectors operating at half the symbol rate. The Viterbi detector is enabled by Register 13, Bit DB11. To facilitate different run-length constraints in the transmitted bit stream, the Viterbi path memory length is programmable in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the VITERBI_ PATH_MEMORY bits (Register 13, Bits[DB14:DB13]). This value should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. When used with Viterbi detection, the receiver sensitivity for 3FSK is typically 3 dB greater than that obtained using threshold detection. When the Viterbi detector is enabled, however, the receiver bit latency is increased by twice the Viterbi path memory length. Clock and Data Recovery (CDR) An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock in all modulation modes. The oversampled clock rate of the PLL (CDR CLK) must be set at 32 times the symbol rate (see the Register 3—Transmit/Receive Clock Register section). The maxi- mum data/symbol rate tolerance of the CDR PLL is determined by the number of zero-crossing symbol transitions in the trans- mitted packet. For example, if using 2FSK with a 101010 preamble, a maximum tolerance of ±3.0% of the data rate is achieved. However, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the data rate tolerance of the CDR, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. For example, using 2FSK with Manchester-encoded data achieves a data rate tolerance of ±2.0%. The CDR PLL is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchro- nization within five-symbol transitions of preamble. In 4FSK modulation, the tolerance using the +3, −3, +3, −3 preamble is ±3% of the symbol rate (or ±1.5% of the data rate). However, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the symbol/data rate tolerance of the CDR, the remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to dc-free properties by using data scram- bling and/or by inserting specific dc-balancing symbols into the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. In 3FSK modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. However, Tx data scrambling is recommended to limit the run length of 0 symbols in the transmit bit stream. Using 3FSK, the CDR data rate tolerance is typically ±0.5%.

Table 15. Enabling the Correlator Demodulator Round is rounded to the nearest integer. inner frequency deviations). are assigned according to Table 16 and Table 17. Table 16. Assignment of Correlator K Value for 2FSK and 3FSK Table 17. Assignment of Correlator K Value for 4FSK (Register 4, Bits[DB6:DB4]) to 000. set according to the received modulation type and data rate. Table 18. Postdemodulator Filter Bandwidth Settings for activated by setting Register 13, Bit DB11, to Logic 1. 0s in the interleaved transmit bit stream. (Register 13, Bits[DB10:DB4]). the 3FSK Viterbi Detector Setup section.

transitions for the CDR to acquire lock. parameters in Register 13 to be set (see Table 19). RC2FSK is a dc-free pattern (such as a 10101010… pattern). receiver and CDR acquisition (see Table 20). Application Note for more information. preamble is 32 bits (16 symbols). as after every 8 or 16 symbols. Table 19. 3FSK CDR Settings Table 20. Preamble Bit Length for 2FSK Modulation 1 This value is generally true; however, some sensitivity degradation may occur close to the edge of the IF filter. 2 Limited to ±0.5 × IFBW or AFC pull-in range, whichever is less. minimum preamble length increases as the modulation index and fDEV are reduced. 4 Dependent on the performance of the symbol timing recovery module on the external microcontroller. Logic 1 is the same as the width of a Logic 0.

Rev. 0 | Page 34 of 60 Correlator Demodulator and Low Modulation Indexes The modulation index in 2FSK is defined as Rate Data fIndexModulation DEV×= 2 The receiver sensitivity performance and receiver frequency tolerance can be maximized at low modulation indexes by increasing the discriminator bandwidth of the correlator demodulator. For modulation indexes of less than 0.4, it is recommended that the correlator bandwidth be doubled by calculating K as follows: DEVfRound K2 1003 The DISCRIMINATOR_BW value in Register 4 should be recalculated using the new K value. Figure 29 illustrates the improved sensitivity that can be achieved for 2FSK modulation, at low modulation indexes, by doubling the correlator bandwidth. AFC OPERATION The ADF7021-V also supports a real-time AFC loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/TCXOs. The AFC loop uses the linear frequency discriminator block to estimate frequency errors. The linear FSK discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In receive mode, the output of the envelope detector provides an estimate of the average IF frequency. The two methods of AFC supported on the ADF7021-V are external AFC and internal AFC. External AFC With external AFC, the user reads back the frequency infor- mation through the ADF7021-V serial port and applies a frequency correction value to the synthesizer-N divider. The frequency information is obtained by reading the signed, 16-bit AFC readback value, as described in the Readback Format section, and by applying the following formula: Frequency Readback (Hz) = (AFC READBACK × DEMOD CLK)/2 Although the AFC readback value is a signed number, under normal operating conditions, it is positive. In the absence of frequency errors, the frequency readback value is equal to the IF frequency of 100 kHz. Internal AFC The ADF7021-V supports a real-time, internal, automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-N divider using an internal proportional integral (PI) control loop. The internal AFC control loop parameters are controlled in Register 10. The internal AFC loop is activated by setting Bit DB4 in Register 10 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up using Bits[DB16:DB5] in Register 10 and should be calculated as follows: ⎛ ×= XTALRoundFACTORSCALINGAFC 500 2__ Maximum AFC Range The maximum frequency correction range of the AFC loop is programmable using Register 10, Bits[DB31:DB24]. The maximum AFC correction range is the difference in frequency between the upper and lower limits of the AFC tuning range. For example, if the maximum AFC correction range is set to 10 kHz, the AFC can adjust the receiver LO within the f LO ± 5 kHz range. However, when RF_DIVIDE_BY_2 (Register 1, Bit DB18) is enabled, the programmed range is halved. The user should account for this halving by doubling the programmed maxi- mum AFC range. The recommended maximum AFC correction range should be ≤1.5 × IF filter bandwidth. If the maximum frequency correction range is set to be >1.5 × IF filter bandwidth, the attenuation of the IF filter can degrade the AFC loop sensitivity. The adjacent channel rejection (ACR) performance of the receiver can be degraded when AFC is enabled and the AFC correction range is close to or greater than the IF filter bandwidth. However, because the AFC correction range is programmable, the user can trade off AFC correction range and ACR performance of the receiver. When AFC errors are removed using either the internal or external AFC, further improvement in receiver sensitivity can be obtained by reducing the IF filter bandwidth using the IF_FILTER_BW bits (Register 4, Bits[DB31:DB30]).

Rev. 0 | Page 35 of 60 AUTOMATIC SYNC WORD DETECTION (SWD) The ADF7021-V also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021-V . In receive mode, this preprogrammed word is compared to the received bit stream. When a valid match is identified, the external SWD pin is asserted by the ADF7021-V on the next Rx clock pulse. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The SWD signal can also be used to frame the received packet by staying high for a preprogrammed number of bytes. The data packet length can be set in Register 12, Bits[DB15:DB8]. The SWD pin status can be configured by setting Bits[DB7:DB6] in Register 12. Bits[DB5:DB4] in Register 11 are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. A value of 24 bits is recommended to minimize false sync word detection in the receiver that can occur during recovery of the remainder of the packet or when a noise/no signal is present at the receiver input. The transmitter must transmit the sync byte MSB first, LSB last to ensure proper alignment in the receiver sync-byte-detection hardware. An error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in Register 11, Bits[DB7:DB6].

calibration or a fine calibration. Table 21. IF Filter Calibration Specifications followed by a fine calibration; otherwise, the calibration ends.

10 RSSI measurements, at which point the calibration algorithm

sets the IF filter center frequency to within 0.6 kHz of 100 kHz. as shown in the following equations. Table 22. IF Filter Fine Calibration Tone Frequencies small positive offset in the IF filter center frequency. Table 22 to adjust the fine calibration result. the filter calibration duration or to signal the end of calibration. The ADF7021-V should not be accessed during calibration.

receive are shown in Figure 54 and Figure 55, respectively. reference is shown in these figures. Figure 54. Power-Up Sequence for Transmit Mode

Figure 55. Power-Up Sequence for Receive Mode

capacitors are omitted for clarity. in narrow-band applications.

  1. PINS[13:18], PINS[20:21], AND PIN 23 ARE TEST PINS AND ARE NOT USED IN NORMAL OPERATION.

Figure 56. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown)

consists of a level shifter, 32-bit shift register, and 16 latches. powered by the regulator and, therefore, is inactive when CE is low. signals with either the linear or correlator demodulator active. variation in the readback value can be improved by averaging. RSSI readback value as described in the RSSI/AGC section. subsequent SPI command (LOCK_THRESHOLD_MODE = 1). Figure 57. Readback Value Table

0 TRANSMIT

0 REGULATOR_READY (DEFAULT)

0 DIGITAL_LOCK_DETECT

0 RSSI_READY

1 LOGIC_ZERO

1 LOGIC_ONE

1 ENABLED

Figure 62. Register 0—N Register Map

  • The RF output frequency is calculated as follows: • In the MUXOUT map (Bits[DB31:DB29]), FILTER_CAL_ COMPLETE indicates when a coarse or coarse plus fine IF filter calibration has finished. DIGITAL_LOCK_DETECT indicates when the PLL has locked. RSSI_READY indicates that the RSSI signal has settled and an RSSI readback can be performed. Tx_Rx gives the status of Bit DB27 in this register, which can be used to control an external Tx/Rx switch. For direct output, ⎞⎜⎝ ⎛ +× = 152 __ NFRACTIONALNINTEGERPFDRFOUT With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled, ⎞⎜⎝ ⎛ +× × = 152 __5 . 0 NFRACTIONALNINTEGERPFDRFOUT
  • In UART/SPI mode, the TxRxCLK pin is used to input the transmitted data. The received data is available on the TxRxDATA pin.

0 OFF

Figure 63. Register 1—Oscillator Register Map

  • The R_COUNTER and XTAL_DOUBLER relationship is as follows: If XTAL_DOUBLER = 0, COUNTERR XTAL PFD_= If XTAL_DOUBLER = 1, COUNTERR XTAL PFD_ 2×=
  • CLKOUT_DIVIDE is a divided-down and inverted version of the XTAL and is available on Pin 36 (CLKOUT).
  • Set XOSC_ENABLE high when using an external crystal. If using an external oscillator (such as TCXO) with CMOS level outputs into Pin OSC2, set XOSC_ENABLE low. If using an external oscillator with a 0.8 V p-p clipped sine wave output into Pin OSC1, set XOSC_ENABLE high.

16 CODES/BIT

8 CODES/BIT

4 CODES/BIT

Figure 64. Register 2—Transmit Modulation Register Map

  • The 2FSK/3FSK/4FSK frequency deviation is expressed as follows: For direct RF output, Frequency Deviation (Hz) = 162 PFD ONCY_DEVIATITx_FREQUEN × With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled, Frequency Deviation (Hz) = 1625 . 0 PFD ONCY_DEVIATITx_FREQUEN ×× where: Tx_FREQUENCY_DEVIATION is set by Bits[DB27:DB19]. PFD is the PFD frequency.
  • In the case of 4FSK, there are tones at ±3 × the frequency deviation and at ±1 × the frequency deviation.
  • The power amplifier (PA) ramps at the programmed rate (Bits[DB10:DB8]) until it reaches its programmed level (Bits[DB18:DB13]). If the PA is enabled/disabled by the PA_ENABLE bit (Bit DB7), it ramps up and down. If it is enabled/disabled by the Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off. R-COSINE_ALPHA sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7.

Figure 65. Register 3—Transmit/Receive Clock Register Map

  • Baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, where BBOS CLK = (XTAL/BBOS_CLK_DIVIDE)
  • Set the demodulator clock (DEMOD CLK) such that

2 MHz ≤ DEMOD CLK ≤ 15 MHz, where

  • For 2FSK/3FSK, the clock/data recovery frequency (CDR CLK) must be within 2% of (32 × data rate). For 4FSK, the CDR CLK must be within 2% of (32 × symbol rate). CDR CLK = (DEMOD CLK/CDR_CLK_DIVIDE)
  • The sequencer clock (SEQ CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible. SEQ CLK = (XTAL/SEQ_CLK_DIVIDE)
  • The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 3 kHz. AGC Update Rate (Hz) = (SEQ CLK/AGC_CLK_DIVIDE)

Figure 66. Register 4—Demodulator Setup Register Map

  • To solve for DISCRIMINATOR_BW , (Bits[DB19:DB10]), use the following equation: ×= 310 400_ K CLKDEMOD BW TORDISCRIMINA where the maximum value = 660. For 2FSK, ⎛ ×= DEVfRound K 310 100 For 3FSK, DEVfRound K 2 10 1003 For 4FSK, DEV FSK fRound K 4 10 1003 where: Round is rounded to the nearest integer. Round4FSK is rounded to the nearest of the following integers: fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is the frequency deviation used for the ±1 symbols (that is, the inner frequency deviations).
  • Rx_INVERT (Bits[DB9:DB8]) and DOT_PRODUCT (Bit DB7) must be set as indicated in Table 16 and Table 17.
  • POST_DEMOD_BW (Bits[DB29:DB20]) sets the bandwidth of the postdemodulator filter. To solve for POST_DEMOD_BW , use the following equation: CLKDEMOD f_BWPOST_DEMOD CUTOFF× ×= π 211 where fCUTOFF (the cutoff frequency of the postdemodulator filter) should typically be set equal to 0.75 × the data rate in 2FSK. In 3FSK, it should be set equal to the data rate, whereas in 4FSK, it should be set equal to 1.6 × the symbol rate.

Figure 67. Register 5—IF Filter Setup Register Map

  • A coarse IF filter calibration is performed when the IF_CAL_COARSE bit (Bit DB4) is set. If the IF_FINE_ CAL bit (Register 6, Bit DB4) has been previously set, a fine IF filter calibration is automatically performed after the coarse calibration. Set IF_FILTER_DIVIDER such that kHz 50_ _ =DIVIDERFILTER IF XTAL
  • IF_FILTER_ADJUST allows the IF fine filter calibration result to be programmed directly on subsequent receiver power-ups, thereby eliminating the need to redo a fine filter calibration in some instances. See the Filter Bandwidth Calibration Readback section for information about using the IF_FILTER_ADJUST bits. Bits[DB31:DB20] are used for image rejection calibration. See the Image Rejection Calibration section for information about how to program these parameters.

Figure 68. Register 6—IF Fine Calibration Setup Register Map

  • A fine IF filter calibration is set by enabling the IF_FINE_ CAL bit (Bit DB4). A fine calibration is performed only when Register 5 is written to and Register 5, Bit DB4 is set. Lower Tone Frequency (kHz) = 2×VIDEER_TONE_DIIF_CAL_LOW XTAL Upper Tone Frequency (kHz) = 2×VIDEER_TONE_DIIF_CAL_UPP XTAL It is recommended that the lower tone and the upper tone be set as shown in Table 24.

Table 24. IF Filter Fine Calibration Tone Frequencies

  • The IF tone calibration time is the amount of time that is spent at an IF calibration tone. It is dependent on the sequencer clock. It is recommended that the IF tone calibration time be at least 800 μs. CLK SEQ LL_TIMEIF_CAL_DWETime n CalibratioTone IF = The total time for a fine IF filter calibration is IF Tone Calibration Time × 10
  • Bits[DB30:DB28] control the internal source for the image rejection (IR) calibration. The IR_CAL_SOURCE_DRIVE_ LEVEL bits (Bits[DB29:DB28]) set the drive strength of the source, whereas the IR_CAL_SOURCE ÷2 bit (Bit DB30) allows the frequency of the internal signal source to be divided by 2.

Figure 69. Register 7—Readback Setup Register Map

  • Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external ADCIN pin is not valid in Rx mode. To read back the battery voltage, the temperature sensor, or the voltage at the external ADCIN pin in Tx mode, the user should first power up the ADC using Register 8, Bit DB8 because it is turned off by default in Tx mode to save power. For AFC readback, use the following equations (see the Readback Format section): FREQ RB (Hz) = (AFC READBACK × DEMOD CLK)/2 VBATTERY = BATTERY VOLTAGE READBACK/21.1 VADCIN = ADCIN VOLTAGE READBACK/42.1 Temperature (°C) = −40 + [(68.4 − TEMP READBACK) × 9.32]

Figure 70. Register 8—Power-Down Test Register Map is the power-up default condition.

Figure 71. Register 9—AGC Register Map

  • It is necessary to program this register only if AGC settings other than the defaults are required.
  • In receive mode, AGC is set to automatic AGC by default on power-up. The default thresholds are AGC_LOW_ THRESHOLD = 30 and AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. AGC high and low threshold values must be more than 30 apart to ensure correct operation. An LNA gain of 30 is available only if LNA_MODE (Bit DB25) is set to 0.

Figure 72. Register 10—AFC Register Map

  • The AFC_SCALING_FACTOR can be expressed as ⎛ ×= XTALRoundFACTORSCALINGAFC 500 2__
  • The settings for KI and KP affect the AFC settling time and AFC accuracy. The allowable range for each parameter is KI > 6 and KP < 7. The recommended settings for optimal AFC performance are KI = 11 and KP = 4. To trade off between AFC settling time and AFC accuracy, the KI and KP parameters can be adjusted from the recommended settings (staying within the allowable range) such that AFC Correction Range = MAX_AFC_RANGE × 500 Hz When RF_DIVIDE_BY_2 (Register 1, Bit DB18) is enabled, the programmed AFC correction range is halved. The user must account for this halving by doubling the programmed MAX_AFC_RANGE value.
  • Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter. As a result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the AFC.

12 BITS

16 BITS

20 BITS

24 BITS

Figure 73. Register 11—Sync Word Detect Register Map

0 THRESHOLD FREE RUNNING

1 LOCK THRESHOLD AFTER NEXT SYNC WORD

2 LOCK THRESHOLD AFTER NEXT SYNC WORD

3 LOCK THRESHOLD

0 INVALID

0 SWD PIN LOW

1 SWD PIN HIGH AFTER NEXT SYNC WORD

2 SWD PIN HIGH AFTER NEXT SYNC WORD

3 SWD PIN HIGH

Figure 74. Register 12—SWD/Threshold Setup Register Map Lock threshold locks the threshold of the envelope detector.

See the Receiver Setup section for information about programming these settings.

4 BITS0

6 BITS

8 BITS

32 BITS

0 DISABLED

Figure 75. Register 13—3FSK/4FSK Demodulation Register Map

0.5 RESPONSE TO PEAK

0.25 RESPONSE TO PEAK

0.125 RESPONSE TO PEAK

Figure 76. Register 14—Test DAC Register Map enabled only by setting Register 15, Bits[DB7:DB4] to 0x9. about using the test DAC, see the AN-852 Application Note. maximum dynamic range of the DAC. also be constructed to measure the received signal quality. Provide analog FM demodulation.

2 FILTER I CHANNEL: STAGE 1

3 FILTER I CHANNEL: STAGE 2

4 FILTER I CHANNEL: STAGE 1

5 FILTER Q CHANNEL: STAGE 1

6 FILTER Q CHANNEL: STAGE 2

7 FILTER Q CHANNEL: STAGE 1

8 ADC REFERENCE VOLTAGE

9 BIAS CURRENT FROM RSSI 5µA

10 FILTER COARSE CAL OSCILLATOR OUTPUT

11 ANALOG RSSI I CHANNEL

15 BIAS CURRENT FROM BB FILTER

3 DITHER TO FIRST STAGE

4 DITHER TO SECOND STAGE

5 DITHERTO THIRD STAGE

6 DITHER × 8

7 DITHER × 32

3 RCNTR/2 ON MUXOUT

4 NCNTR/2 ON MUXOUT

5 ACNTR TO MUXOUT

6 PFD PUMP UP TO MUXOUT

7 PFD PUMP DNTO MUXOUT

8 S DATA TO MUXOUT (OR SREAD)

9 ANALOG LOCK DETECT ON MUXOUT

10 END OF COARSE CAL ON MUXOUT

11 END OF FINE CAL ON MUXOUT

13 TEST MUX SELECTS DATA

14 LOCK DETECT PRECISION

15 RESERVED

5 CP PUMP UP

6 CP TRISTATE

7 CP PUMP DN

1 OVERRIDE GAIN

2 OVERRIDE BW

3 OVERRIDE BW AND GAIN

1 SCLK, SDATA I,Q

2 REVERSE I,Q

Figure 77. Register 15—Test Mode Register Map

  • Analog RSSI can be viewed on the TEST_A pin by setting ANALOG_TEST_MODES (Bits[DB27:DB24]) to 11.
  • Tx_TEST_MODES can be used to enable modulation test.
  • The CDR block can be bypassed by setting Rx_TEST_ MODES to 4, 5, or 6, depending on the demodulator used.

0.50 BSC

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

0.60 MAX PIN 1

0.25 MIN

Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the prop erty of their respective owners.