ADF7020

ADF7020 (Rev. E)

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 47

Technical content

High Performance, ISM Band, FSK/ASK Transceiver IC Data Sheet ADF7020 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Low power, low IF transceiver Frequency bands

431 MHz to 478 MHz

862 MHz to 956 MHz

0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 0.3 dBm steps Receiver sensitivity −119 dBm at 1 kbps, FSK −112 dBm at 9.6 kbps, FSK −106.5 dBm at 9.6 kbps, ASK Low power consumption 19 mA in receive mode 26.8 mA in transmit mode (10 dBm output) −3 dBm IIP3 in high linearity mode On-chip VCO and fractional-N PLL On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) compensates for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at Leakage current of <1 μA in power-down mode

APPLICATIONS

Low cost wireless data transfer Remote control/security systems Wireless metering Keyless entry Home automation Process and building control Wireless voice FUNCTIONAL BLOCK DIAGRAM Tx/Rx CONTROL AGC CONTROL FSK/ASK DEMODULATOR DATA SYNCHRONIZERRSSI 7-BIT ADC GAIN DIV R SERIAL PORT RFOUT OFFSET CORRECTION OFFSET CORRECTION LNA VCO PFDCP AFC CONTROL OSC1 OSC2 DIVIDERS/ MUXING N/N + 1DIV P MUX TEMP SENSOR OSC CLK DIV CLKOUT TEST MUX VCOIN CPOUT LDO(1:4) MUXOUTADCINRSET CREG[1:4] RLNA RFIN RFINB SLE SDATA CE DATA CLK SREAD SCLK INT/LOCK DATA I/O FSK MOD CONTROL GAUSSIAN FILTER Σ-∆ MODULATOR 05351-001 IF FILTER ADF7020 Figure 1.

Rev. E | Page 2 of 47 TABLE OF CONTENTS Register 2—Transmit Modulation Register (ASK/OOK Register 2—Transmit Modulation Register (GFSK/GOOK

Rev. E | Page 3 of 47

REVISION HISTORY

9/2016—Rev. D to Rev. E Changes to Interfacing to Microcontroller/DSP Section and 8/2012—Rev. C to Rev. D 5/2011—Rev. B to Rev. C 8/2007—Rev. A to Rev. B Changes to Choosing Channels for Best Performance Section 17 4/2006—Rev. 0 to Rev. A Changes to Transmit Protocol and Coding Considerations Changes to Register 1—Oscillator/Filter Register Changes to Register 2—Transmit Modulation Register Changes to Register 2—Transmit Modulation Register Changes to Register 4—Demodulator Setup Register 6/2005—Revision 0: Initial Version

Rev. E | Page 4 of 47 GENERAL DESCRIPTION The ADF7020 is a low power, highly integrated FSK/ASK/OOK transceiver designed for operation in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed Japanese RFID band at 950 MHz. A Gaussian data filter option is available to allow either GFSK or G-ASK modulation, which provides a more spectrally efficient modulation. In addition to these modulation options, the ADF7020 can also be used to perform both MSK and GMSK modulation, where MSK is a special case of FSK with a modulation index of 0.5. The modula- tion index is calculated as twice the deviation divided by the data rate. MSK is spectrally equivalent to O-QPSK modulation with half-sinusoidal Tx baseband shaping, so the ADF7020 can also support this modulation option by setting up the device in MSK mode. This device is suitable for circuit applications that meet the European ETSI-300-220, the North American FCC (Part 15), or the Chinese Short Range Device regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7020 very suitable for price-sensitive and area-sensitive applications. The transmitter block on the ADF7020 contains a VCO and low noise fractional-N PLL with an output resolution of <1 ppm. This frequency agile PLL allows the ADF7020 to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency-pulling problems. The transmitter output power is programmable in 0.3 dB steps from −16 dBm to +13 dBm. The transceiver RF frequency and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to track out the frequency error in the incoming signal. An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

Rev. E | Page 5 of 47 SPECIFICATIONS VDD = 2.3 V to 3.6 V , GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V , TA = 25°C. All measurements are performed using the E VA L-ADF7020DBZ1 through E VA L-ADF7020DBZ3 using the PN9 data sequence, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions RF CHARACTERISTICS Frequency Ranges (Direct Output) 862 870 MHz VCO adjust = 0, VCO bias = 10 902 928 MHz VCO adjust = 3, VCO bias = 10 928 956 MHz VCO adjust = 3, VCO bias = 12, VDD = 2.7 V to 3.6 V Frequency Ranges (Divide-by-2 Mode) 431 440 MHz VCO adjust = 0, VCO bias = 10 440 478 MHz VCO adjust = 3, VCO bias = 12 Phase Frequency Detector Frequency RF/256 24 MHz TRANSMISSION PARAMETERS Data Rate FSK/GFSK 0.15 200 kbps OOK/ASK 0.15 641 kbps OOK/ASK 0.3 100 kbaud Using Manchester encoding Frequency Shift Keying GFSK/FSK Frequency Deviation2, 3 1 110 kHz PFD = 3.625 MHz 4.88 620 kHz PFD = 20 MHz Deviation Frequency Resolution 100 Hz PFD = 3.625 MHz Gaussian Filter BT 0.5 Amplitude Shift Keying ASK Modulation Depth 30 dB PA Off Feedthrough in OOK Mode −50 dBm Transmit Power4 −20 +13 dBm VDD = 3.0 V, TA = 25°C Transmit Power Variation vs. Temperature ±1 dB From −40°C to +85°C Transmit Power Variation vs. VDD ±1 dB From 2.3 V to 3.6 V at 915 MHz, TA = 25°C Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz, 3 V, TA = 25°C Programmable Step Size −20 dBm to +13 dBm 0.3125 dB Integer Boundary −55 dBc 50 kHz loop BW Reference −65 dBc Harmonics Second Harmonic −27 dBc Unfiltered conductive Third Harmonic −21 dBc All Other Harmonics −35 dBc VCO Frequency Pulling, OOK Mode 30 kHz rms DR = 9.6 kbps Optimum PA Load Impedance5 39 + j61 Ω FRF = 915 MHz 48 + j54 Ω FRF = 868 MHz 54 + j94 Ω FRF = 433 MHz RECEIVER PARAMETERS FSK/GFSK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz, LNA and PA matched separately6 Sensitivity at 1 kbps −119.2 dBm FDEV = 5 kHz, high sensitivity mode7 Sensitivity at 9.6 kbps −112.8 dBm FDEV = 10 kHz, high sensitivity mode Sensitivity at 200 kbps −100 dBm FDEV = 50 kHz, high sensitivity mode OOK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz Sensitivity at 1 kbps −116 dBm High sensitivity mode Sensitivity at 9.6 kbps −106.5 dBm High sensitivity mode

Rev. E | Page 6 of 47 Parameter Min Typ Max Unit Test Conditions LNA and Mixer, Input IP37 Enhanced Linearity Mode −3 dB m Pin = −20 dBm, 2 CW interferers Low Current Mode −5 dBm FRF = 915 MHz, F1 = FRF + 3 MHz High Sensitivity Mode −24 dBm F2 = FRF + 6 MHz, maximum gain Rx Spurious Emissions8 −57 dBm <1 GHz at antenna input −47 dBm >1 GHz at antenna input AFC Pull-In Range at 868 MHz/915 MHz ±50 kHz IF_BW = 200 kHz Pull-In Range at 433 MHz ±25 kHz IF_BW = 200 kHz Response Time 48 Bits Modulation index = 0.875 Accuracy 1 kHz CHANNEL FILTERING Desired signal 3 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3, image channel excluded Adjacent Channel Rejection (Offset = ±1 × IF Filter BW Setting) 27 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz Second Adjacent Channel Rejection (Offset = ±2 × IF Filter BW Setting) 50 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz Third Adjacent Channel Rejection (Offset = ±3 × IF Filter BW Setting) 55 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz Image Channel Rejection (Uncalibrated) 30 dB Image at FRF = 400 kHz Image Channel Rejection (Calibrated) 50 dB Image at FRF = 400 kHz CO-CHANNEL REJECTION −2 dB Wideband Interference Rejection 70 dB Swept from 100 MHz to 2 GHz, measured as channel rejection BLOCKING Desired signal 3 dB above the input sensitivity level, CW interferer power level increased until BER = 10−2 ±1 MHz 60 dB ±5 MHz 68 dB ±10 MHz 65 dB ±10 MHz (High Linearity Mode) 72 dB Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10 −3 LNA Input Impedance 24 − j60 Ω FRF = 915 MHz, RFIN to GND 26 − j63 Ω FRF = 868 MHz 71 − j128 Ω FRF = 433 MHz RSSI Range at Input −110 to −24 dBm Linearity ±2 dB Absolute Accuracy ±3 dB Response Time 150 μs See the RSSI/AGC section PHASE-LOCKED LOOP VCO Gain 65 MHz/V 902 MHz to 928 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 10

130 MHz/V 860 MHz to 870 MHz band, VCO adjust = 0

65 MHz/V 433 MHz, VCO adjust = 0

Phase Noise (In-Band) −89 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 915 MHz, VCO_BIAS_SETTING = 10 Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 868 MHz PLL Settling 40 μs Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz

Rev. E | Page 7 of 47 Parameter Min Typ Max Unit Test Conditions REFERENCE INPUT Crystal Reference 3.625 24 MHz External Oscillator 3.625 24 MHz Load Capacitance 33 pF See crystal manufacturer’s specification sheet Crystal Start-Up Time 2.1 ms 11.0592 MHz crystal, using 33 pF load capacitors 1.0 ms Using 16 pF load capacitors Input Level CMOS levels See the Reference Input section ADC PARAMETERS INL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C DNL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C TIMING INFORMATION Chip Enabled to Regulator Ready 10 µs CREG = 100 nF Chip Enabled to RSSI Ready 3.0 ms See Table 11 for more details Tx to Rx Turnaround Time 150 µs + (5 × TBIT) Time to synchronized data out, includes AGC settling; see the AGC Information and Timing section LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 µA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH DVDD − 0.4 V IOH = 500 µA Output Low Voltage, VOL 0.4 V IOL = 500 µA CLKOUT Rise/Fall 5 ns CLKOUT Load 10 pF TEMPERATURE RANGE, TA −40 +85 °C POWER SUPPLIES Voltage Supply VDD 2.3 3.6 V All VDD pins must be tied together Transmit Current Consumption FRF = 915 MHz, VDD = 3.0 V, PA is matched to 50 Ω −20 dBm 14.8 mA Combined PA and LNA matching network as on EVAL-ADF7020DBZ1 through EVAL-ADF7020DBZ3 boards, VCO_BIAS_SETTING = 12 −10 dBm 15.9 mA 0 dBm 19.1 mA 10 dBm 28.5 mA 10 dBm 26.8 mA PA matched separately with external antenna switch, VCO_BIAS_SETTING = 12 Receive Current Consumption Low Current Mode 19 mA High Sensitivity Mode 21 mA Power-Down Mode Low Power Sleep Mode 0.1 1 µA 1 Higher data rates are achievable, depending on local regulations. 2 For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section. 3 For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section. 4 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 5 For matching details, see the LNA/PA Matching section and the AN-764 Application Note. 6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. 7 See Table 5 for a description of different receiver modes. 8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

Rev. E | Page 10 of 47 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to GND1 −0.3 V to +5 V Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C MLF θJA Thermal Impedance 26°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec 1 GND = GND1 = RFGND = GND4 = VCO GND = 0 V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV , and is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION

1. EXPOSED PAD MUST BE CONNECTED TO GROUND.

Figure 6. Pin Configuration Table 4. Pin Function Descriptions 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. pin and ground for regulator stability and noise rejection. possible to this pin. All VDD pins should be tied together. 5 RFGND Ground for Output Stage of Transmit ter. All GND pins should be tied together. input to ensure maximum power transfer. See the LNA/PA Matching section. 7 RFINB Complementary LNA Input. See the LNA/PA Matching section. 8 R LNA External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. 9 VDD4 Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. for regulator stability and noise rejection. 12 GND4 Ground for LNA/MIXER Block. 19, 22 GND4 Ground for LNA/MIXER Block. CE is low, and the part must be reprogrammed once CE is brought high. the fourteen latches. A latch is selected using the control bits.

Rev. E | Page 12 of 47 Pin No. Mnemonic Description 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin. 28 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. 29 GND2 Ground for Digital Section. 30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. 31 CREG2 Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 32 VDD2 Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. 33 INT/LOCK Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay. 34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. 35 DATA CLK In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section. 36 CLKOUT A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio. 37 MUXOUT This pin provides the LOCK_DETECT signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include REGULATOR_READY, which is an indicator of the status of the serial interface regulator. 38 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. 39 OSC1 The reference crystal should be connected between this pin and OSC2. 40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 μF capacitor. 41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor. 44 to 47 GND, GND1, VCO GND Grounds for VCO Block. 48 CVCO A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise. EP Exposed Pad. The exposed pad must be connected to ground.

applied to OSC2 with R1_DB12 set low. Figure 19. Oscillator Circuit on the ADF7020

1 TO 15

Figure 20. CLKOUT Stage the clock edges to reduce these spurs at fCLK. as the reference clock to the phase frequency detector (PFD). components. The R register defaults to R = 1 on power-up. Figure 21. MUXOUT Circuit remains high until 25 ns phase error is detected at the PFD. detect, it is more widely used than analog lock detect. been detected, this output is high with narrow low going pulses.

current setting under all conditions is 0xA. Figure 24. Voltage-Controlled Oscillator (VCO)

868 MHz to 956 MHz (and 433 MHz using divide-by-2) to a

spurs are not attenuated by the loop. away from integer multiples of the PFD.

The output power is set using Bits R2_DB[9:14]. active state of the TxData input is set by Bits R2_DB[9:14].

6 R2_DB[9:14]

Figure 25. PA Configuration in FSK/GFSK Mode Figure 26. PA Configuration in ASK/OOK Mode pole antennas. See the LNA/PA Matching section for details. Select FSK using Bits R2_DB[6:8]. Figure 27. FSK Implementation

Rev. E | Page 19 of 47 Gaussian Frequency Shift Keying (GFSK) Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the TxData. A TxCLK output line is provided from the ADF7020 for synchronization of TxData from the microcontroller. The TxCLK line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate. Setting Up the ADF7020 for GFSK To set up the frequency deviation, set the PFD and the modulation control bits. 122 2]Hz[ m DEVIATION PFDGFSK ×= where m is GFSK_MOD_CONTROL, set using R2_DB[24:26]. To set up the GFSK data rate, COUNTERINDEXFACTORDIVIDER PFDDR __]bps[ ×= The INDEX_COUNTER variable controls the number of intermediate frequency steps between the low and high frequency. It is usually possible to achieve a given data rate with various combinations of DIVIDER_FACTOR and INDEX_COUNTER. Choosing a higher INDEX_COUNTER can help in improving the spectral performance. Amplitude Shift Keying (ASK) Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2. A 0 TxData bit sends Bits R2_DB[15:20] to the DAC. A high TxData bit sends Bits R2_DB[9:14] to the DAC. A maximum modulation depth of 30 dB is possible. On-Off Keying (OOK) On-off keying is implemented by switching the output stage to a certain power level for a high TxData bit and switching the output stage off for a zero. For OOK, the transmitted power for a high input is programmed using Bits R2_DB[9:14]. Gaussian On-Off Keying (GOOK) Gaussian on-off keying represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian filtered transitions, the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired BW , especially if it is not possible to increase the loop filter BW > 300 kHz. The GOOK sampling clock samples data at the data rate (see the Setting Up the ADF7020 for GFSK section).

mode, extra digital filtering is performed on the RSSI value. level can be converted to input power in dBm.

1. FWR = FULL WAVE RECTIFIER

Figure 29. RSSI Block Diagram R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz. where BBOS_CLK_DIVIDE can be set to 4, 8, or 16. for a programmed time to allow transients to settle. adjusting the appropriate parameters. readback register (see the Readback Format section). GAIN_MODE_CORRECTION is given by the values in Table 6. Table 6. Gain Mode Correction in the front-end matching network/antenna. Select these using the demodulator select bits, R4_DB[4:5]. presence of additive white Gaussian noise (AWGN).

Figure 30. FSK Correlator/Demodulator Block Diagram the demodulated bit stream at the output of the discriminator. the more traditional FSK demodulators. frequency deviation (see the AFC section). of the PLL (CDR_CLK) must be set at 32 times the data rate. accommodate frequency errors of up to ±2%. frequency that is used by the FSK transmitter. Register section, second comment. Table 7. When K Is Even Table 8. When K Is Odd

Table 9. Register Settings1

1 The latest version of the ADF7020 configuration software can aid in

calculating register settings. Figure 31 shows a block diagram of the linear FSK demodulator. Figure 31. Block Diagram of Frequency Measurement System and is linearly proportional to the frequency of the limiter outputs. demodulator, set Bits R4_DB[4:5] to 00. Register 3—Receiver Clock Register section, second comment. in Register 10 for robust operation over the full input range. This improves the receiver’s AM immunity performance. the ADF7020 (in FSK mode only). the fractional-N synthesizer’s N divider. equal to the IF frequency of 200 kHz.

the synthesizer N divider using an internal PI control loop. Figure 18. The maximum AFC frequency range is ±50 kHz, one ±50 ppm crystal and one ±8 ppm TCXO. in Register 4 at the expense of Rx sensitivity. INT/LOCK is asserted by the ADF7020. after nine data clock cycles. error tolerance value is assigned in Bits R5_DB[6:7].

Figure 36. Typical Format of a Transmit Protocol is a dc-balanced pattern such as a 10101010… sequence. synchronization time of the received bit stream in the receiver. error between the actual data rate and the on-board CDR_CLK/32.

11.0592 MHz XTAL gives a 0% nominal error between the

rate, which is twice the effective data rate. the ADF7020 in either Tx or Rx mode after CE is brought high. 200 kHz and to toggle the Tx/Rx bit. Table 10. Minimum Register Writes Required for Tx/Rx Setup sequence and associated timing for power-up from standby mode. connections shown in Figure 37 and Figure 38. Figure 37. ADuC841 to ADF7020 Connection Diagram Figure 38. ADSP-BF533 to ADF7020 Connection Diagram

Figure 40. Tx Programming Sequence and Timing Diagram

Figure 41. Application Circuit

determined by the value of the four control bits (C4 to C1). puts the SREAD pin back in three-state. signals with either the linear or correlator demodulator active. product code for the ADF7020 should read back as PC = 0x200. The current revision code should read as RV = 0x8. should be read back as the default value. Figure 42. Readback Value Table

0 TRANSMIT

0 REGULATOR READY (DEFAULT)

0 R DIVIDER OUTPUT

0 N DIVIDER OUTPUT

0 DIGITAL LOCK DETECT

1 ANALOG LOCK DETECT

1 THREE-STATE

1 PLL TEST MODES

0 PLL OFF

1 PLL ON

Figure 43. Register 0—N Register  The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and controls the state of the internal Tx/Rx switch. operating frequency, due to removal of the divide-by-2 stage in the feedback path.

0 OFF

Figure 44. Register 1—Oscillator/Filter Register the 902 MHz to 928 MHz band. numbers are specified for these VCO Adjust and Bias settings.

Figure 45. Register 2—Transmit Modulation Register (ASK/OOK Mode)  See the Transmitter section for a description of how the PA bias affects the power amplifier level. The default level is 9 μA. If maximum power is needed, program this value to 11 μA.  D7, D8, and D9 are don’t care bits.

Figure 46. Register 2—Transmit Modulation Register (FSK Mode)  When operating in the 431 MHz to 478 MHz band, fSTEP = PFD/215.

Figure 47. Register 2—Transmit Modulation Register (GFSK/GOOK Mode)  GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212.  When operating in the 431 MHz to 478 MHz band, GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/213.  Data Rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).

Figure 48. Register 3—Receiver Clock Register Note that this can affect your choice of XTAL, depending on the desired data rate.

Figure 49. Register 4—Demodulator Setup Register where the cutoff frequency (fCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate. where SEQ_CLK is defined in the Register 3—Receiver Clock Register section.

12 BITS

16 BITS

20 BITS

24 BITS

0 ERRORS

1 ERROR

2 ERRORS

3 ERRORS

Figure 50. Register 5—Sync Byte Register  Sync byte detect is enabled by programming Bits R4_DB[25:23] to 010 or 011.  Choose a sync byte pattern that has good autocorrelation properties, for example, 0x123456.

Figure 51. Register 6—Correlator/Demodulator Register  See the FSK Correlator/Demodulator section for an example of how to determine register settings.  Nonadherence to correlator programming guidelines results in poorer sensitivity. formula is XTAL/FILTER_CLOCK_DIVIDE.  DISCRIMINATOR_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section. Maximum value = 600. linearity is a concern. See Table 5 for details of the different Rx modes.

Figure 52. Register 7—Readback Setup Register method of using the battery readback function because most configurations typically require AGC.  Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.  See the Readback Format section for more information.

Figure 53. Register 8—Power-Down Test Register  For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.  It is not necessary to write to this register under normal operating conditions.

Figure 54. Register 9—AGC Register AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. Default register setting = 0xB2 31E9.  AGC high and low settings must be more than 30 apart to ensure correct operation.  LNA gain of 30 is available only if LNA mode, R6_DB15, is set to 0.

Figure 57. Register 12—Test Register This register does not need to be written to in normal operation. received bit stream to measure the received signal quality. Provide analog FM demodulation. maximum dynamic range of the DAC. removal (needed for linear demodulation only, 0x02 800C). above the demodulated data rate.

Figure 58. Register 13—Offset Removal and Signal Gain Register  Ki (default) = 3. Kp (default) = 2.

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

0.05 MAX

0.02 NOM

0.20 MIN

0.20 REF

Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] registered trademarks are the prop erty of their respective owners.