ADF7010

ADF7010 (Rev. 0) - Obsolete

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 20

Technical content

REV. 0 a Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADF7010 High Performance ISM Band ASK/FSK/GFSK Transmitter IC

FEATURES

Single Chip Low Power UHF Transmitter

902 MHz–928 MHz Frequency Band

On-Chip VCO and Fractional-N PLL 2.3 V–3.6 V Supply Voltage Programmable Output Power –16 dBm to +12 dBm, 0.3 dB Steps Data Rates up to 76.8 kbps Low Current Consumption 28 mA at 8 dBm Output Power-Down Mode (<1 /H9262A) 24-Lead TSSOP Package

APPLICATIONS

Low Cost Wireless Data Transfer Wireless Metering Remote Control/Security Systems Keyless Entry FUNCTIONAL BLOCK DIAGRAM VCO OOK/ASK LDO REGULA TOR MUXOUT LOCK DETECT SERIAL INTERFACE FREQUENCY COMPENSA TION CENTER FREQUENCY /H11548 FRACTIONAL N SIGMA-DEL T A OOK/ASK PFD/ CHARGE PUMP /H11548 R /H11548 CLK PA FSK/GFSK OSC1 OSC2 CLKOUT CPVDD CPGND CREG CVCO VCOGND VDD RFOUT RFGND CREG RSET MUXOUT TESTAGNDCE CLK DATA LE TxDATA TxCLK DGND DVDD GENERAL DESCRIPTION The ADF7010 is a low power OOK/ASK/FSK/GFSK UHF transmitter designed for use in ISM band systems. It contains an integrated VCO and sigma-delta fractional-N PLL. The output power, channel spacing, and output frequency are pro- grammable with four 24-bit registers. The fractional-N PLL enables the user to select any channel frequency within the U.S.

902 MHz–928 MHz band, allowing the use of the ADF7010 in

frequency hopping systems. It is possible to choose from the four different modulation schemes: Binary or Gaussian Frequency Shift Keying (FSK/ GFSK), Amplitude Shift Keying (ASK), or On/Off Keying (OOK). The device also features a crystal compensation register that can provide /H110061 ppm resolution in the output frequency. Indirect temperature compensation of the crystal can be accom- plished inexpensively using this register. Control of the four on-chip registers is via a simple 3-wire inter- face. The devices operate with a power supply ranging from 2.3 V to 3.6 V and can be powered down when not in use. OBSOLETE

REV. 0–2– ADF7010–SPECIFICATIONS1 (VDD = 2.3 V to 3.6 V, GND = 0 V, T A = TMIN to TMAX, unless otherwise noted. Typical specifications are at V DD = 3 V, TA = 25/H11543C.) Parameter Min Typ Max Unit RF CHARACTERISTICS Output Frequency Ranges U.S. ISM Band 902 928 MHz Phase Frequency Detector Frequency 3.625 20 MHz @ 928 MHz TRANSMISSION PARAMETERS Transmit Rate FSK 0.3 76.8 kbps ASK 0.3 9.6 kbps GFSK 0.3 76.8 kbps Frequency Shift Keying FSK Separation2, 3 1 110 kHz, Using 3.625 MHz PFD 4.88 620 kHz, Using 20 MHz PFD Gaussian Filter /H9252t 0.5 Amplitude Shift Keying Depth 30 dB, Max Output Power 2 dBm On/Off Keying 40 dB Output Power Output Power Variation Max Power Setting 9 12 dBm, V DD = 3.6 V 11 dBm, V DD = 3.0 V 9.5 dBm, V DD = 2.3 V Programmable Step Size –16 dBm to +12 dBm 0.3125 dB LOGIC INPUTS VINH, Input High Voltage 0.7 /H11003 VDD V VINL, Input Low Voltage 0.2 /H11003 VDD V IINH/IINL, Input Current /H110061 mA CIN, Input Capacitance 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS VOH, Output High Voltage DVDD – 0.4 V, IOH = 500 mA VOL, Output Low Voltage 0.4 V, IOL = 500 mA CLKOUT Rise/Fall Time 16 ns, F CLK = 4.8 MHz into 10 pF CLKOUT Mark: Space Ratio 50:50 POWER SUPPLIES Voltage Supply DVDD 2.3 3.6 V Transmit Current Consumption –20 dBm (0.01 mW) 12 mA –10 dBm (0.1 mW) 15 mA 0 dBm (1 mW) 20 mA +8 dBm (6.3 mW) 28 mA +12 dBm (16 mW) 40 mA Crystal Oscillator Block Current Consumption 190 mA Regulator Current Consumption 380 mA Power-Down Mode Low Power Sleep Mode 0.2 1 mA OBSOLETE

REV. 0 ADF7010 –3– Parameter Min Typ Max Unit PHASE-LOCKED LOOP VCO Gain 80 MHz/V @ 915 MHz Phase Noise (In-Band) 4 –80 dBc/Hz @ 5 kHz Offset Phase Noise (Out of Band) 5 –100 dBc/Hz @ 1 MHz Offset Spurious 100 kHz Loop BW Integer Boundary6 –55 dBc, 50 kHz Loop Reference –50 dBc Harmonics7 –14 dBc Second Harmonic VDD = 3.0 V –27 –18 dBc Third Harmonic VDD = 3.0 V –21 –18 dBc All Other Harmonics –35 dBc REFERENCE INPUT Crystal Reference 3.625 20 MHz External Oscillator 3.625 40 MHz Input Level, High Voltage 0.7 /H11003 VDD V Input Level, Low Voltage 0.2 /H11003 VDD V FREQUENCY COMPENSATION Pull In Range of Register 1 100 ppm PA CHARACTERISTICS RF Output Impedance High Range Amplifier 16 – j33 W, ZREF = 50 W TIMING INFORMATION Chip Enabled to Regulator Ready 7 50 200 ms Crystal Oscillator to CLK OUT OK 2 ms, 19.2 MHz Xtal TEMPERATURE RANGE, TA –40 +85 /H11034C NOTES 1Operating temperature range is as follows: –40 ∞C to +85∞C. 2 Frequency Deviation = (PFD Frequency /H11003 Mod Deviation )/2 12. 3 GFSK Frequency Deviation = (PFD Frequency /H11003 2m )/212 where m = Mod Control. 4 VDD = 3 V, PFD = 19.2 MHz, PA = 8 dBm

5 VDD = 3 V, Loop Filter BW = 100 kHz

6 Measured >1 MHz away from integer channel. See Successful Design with ADF7010 Transmitter application note. 7 Not production tested. Based on characterization. Specifications subject to change without notice. OBSOLETE

Guaranteed by design but not production tested. Figure 1. Timing Diagram for extended periods may affect device reliability. 3GND = CPGND = RFGND = DGND = AGND = 0 V. to avoid performance degradation or loss of functionality.

REV. 0 ADF7010 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1R SET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 4.7 k W as default: I R CP MAX SET = 95. So, with RSET = 4.7 kW, ICPMAX = 2.02 mA. 2 CPVDD Charge Pump Supply. This should be biased at the same level as RFV DD and DVDD. The pin should be decoupled with a 0.1 mF capacitor as close to the pin as possible. 3C P GND Charge Pump Ground 4C P OUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 5C EC hip Enable. A logic low applied to this pin powers down the part. This must be high for the part to function. This is the only way to power down the regulator circuit. 6 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. 7 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input. 8L EL oad Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 9T xDATA Digital data to be transmitted is input on this pin. 10 TxCLK GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7010. The clock is provided at the same frequency as the data rate. 11 MUXOUT This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled reference frequency to be accessed externally. Used commonly for system debug. See Function Register Map.

12 D GND Ground Pin for the RF Digital Circuitry

13 CLK OUT The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock input of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can be reduced with a series RC. For 4.8 MHz output clock, a series 50 W into 10 pF will reduce spurs to < –50 dBc. Defaults on power-up to divide by 16. 14 OSC2 Oscillator Pin. If a single-ended reference is used (such as a TCXO), it should be applied to this pin. When using an external signal generator, a 51 W resistor should be tied from this pin to ground. The XOE bit in the R Register should set high when using an external reference. PIN CONFIGURATION TOP VIEW (Not to Scale) TSSOP ADF7010 DGND MUXOUT TxCLK TxDA T A LE RSET CPVDD CPGND CPOUT CLK CE CLKOUT OSC2 OSC1 VCOGND TEST CREG CVCO VCOIN AGND DVDD RFGND RFOUT DATA OBSOLETE

REV. 0–6– ADF7010 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function 15 OSC1 Oscillator Pin. For use with crystal reference only. This is three-stated when an external reference oscillator is used.

16 VCOGND Voltage Controlled Oscillator Ground

17 TEST Input to the RF fractional-N divider. This pin allows the user to connect an external VCO to the part. Disabling the internal VCO activates this pin. If the internal VCO is used, this pin should be grounded. 18 DV DD Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 19 RF GND Ground for Output Stage of Transmitter 20 RF OUT The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output should be impedance matched to the desired load using suitable components. See the Output RF Stage section. 21 A GND Ground Pin for the RF Analog Circuitry 22 VCO IN The tuning voltage on this pin determines the output frequency of the Voltage Controlled Oscillator (VCO). The higher the tuning voltage the higher the output frequency. 23 C VCO A 0.22 mF capacitor should be added to reduce noise on VCO bias lines. Tied to C REG pin. 24 C REG A 2.2 mF capacitor should be added at C REG to reduce regulator noise and improve stability. A reduced capacitor will improve regulator power-on time but may cause higher spurious components. OBSOLETE

REV. 0 Typical Performance Characteristics–ADF7010 –7– RL = 10.0dBm VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 1kHz 915.7MHz SP AN 5.000MHz TPC 1. FSK Modulated Signal, F DEVIATION = 58 kHz, Data Rate = 19.2 kbps/s, 10 dBm RL = 10.0dBm VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 1MHz RBW = 3kHz 915.7MHz SP AN 500kHz 2dBm –36dBm @ 200kHz TPC 2. OOK Modulated Signal, Data Rate = 4.8 kbps/s, 4 dBm ST ART 800MHz STOP 7.750GHz +10dBm SECOND HARMONIC –22dBc THIRD HARMONIC –34dBc RBW 1.0MHz TPC 3. Harmonic Levels at 10 dBm Output Power. See Figure 15. 30.00/H9262s 901.000MHz 918.000MHz 935.000MHz 5.00/H9262s–20.00/H9262s 5.00/H9262s/DIV VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz TPC 4. PLL Settling Time, 902 MHz to 928 MHz, 23 /H9262s (±400 kHz) RBW 100kHz SP AN 50.00MHz915.7MHz +10dBm VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 100kHz +19.2MHz –61dBc TPC 5. PFD Spurious/Fractional Spurious SP AN 10.00kHz915.7MHz +10dBm VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 30Hz PN @ 4kHz 80dBc/Hz TPC 6. In-Band Phase Noise OBSOLETE

REV. 0–8– ADF7010 Ch1 500mV C1 FREQ 1.6MHz M 200ns C1 RISE 144.8ns C1 FALL 145.6ns C1 +DUTY 49.385 TPC 7. 1.6 MHz CLOCK OUT Waveform SP AN 5.00MHz915.7MHz +10dBm VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 10Hz +1.6MHz –53dBc TPC 8. Spurious Signal Generated by CLOCK OUT FREQUENCY – GHz –10 –15 –20 –25 SENSITIVITY – dBm TPC 9. N-Divider Input Sensitivity FREQUENCY 885 GAIN – MHz/V 945925915905895 100 110 935 VDD = 3V TA = 25/H11543C TPC 10. Typical VCO Gain PA SETTING – MODULA TION REGISTER LEVEL – dBm –30 VDD = 2.2V VDD = 3.0V VDD = 3.6V –25 –20 –15 –10 60 80 100 120 MID RANGELOW RANGE HIGH RANGE TPC 11. PA Output Programmability, T A = 25∞C SUPPL Y VOL T AGE – V 2.2 CURRENT – mA 3.2 3.6 TPC 12. I DD vs. VDD @ 10 dBm OBSOLETE

REV. 0 ADF7010 –9– REGISTER MAPS RF N REGISTER MODULATION REGISTER FUNCTION REGISTER RF R REGISTER F1R1 11-BIT FREQUENCY ERROR CORRECTION4-BIT R-VALUE DB19 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CLKOUT CL4 XOERESERVED C2 (0) C1 (0) CONTROL BITS DB1 DB0 F2 F3 F4 F5 F6 F7 F8 F9F10 F11R2 R3 R4X1CL1CL2CL3R1 R2 C2 (0) C1 (1)M1M12 12-BIT FRACTIONAL-N 8-BIT INTEGER-N DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB20DB21DB23 DB22 VCOBAND LD PRECISION M2M3 M4M5M6 M7 M8 M9M10M11N1 N2 N3 N4 N5 N6 N7V1LDP DB16 DB15 DB14DB17DB20 DB19 DB18DB21 C2 (1) C1 (0) MODULATION DEVIATION MODULATION SCHEME DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 POWER AMPLIFIER DB22DB23 INDEX COUNTER GFSK MOD CONTROL PRE- SCALER P1 P5P6P7 S1 S2 P1 P2 P3 P4D1 D2 D3 D4 D5 D6 D7MC1MC2MC3IC1 IC2 MUXOUT M2 M1 PD1 TEST MODES C2 (1) C1 (1) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB15 DB14 DB13 DB12 DB11 I1 DATA INVERT DB16 PD3 PLL ENABLE CLKOUT ENABLE PA ENABLE CHARGE PUMPFAST LOCK DB17DB22 DB21 DB20 DB19DB23 VCO DISABLE DB18 PD2CP1CP2CP3CP4VP1M3 M4T1 T2 T3 T4 T5 T6 T7 T8 T9 DB18DB20DB21DB22DB23 CONTROL BITS CONTROL BITS CONTROL BITS OBSOLETE

REV. 0–10– ADF7010 RF R REGISTER e.g., F-COUNTER OFFSET = /H115461, FRACTIONAL OFFSET = /H115461/2 F-COUNTER OFFSETF1F2F3F11 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 R4 R3 R2 R1 RF R COUNTER DIVIDE RATIO

0 XTAL OSCILLATOR ON

1 XTAL OSCILLATOR OFF

DIVIDE RATIO CL4 CL3 CL2 CL1 F1R1 11-BIT FREQUENCY ERROR CORRECTION4-BIT R-VALUE DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CLKOUT DB20 DB19 CL4 XOE DB21DB23 DB22 RESERVED C2 (0) C1 (0) CONTROL BITS DB1 DB0 F2 F3 F4 F5 F6 F7 F8 F9F10 F11R2 R3 R4X1CL1CL2CL3R1 R2 CLKOUT OBSOLETE

REV. 0 ADF7010 –11– RF N REGISTER C2 (0) C1 (1)M1M12 CONTROL BITS12-BIT FRACTIONAL-N 8-BIT INTEGER-N DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB20DB21DB23 DB22 M2 M3 M4 M5 M6 M7 M8 M9M10M11N1 N2 N3 N4 N5 N6 N7V1LDP THE N-VALUE CHOSEN IS A MINIMUM OF P2 + 3P + 3. FOR PRESCALER = 8/9 THIS MEANS A MINIMUM N DIVIDE OF 91. N COUNTER DIVIDE RATIO 0 0011111 3 1 0 0100000 3 2 0 0100001 3 3 0 0100010 3 4 1 1111101 2 53 1 1111110 2 54 1 1111111 2 55 N8 N7 N6 N5 N4 N3 N2 N1 MODULUS DIVIDE RATIO M12 M11 M10 M3 M2 M1 VCO BAND MHZ 0 902–928 1 451–464 LOCK DETECT PRECISION 0 3 CYCLES <15ns 1 5 CYCLES <15ns e.g., SETTING F = 0 IN FSK MODE TURNS ON THE SIGMA-DELTA WHILE THE PLL IS AN INTEGER VALUE e.g., MODULUS DIVIDE RATIO = 2048 –> FRACTION 1/2 LDP VCO BAND LD PRECISION OBSOLETE

REV. 0–12– ADF7010 MODULATION REGISTER D7 D6 . D2 D1 P7 P6 . P2 P1 D7. . . . D3 D2 D1 F DEVIATION IF FREQUENCY SHIFT KEYING SELECTED 0 . . . . 0 0 0 PLL MODE 0 . . . . 0 0 11 /H11547 F STEP 0 . . . . 0 1 02 /H11547 FSTEP 0 . . . . 0 1 13 /H11547 FSTEP 1 . . . . 1 1 127 /H11547 F STEP D7 D3 D2 D1 DIVIDER FACTOR 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 11 1 1 127 INDEX COUNTER 0 0 16 0 1 32 1 0 64 1 1 128 GFSK MOD CONTROL 000 0 001 1 ... . 111 7 MODULATION SCHEME 0 0 FSK 0 1 GFSK 1 0 ASK 1 1 OOK S2 S1 0 4/5 1 8/9 FSTEP = FPFD/212 DB16 DB15 DB14DB17DB20 DB19 DB18DB21 C2 (1) C1 (0) MODULATION DEVIATION DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 POWER AMPLIFIER DB22DB23 INDEX COUNTER GFSK MOD CONTROL P1 P5 P6 P7 S1 CONTROL BITS S2 P1 P2 P3 P4D1 D2 D3 D4 D5 D6 D7MC1MC2MC3IC1 IC2 P1 RF PRESCALER MC3 MC2 MC1 IC2 IC1 POWER AMPLIFIER OUTPUT LEVELIF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0 IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED PRE- SCALER MODULATION SCHEME 00 .X X P A OFF 01 .0 0 /H1154616.0dBm 01 .0 1 /H1154616/H115451/H11547(10/32) 01 .1 1 /H1154616/H1154531/H11547(10/32) 10 .0 0 /H115466dBm 10 .0 1 /H115466/H115451/H11547(10/32) 10 .1 1 /H115466/H115451/H11547(10/32) 11 .0 0 2 d B m 11 .0 1 2 /H115451/H11547(10/32) 11 .. . . 11 .1 1 12dBm 00. X X P A OFF 01. 0 0 /H1154616.0dBm 01. 0 1 /H1154616/H115451/H11547(10/32) 01. 1 1 /H1154616/H1154531/H11547(10/32) 10. 0 0 /H115466dBm 10. 0 1 /H115466/H115451/H11547(10/32) 10. 1 1 /H115466/H115451/H11547(10/32) 11. 0 0 2 d B m 11. 0 1 2 /H115451/H11547(10/32) 11. . . . 11. 1 1 12dBm OBSOLETE

REV. 0 ADF7010 –13– FUNCTION REGISTER M4 M3 M2 M1 MUXOUT 0 0 0 0 LOGIC LOW 0 0 0 1 LOGIC HIGH 0 0 1 0 THREE-STATE 0 0 1 1 REGULATOR READY (DEFAULT) 0 1 0 0 DIGITAL LOCK DETECT 0 1 0 1 ANALOG LOCK DETECT 0 1 1 0 R DIVIDER / 2 OUTPUT 0 1 1 1 N DIVIDER / 2 OUTPUT 1 0 0 0 RF R DIVIDER OUTPUT 1 0 0 1 RF N DIVIDER OUTPUT 1 0 1 0 DATA RATE 1 0 1 1 LOGIC LOW 1 1 0 0 LOGIC LOW 1 1 0 1 LOGIC LOW 1 1 1 0 NORMAL TEST MODES 1 1 1 1 SIGMA-DELTA TEST MODES I1 DATA INVERT

0 DATA

1 DATA

CP2 CP1 ICP (mA) 2.7k/H9024 4.7k/H9024 10k/H9024 0 0 0.50 0.29 0.14 0 1 1.50 0.87 0.41 1 0 2.51 1.44 0.68 1 1 3.51 2.02 0.95 CP4 CP FLOCK DOWN 0B LEED OFF 1B LEED ON VP1 VCO DISABLE

0 VCO ON

1 VCO OFF

0 PLL OFF

1 PLL ON

C2 (1) DB19 DB18 DB17 DB16 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB20DB21DB23 DB22 T2 T3 T4 T5T1 M2 M3 M4M1 VP1 CP4 C2CP3 C1 PD3 I1 PD2 PD1 C1 (1) DB15 OBSOLETE

REV. 0–14– ADF7010 DEFAULT VALUES FOR REGISTERS C2 (0) C1 (1)01 CONTROL BITS12-BIT FRACTIONAL-N 8-BIT INTEGER-N DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB20DB21DB23 DB22 VCO BAND LD PRECISION N REGISTER 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 00 0 MODULATION REGISTER DB16 DB15 DB14DB17DB20 DB19 DB18DB21 C2 (1) C1 (0) MODULATION DEVIATION MODULATION SCHEME DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 POWER AMPLIFIER DB22DB23 INDEX COUNTER GFSK MOD CONTROL PRE- SCALER 1 011 0 CONTROL BITS 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 FUNCTION REGISTER MUXOUT 1 1 0 TEST MODES C2 (1) C1 (1) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB15 DB14 DB13 DB12 DB11 DB17DB22 DB21 DB20 DB19DB23 VCO DISABLE CONTROL BITS DB18 01 10 0 00 0 0 0 0 0 0 0 0 0 0 11-BIT FREQUENCY ERROR CORRECTION4-BIT R-VALUE DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CLKOUT DB20 DB19 XOE DB21DB23 DB22 RESERVED C2 (0) C1 (0) CONTROL BITS DB1 DB0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 00 0 R REGISTER OBSOLETE

by default on power-up and is disabled by bringing CE low. levels should be applied to OSC2, with XOE set high. Figure 2. Oscillator Circuit on the ADF7010 is available. This divide is set by the 4 MSBs in the R register. OUT defaults to divide by 16.

1 TO 15

Figure 3. CLKOUT Stage spurious components. The R register defaults to R = 1 on power-up. Figure 4. PFD Stage transfer function and minimizes phase noise and reference spurs. Bits M1 to M4 in the function register.

N Register should be set to 1. regulator to reduce internal noise. Figure 7. Voltage Controlled Oscillator the output power in the selected range. up the same way but using the bits D1–D7. Figure 8. Output Stage registers using a 3-wire interface. (CLK, Data, and Load Enable).

00 R Register

01 N Register

10 Modulation Register

11 Function Register

LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1. Figure 9. Output Stage Matching

in better phase noise for higher PFDs. Increasing the PFD reduces your resolution at the output. by setting Bits S1 and S2 to zero in the modulation register. Figure 13. FSK Implementation by the transmitted spectrum by digitally prefiltering the TxDATA. register that clocks data to the transmitter at the exact data rate. Figure 14. TxCLK Pin Synchronizing Data for GFSK is possible. ASK is selected by setting Bit S2 = 1 and Bit S1 = 0. Bits S1 and S2 to 1 in the modulation register.

902 MHz to 928 MHz to a resolution of < 100 Hz, as well as

avoidance by changing the RF channel on a regular basis. cies are at multiples of the reference, which is typically > 10 MHz. avoiding very small or very large values in the fractional register. spurs to < –60 dBc for the same conditions above.

Figure 15. Application Diagram

6.40 BSC