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24 GHz, ISM Band, Multichannel
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FEATURES
24 GHz to 24.25 GHz VCO (industrial, scientific, and medical (ISM) radio band) 2-channel 24 GHz power amplifier with 8 dBm output Single-ended outputs 2-channel muxed outputs with mute function Programmable output power LO output buffer RF frequency range: 24 GHz to 24.25 GHz Power control detector Auxiliary 8-bit ADC High and low speed FMCW ramp generation 25-bit fixed modulus allows subhertz frequency resolution PFD frequencies up to 110 MHz Normalized phase noise floor of −222 dBc/Hz Programmable charge pump currents ±5°C temperature sensor 4-wire SPI ESD performance HBM: 2000 V CDM: 250 V Qualified for automotive applications
APPLICATIONS
The ADF5902 is a 24 GHz transmitter (Tx) monolithic microwave integrated circuit (MMIC) with an on-chip, 24 GHz voltage controlled oscillator (VCO). The VCO features a fractional-N frequency synthesizer with waveform generation capability with programmable grid array (PGA) and dual transmitter channels for radar systems. The on-chip, 24 GHz VCO generates the
24 GHz signal for the two transmitter channels and the local
oscillator (LO) output. Each transmitter channel contains a power control circuit. There is also an on-chip temperature sensor. Control of all the on-chip registers is through a simple, 4-wire serial peripheral interface (SPI). The ADF5902 comes in a compact, 32-lead, 5 mm × 5 mm LFCSP package. FUNCTIONAL BLOCK DIAGRAM 16746-001 TXOUT1 TXOUT2 LOOUTVTUNE RSET GND TX_AHI ATEST RF_AHI AHI DVDD VREGC1 C2 MUXOUT VCO_AHI REFIN N DIVIDER VCO CAL R DIVIDER TEMPERATURE SENSOR ADC BIASREGULATOR ADC ADC ADF5902 + PHASE FREQUENCY DETECTOR READBACK CONTROL ADC OUTPUT FREQUENCY COUNTER CHARGE PUMP CPOUT 32-BIT DATA REGISTER DOUT LE DATA CLK CE THIRD-ORDER FRACTIONAL INTERPOLATOR RAMP GENERATIONTX_DATA CP_AHI RDIV NDIV RAMP STATUS DVDD GND FMCW RAMP GENERATION PLL Figure 1.
Rev. 0 | Page 2 of 39 TABLE OF CONTENTS
REVISION HISTORY
12/2018—Revision 0: Initial Version
Rev. 0 | Page 3 of 39 SPECIFICATIONS AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = CP_AHI = 3.3 V ± 5%, GND = 0 V , dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. The operating temperature range is −40°C to +105°C. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments OPERATING CONDITIONS RF Frequency Range 24 24.25 GHz VCO CHARACTERISTICS VTUNE 0.5 2.5 V VTUNE Impedance 100 kΩ VCO Phase Noise Performance Closed-loop, 10 kHz loop filter At 100 kHz Offset −88 dBc/Hz At 1 MHz Offset −108 dBc/Hz At 10 MHz Offset −128 dBc/Hz Amplitude Noise −150 dBc/Hz At 1 MHz offset Static Pulling VCO Frequency (fVCO) Change vs. Load ±2 MHz Open-loop into 2:1 voltage standing wave ratio (VSWR) load Dynamic Pulling Transmitter On or Off Switch Change ±10 MHz Open-loop Dynamic Pulling Transmitter to Transmitter Switch Change ±5 MHz Open-loop Pushing fVCO Change vs. AHI Change ±5 MHz/V Open-loop Spurious Level Harmonics −30 dBc Spurious Level Nonharmonics <−70 dBc POWER SUPPLIES AHI, TX_AHI, RF_AHI, VCO_AHI, DVDD, CP_AHI 3.135 3.3 3.465 V Total Current (ITOTAL)1 190 mA Software Power-Down Mode 1.2 mA Hardware Power-Down Mode 200 μA TRANSMITTER OUTPUT Output Power 2 8 12 dBm Output Impedance 50 Ω On to Off Isolation 30 dB Single transmitter output switched on to off Transmitter to Transmitter Isolation 25 dB Power-Up/Power-Down Time 200 ns LO OUTPUT Output Power −7 −1 +5 dBm Output Impedance 50 Ω On to Off Isolation 35 dB PHASE FREQUENCY DETECTOR (PFD) Phase Detector Frequency2 110 MHz CHARGE PUMP Charge Pump Current (ICP) Sink and Source Current Programmable High Value 4.48 mA RSET = 5.1 kΩ; RSET is a resistor to ground that sets the maximum charge pump output current Low Value 280 μA Absolute Accuracy 2.5 % R SET = 5.1 kΩ RSET Range 5.049 5.1 5.151 kΩ ICP Tristate Leakage Current 1 nA Sink and source current Sink and Source Matching 2 % 0.5 V < charge pump voltage (V CP) < CP_AHI − 0.6 V ICP vs. VCP 2 % 0.5 V < VCP < CP_AHI − 0.6 V ICP vs. Temperature 2 % V CP = CP_AHI/2
Rev. 0 | Page 4 of 39 Parameter Min Typ Max Unit Test Conditions/Comments NOISE CHARACTERISTICS Normalized Phase Noise Floor, Fractional-N Mode3 −222 dBc/Hz PLL loop bandwidth (BW) = 1 MHz Normalized 1/f Noise (PN1_f)4 −120 dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz TEMPERATURE SENSOR Analog Accuracy ±5 °C Following one point calibration Digital Accuracy ±5 °C Following one point calibration Sensitivity 6.4 mV/°C ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution 8 Bits Integral Nonlinearity (INL) ±1 LSB Differential Nonlinearity (DNL) ±1 LSB Least Significant Bit (LSB) 7.4 mV REFIN CHARACTERISITICS REFIN Input Frequency 10 260 MHz −5 dBm minimum to +9 dBm maximum biased at AHI/2 (ac coupling ensures 1.8 ÷ 2 bias); for frequencies < 10 MHz, use a dc-coupled, CMOS- compatible square wave with a slew rate > 25 V/μs REFIN Input Capacitance2 1.2 pF REFIN Input Current ±100 μA LOGIC INPUTS Input Voltage High (VIH) 1.4 V Low (VIL) 0.6 V Input Current (IINH, IINL) ±1 μA Input Capacitance (CIN)2 10 pF LOGIC OUTPUTS Output Voltage High (VOH)5 DVDD − 0.4 V Low (VOL) 0.4 V Output Current High (IOH) 500 μA Low (IOL) 500 μA 1 Following the initialization sequence described in the Initialization Sequence section, TA = 25°C, AHI = 3.3 V, fREFIN = 100 MHz, and RF = 24.025 GHz. 2 Guaranteed by design. Sample tested to ensure compliance. 3 This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate in-band phase noise performance as seen at the VCO output. 4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 5 DVDD selected from the IO level bit (Bit DB11 in Register 3).
precautions for handling and assembly. PCB thermal design is required. Table 4. Thermal Resistance measured in a one cubic foot sealed enclosure. 2 θJC is the junction-to-case thermal resistance.
3 Test Condition 1: thermal impedance simulated values are based on use of a
PCB with the thermal impedance pad soldered to GND.
- THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration Table 5. Pin Function Descriptions GND RF Ground. Tie all GND pins together. 2 TX OUT1 24 GHz Transmitter Output 1. ground plane as close as possible to this pin. TX_AHI must be the same value as AHI. 7 TX OUT2 24 GHz Transmitter Output 2. 9 ATEST Analog Test Output Pin. plane as close as possible to this pin. RF_AHI must be the same value as AHI. ground plane as close as possible to this pin. 1 nF, and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI. 18 VREG Internal 1.8 V Regulator Output. Connect a 220 nF ca pacitor to ground as close as possible to this pin. TX_DATA signal to the rising edge of REFIN. 20 CE Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device. 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 18 latches with the latch selected via the control bits. 25 MUXOUT Multiplexer Output. This multiplexer output allows various internal signals to be accessed externally. nominal voltage potential at the RSET pin is 0.62 V. filter, which, in turn, drives the VCO.
Rev. 0 | Page 8 of 39 Pin No. Mnemonic Description 29 V TUNE Control Input to the VCO. This voltage determines the output. 30 VCO_AHI Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane as close as possible to this pin. VCO_AHI must be the same value as AHI. 31 C1 Decoupling Capacitor 1. Place a 47 nF capacitor to ground as close as possible to this pin. 32 C2 Decoupling Capacitor 2. Place a 220 nF capacitor to ground as close as possible to this pin. EP Exposed Pad. The exposed pad must be connected to GND.
program modes in the ADF5902. register. Second, a new write must be performed on Register R5. the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5. Write to Register R6 first, followed by the write to Register R5. The frequency change begins after the write to Register R5. do not take effect until after the write to Register R5. Table 6. C5, C4, C3, C2, and C1 Truth Table
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5. Figure 21. Register Summary (Register 0 to Register 6)
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5. Figure 22. Register Summary (Register 7 to Register 12)
0 SS1 SS0 SW19
Figure 23. Register Summary (Register 13 to Register 17)
0010 L O G I C L O W
0101 R E S E R V E D
0110 R E S E R V E D
0111 C A L B U S Y
1000 R E S E R V E D
1001 R E S E R V E D
1010 R E S E R V E D
1101 R E S E R V E D
1110 R E S E R V E D
1DBR = DOUBLE-BUFFERED REGISTER.
0000 N O N E
0110 R E G S I T E R 5
0110 ADC READBACK
Figure 27. Register 3 (R3) With Bits[C5:C1] set to 00011, Register R3 is programmed. ADF5902. See Figure 27 for the truth table. ADF5902. See Figure 27 for the truth table.
0011000001 TEMPERATURE SENSOR TO ADC10
Figure 28. Register 4 (R4) With Bits[C5:C1] set to 00100, Register R4 is programmed.
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
0 RAMP DISABLED
Figure 29. Register 5 (R5) With Bits[C5:C1] set to 00101, Register R5 is programmed. is set to 0, the ramp function is disabled. required prior to repeating the single ramp function. Synthesis: a Worked Example section for more information.
0 DISABLED
1 ENABLED
1DBR = DOUBLE-BUFFERED REGISTER. Figure 31. Register 7 (R7) With Bits[C5:C1] set to 00111, Register R7 is programmed. bit to 1 performs a reset of the device and all register maps. Setting this bit to 0 returns the device to normal operation. CLK1 is less than or equal to 25 kHz. between the R counter and VCO calibration block.
Figure 35. Register 10 (R10 0x1D32A64A)
0 CONTINUOUS SAWTOOTH
1 SINGLE RAMP BURST
0 ENABLED
Figure 36. Register 11 (R11) as shown in Figure 35 using a hexadecimal word of 0x1D32A64A. With Bits[C5:C1] set to 01011, Register R11 is programmed. be set as shown in Figure 36. Register R5, set this bit to 1. more information, see the Ramp and Modulation section. this bit to 1 performs a counter reset of the device counters. Setting this bit to 0 returns the device to normal operation. Bit DB5 is shown as CNTR RESET in Figure 36.
1DBR = DOUBLE-BUFFERED REGISTER. Figure 37. Register 12 (R12) With Bits[C5:C1] set to 01100, Register R12 is programmed. setting the charge pump current when the doubler is enabled. mode. For normal charge pump operation, set this bit to 0.
Figure 39. Register 14 (R14) With Bits[C5:C1] set to 01110, Register R14 is programmed. Ramp and Modulation section). step (see the Ramp and Modulation section).
Figure 40. Register 15 (R15) With Bits[C5:C1] set to 01111, Register R15 is programmed. Bits[DB26:DB25] select the step word to be loaded (see Figure 40).
Figure 41. Register 16 (R16) Figure 42. Register 17 (R17) With Bits[C5:C1] set to 10000, Register R16 is programmed. reserved and must be set as shown in Figure 41. Bits[DB24:DB23] select the delay word to be loaded. activates the ramp in conjunction with Bit DB29 of Register 5. DATA pin to the rising edge of the REFIN reference input. When Bit DB20 is set to 0, this function is disabled. after Bit DB29 of Register 5 is toggled low. When Bit DB20 is set to 0, this function is disabled. enabled. When Bit DB19 is set to 0, this function is disabled. determines the duration of the ramp start delay.
down rate is 200 MHz at 9 μs. Table 7. Initialization Sequence
1 R7 0x02000007 Master reset
2 R11 0x0000002B Reset the counters
3 R11 0x0000000B Enable counters
4 R13 0x0018000D Enable ramp divider
5 R10 0x1D32A64A Reserved
6 R9 0x2A20B929 VCO calibration setup
7 R8 0x40003E88 Set the VCO frequency calibration divider clock to 100 kHz
8 R0 0x800FE520 Power up the device and LO
9 R7 0x01800827 PFD = 50 MHz, CLK1 = 2048
10 R6 0x00000006 Set the LSB FRAC = 0
12 R4 0x00000004 Set the ATEST pin to high impedance
14 R2 0x00020642 Set ADC clock to 1 MHz
15 R1 0xFFF7FFE1 Set the transmitter amplitude level
16 R0 0x800FE720 Start the VCO frequency calibration
17 R0 0x800FE560 Turn Tx1 on, Tx2 off, and LO on
18 R0 0x800FED60 Tx1 amplitude calibration
19 R0 0x800FE5A0 Turn Tx1 off, Tx2 on, and LO on
20 R0 0x800FF5A0 Tx2 amplitude calibration
21 R17 0x00000011 Reserved
22 R16 0x00000010 Ramp delay register
23 R15 0x0000120F Load step register with STEP_SEL = 0, step word is 144
24 R15 0x0200012F Load step register with STEP_SEL = 1, step word is 9
25 R15 0x0400120F Load step register with STEP_SEL = 2, step word is 144
26 R15 0x0600012F Load step register with STEP_SEL = 3, step word is 9
27 R14 0x012038EE Load deviation register with DEV_SEL = 0, DEV = 455, DEV offset = 9
28 R14 0x033C720E Load deviation register with DEV_SEL = 1, dev word= −1820, DEV
29 R14 0x052038EE Load deviation register with DEV_SEL = 2, dev word = 455, dev offset = 9
30 R14 0x73C720E Load deviation register with DEV_SEL = 3, dev word = −1820 dev
31 R13 0x0018050D Load the clock register with CLK DIV SEL = 0, CLK2_0 = 10
32 R13 0x0018052D Load the clock register with CLK DIV SEL = 1, CLK2_1 = 10
33 R13 0x0018054D Load the clock register with CLK DIV SEL = 2, CLK2_2 = 10
34 R13 0x0018056D Load the clock register with CLK DIV SEL = 3, CLK2_3 = 10
36 R9 0x2800B929 Normal Operation
37 R7 0x0100A027 PFD = 100 MHz, CLK1 = 10
38 R6 0x00000006 Set the LSB FRAC = 0
40 R4 0x00002004 Ramp down to MUXOUT
42 R11 0x0000010B Select ramp mode
(see the Temperature Sensor section). Table 8. Recalibration Sequence
6 R9 0x2A20B929 Reserved
36 R9 0x2800B929 Reserved
37 R7 0x0100A027 PFD set to 100 MHz, CLK_DIV1 = 10
39 R5 0x00F04005 Set INT word to 120, set MSB FRAC = 512; lock to
24.025 GHz
Rev. 0 | Page 33 of 39 TEMPERATURE SENSOR The ADF5902 has an on-chip temperature sensor that can be accessed on the ATEST pin or as a digital word on DOUT following an ADC conversion. The temperature sensor operates over the full operating temperature range of −40°C to +105°C. The accuracy can be improved by performing a one-point calibration at room temperature and storing the result in memory. With the temperature sensor on the analog test bus and test bus connected to the ATEST pin (Register 4 set to 0x0000A064), the ATEST voltage can be converted to temperature with the following equation: GAIN OFFATEST V V VeTemperatur C) ( (3) where: VATEST is the voltage on the ATEST pin. VOFF = 0.699 V , the offset voltage. VGAIN = 6.4 × 10−3, the voltage gain. The temperature sensor result can be converted to a digital word with the ADC and readback on DOUT with the following sequence: 1. Write 0x00012064 to Register R4 to connect the analog test bus to the ADC and the temperature sensor to the analog test bus. 2. Write 0x0002A802 to Register R2 to start the ADC conversion. 3. Write 0x0189FAC3 to Register R3 to set the ADC output data to DOUT . 4. Read back DOUT. 5. Write 0x00002064 to Register R4 to reset Register R4 to the initial value. 6. Write 0x00020642 to Register R2 to reset Register R2 to the initial value. Convert the DOUT word to temperature with the following equation: GAIN OFFLSB V V V ADCeTemperatur C) ( (4) where: ADC is the ADC code read back on DOUT. VLSB = 7.33 mV , the ADC LSB voltage. VOFF = 0.699 V , the offset voltage. VGAIN = 6.4 × 10−3, the voltage gain. RF SYNTHESIS: A WORKED EXAMPLE The following equation governs how to program the ADF5902: RFOUT = (INT + (FRAC/225)) × fREF × 2 (5) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. fREF = REFIN × ((1 + D)/(R × (1 + T))) (6) where: REFIN is the reference frequency input. D is the reference doubler bit, DB10 in Register R7 (0 or 1). R is the reference division factor. T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1). For example, in a system where a 24.125 GHz RF frequency output (RF OUT) is required and a 100 MHz reference frequency input (REFIN) is available, fREF is set to 50 MHz. From Equation 6, From Equation 5,
24.125 GHz = 50 MHz × (N + FRAC/225) × 2
Calculating the N and FRAC values, N = int(RFOUT/(fREF × 2)) = 241 FRAC = FMSB × 213 + FLSB FMSB = int(((RFOUT/(fREF × 2)) − N) × 212) = 1024 FLSB = int(((((RFOUT/(fREF × 2)) − N) × 212) − FMSB) × 213) = 0 where: F MSB is the 12-bit MSB FRAC value in Register R5. FLSB is the 13-bit LSB FRAC value in Register R6. int() makes an integer of the argument in parentheses. REFERENCE DOUBLER The on-chip reference doubler allows the input reference signal to be doubled. This doubling is useful for increasing the PFD compar- ison frequency. Doubling the PFD frequency typically improves the noise performance of the system by 3 dB.
DEV is a 16-bit word (Bits[DB20:DB5] in Register R14). DEV_OFFSET is a 4-bit word (Bits[DB24:DB21] in Register R14). Register R7 and 12-bit CLK2 divider in Register R13). Figure 49. The total ramp is separated into four sections. Each programmed frequency deviation and step time. CLK DIV SEL (Register R13, Bits[DB6:DB5]). DEV SEL (Register R14, Bits[DB26:DB25]). Step SEL (Register R15, Bits[DB26:DB25]). fDEV is the frequency deviation of a step. DEV is the deviation value (Register R14, Bits[DB20:DB5]). CLK1 is the CLK1 value (Register R7, Bits[23:12]). CLK2 is the CLK2 value (Register R13, Bits[18:7]). CLK1 is common to all slopes. ramp (Register R5, Bit DB29 = 1) must be last.
- DELAY 0 TO DELAY 3 ARE ENABLED BY REG 16, BITS[DB19].
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b00.
IF SLOPE 0 AND SLOPE 2 ARE THE SAME).
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b10.
- SLOPE 0, SLOPE 1, SLOPE 2, AND SLOPE 3 MUST BE PROGRAMMED.
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b01.
- SLOPE 0 MUST BE PROGRAMMED.
- RAMP MODE (R11BITS[DB8:DB7]) MUST BE SET TO 0b11.
- SLOPE 0 MUST BE PROGRAMMED.
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b11.
- SLOPE 0 AND SLOPE 1 MUST BE PROGRAMMED.
- SING FULL TRI (REG 11, BIT[DB9]) = 1.
MUST BE NEGATIVE TO DECREASE THE FREQUENCY.
- NEGATIVE VALUES ARE TWOS COMPLEMENT BINARY.
2 DIVIDER (REG 13, BITS[DB18:DB7]) = X
Figure 49. Ramp Sections
Figure 53. FMCW Radar with the ADF5902
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP] obtain the specific Automotive Reliability reports for these models. registered trademarks are the prop erty of their respective owners.