ADF5356BCPZ-RL7

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Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF5356 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

RF output frequency range: 53.125 MHz to 13,600 MHz Noise floor integer channel: −227 dBc/Hz Noise floor fractional channel: −225 dBc/Hz Integrated rms jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output Fractional-N synthesizer and integer N synthesizer Pin compatible to the ADF5355 High resolution, 52-bit modulus Phase frequency detector (PFD) operation to 125 MHz Reference input frequency operation to 600 MHz Maintains frequency lock over −40°C to +85°C Low phase noise, voltage controlled oscillator (VCO) Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output Analog and digital power supplies: 3.3 V Charge pump and VCO power supplies: 5.0 V typical Logic compatibility: 1.8 V Programmable output power level RF output mute function Supported by the ADIsimPLL design tool

APPLICATIONS

Wireless infrastructure (L TE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point and point to multipoint microwave links Satellites and very small aperture terminals (VSATs) Test equipment and instrumentation Clock generation GENERAL DESCRIPTION The ADF5356 allows implementation of fractional-N or integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz. The ADF5356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. Control of all on-chip registers is through a simple 3-wire interface. The ADF5356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V , with charge pump and VCO supplies from 4.75 V to 5.25 V . The ADF5356 also contains hardware and software power-down modes. FUNCTIONAL BLOCK DIAGRAM Figure 1. MUXOUT CPOUT VBIAS REFIN CLK DATA LE AVDD CREG1 CREG2 DVDD VP AGND CE CPGND SDGND AGNDVCO RSET VVCO VTUNE VREF RFOUTB RFOUTA+ RFOUTA– VCO CORE PHASE COMPARATOR CHARGE PUMP OUTPUT STAGE OUTPUT STAGE PDBRF MULTIPLEXER 10-BIT R COUNTER DIVIDER×2 DOUBLER FUNCTION LATCH DATA REGISTER INTEGER REG N COUNTER FRACTION REG THIRD-ORDER FRACTIONAL INTERPOLATOR MODULUS REG MULTIPLEXER LOCK DETECT ÷ 1/2/4/8/ 16/32/64 ADF5356 REFINA B VRF AGNDRF VREGVCO AVDD 15360-001

Rev. 0 | Page 2 of 38 TABLE OF CONTENTS

REVISION HISTORY

8/2017—Revision 0: Initial Version

Rev. 0 | Page 3 of 38 SPECIFICATIONS AVDD = DVDD = VRF = 3.3 V ±5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V , AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V , RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFINA/REFINB CHARACTERISTICS Input Frequency Range For f < 10 MHz, ensure slew rate > 21 V/μs Single-Ended Mode 10 250 MHz Differential Mode 10 600 MHz Input Sensitivity Single-Ended Mode 0.4 AV DD V p-p REF INA biased at AVDD/2; ac coupling ensures AVDD/2 bias Differential Mode 0.4 1.8 V p-p Low voltage differential signaling (LVDS) and Low voltage positive emitter-coupled logic (LVPECL) compatible, REFINA/REFINB biased at 2.1 V; ac coupling ensures 2.1 V bias Input Capacitance Single-Ended Mode 6.9 pF Differential Mode 1.4 pF Input Current ±100 μA Single-ended reference programmed ±250 μA Differential reference programmed PFD 125 MHz CHARGE PUMP (CP) CP Current, Sink/Source ICP R SET = 5.1 kΩ, this resistor is internal in the ADF5356 High Value 4.8 mA Low Value 0.3 mA RSET Range 5.1 kΩ Fixed Current Matching 3 % 0.5 V ≤ V CP1 ≤ VP − 0.5 V ICP vs. VCP 3 % 0.5 V ≤ V CP1 ≤ VP − 0.5 V ICP vs. Temperature 1.5 % V CP1 = 2.5 V LOGIC INPUTS Input Voltage High VINH 1.5 DV DD V Low VINL 0.6 V Input Current, High/Low IINH/IINL ±1 μA Input Capacitance CIN 3.0 pF LOGIC OUTPUTS Output High Voltage VOH DV DD − 0.4 V 3.3 V output selected 1.5 1.8 V 1.8 V output selected Output High Current IOH 500 μA Output Low Voltage VOL 0.4 V I OL2 = 500 μA POWER SUPPLIES See Table 7 Analog Power AVDD 3.15 3.3 3.45 V Digital Power and RF Supply Voltage DVDD, VRF AV DD Voltages must equal AV DD CP and VCO Supply Voltage V P, VVCO 4.75 5.0 5.25 V V P must equal VVCO Total Digital and Analog Current, DIDD + AIDD3 82 92 mA Output Dividers 6 to 36 mA Each output divide by 2 consumes 6 mA CP Supply Power Current IP 8 9 For maximum I CP = 4.8 mA Supply Current IVCO 70 90 mA

Rev. 0 | Page 4 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments RFOUTA+/RFOUTA− and RFOUTB Supply Current IRFOUTx± RF Output A and RF Output B enabled; RF Output A is programmable; enabling RF Output B draws negligible extra current 12 15 mA −4 dBm setting 24 29 mA −1 dBm setting 35 42 mA 2 dBm setting 46 56 mA 5 dBm setting Low Power Sleep Mode 5 mA Hardware power-down selected 20 mA Software power-down selected RF OUTPUT CHARACTERISTICS VCO Frequency Range 3400 6800 MHz Fundamental VCO range RFOUTB Output Frequency 6800 13600 MHz 2× VCO output (RF OUTB), prescaler = 8/9 6800 12000 MHz 2× VCO output (RF OUTB), prescaler = 4/5 RFOUTA+/RFOUTA− Output Frequency 53.125 6800 MHz Prescaler = 8/9 53.125 6000 MHz Prescaler = 4/5 VCO Sensitivity KV 25 MHz/V Frequency Pushing (Open Loop) 12 MHz/V Frequency Pulling (Open Loop) 0.5 MHz Voltage standing wave ratio (VSWR) = 2:1 RFOUTA/RFOUTA−

30 MHz VSWR = 2:1 RF OUTB

Second −26 dBc Fundamental VCO output (RF OUTA+) −29 dBc Divided VCO output (RF OUTA+) Third −32 dBc Fundamental VCO output (RF OUTA+) −14 dBc Divided VCO output (RF OUTA+) Fundamental VCO Feedthrough −10 dBm RF OUTB = 10 GHz RF Output Power4 8 dBm RFOUTA+ = 1 GHz; 7.4 nH inductor to VRF −1 dBm RFOUTA+ = 6.8 GHz; 7.4 nH inductor to VRF 0 dBm RFOUTB = 6.8 GHz 2 dBm RFOUTB = 13.6 GHz Variation ±1 dB RFOUTA+ = 5 GHz ±1 dB RFOUTB = 10 GHz Variation over Frequency ±5 dB RF OUTA+ = 1 GHz to 6.8 GHz ±3 dB RFOUTB = 6.8 GHz to 13.6 GHz Level of Signal with RF Output Disabled −53 dBm RF OUTA+ = 1 GHz −20 dBm RFOUTA+ = 6.8 GHz −16 dBm RFOUTB = 6.8 GHz −12 dBm RFOUTB = 13.6 GHz NOISE CHARACTERISTICS Fundamental VCO Phase Noise Performance VCO noise in open-loop conditions −115 dBc/Hz 100 kHz offset from 3.4 GHz carrier −135 dBc/Hz 800 kHz offset from 3.4 GHz carrier −137 dBc/Hz 1 MHz offset from 3.4 GHz carrier −155 dBc/Hz 10 MHz offset from 3.4 GHz carrier −113 dBc/Hz 100 kHz offset from 5.0 GHz carrier −133 dBc/Hz 800 kHz offset from 5.0 GHz carrier −135 dBc/Hz 1 MHz offset from 5.0 GHz carrier −153 dBc/Hz 10 MHz offset from 5.0 GHz carrier −110 dBc/Hz 100 kHz offset from 6.8 GHz carrier −130 dBc/Hz 800 kHz offset from 6.8 GHz carrier −132 dBc/Hz 1 MHz offset from 6.8 GHz carrier −150 dBc/Hz 10 MHz offset from 6.8 GHz carrier

Rev. 0 | Page 5 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments VCO 2× Phase Noise Performance VCO noise in open-loop conditions −110 dBc/Hz 100 kHz offset from 6.8 GHz carrier −130 dBc/Hz 800 kHz offset from 6.8 GHz carrier −132 dBc/Hz 1 MHz offset from 6.8 GHz carrier −149 dBc/Hz 10 MHz offset from 6.8 GHz carrier −107 dBc/Hz 100 kHz offset from 10 GHz carrier −127 dBc/Hz 800 kHz offset from 10 GHz carrier −129 dBc/Hz 1 MHz offset from 10 GHz carrier −147 dBc/Hz 10 MHz offset from 10 GHz carrier −103 dBc/Hz 100 kHz offset from 13.6 GHz carrier −124 dBc/Hz 800 kHz offset from 13.6 GHz carrier −126 dBc/Hz 1 MHz offset from 13.6 GHz carrier −144 dBc/Hz 10 MHz offset from 13.6 GHz carrier Normalized In-Band Phase Noise Floor Fractional Channel5 −225 dBc/Hz Integer Channel6 −227 dBc/Hz Normalized 1/f Noise, PN1_f7 −121 dBc/Hz 10 kHz offset; normalized to 1 GHz Integrated RMS Jitter (1 kHz to

20 MHz)8

Spurious Signals Due to PFD Frequency −85 dBc 1 VCP is the voltage at the CPOUT pin. 2 IOL is the output low current. 4 RF output power using the EV-ADF5356SD1Z evaluation board is measured by a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins are terminated into 50 Ω. 5 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −225 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel. 6 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −227 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel. 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the ADIsimPLL design tool. 8 Integrated rms jitter using the EV-ADF5356SD1Z evaluation board is measured by a spectrum analyzer. The EV-ADF5356SD1Z evaluation board is configured to accept a single-ended REFIN signal (SMA 100) = 160 MHz, VCO frequency = 6 GHz, fPFD = 80 MHz, charge pump current = 0.9 mA, with bleed current off. The loop filter is configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated into 50 Ω.

to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Write Timing Figure 2. Write Timing Diagram

TA = 25°C, unless otherwise noted. 1 GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V. precautions for handling and assembly. Table 4. Thermal Resistance

1 Thermal impedance simulated values are based on use of a PCB with the

Figure 3. Pin Configuration Table 5. Pin Function Descriptions input is a high impedance CMOS input. logic high on this pin powers up the device, depending on the status of the power-down bits. ground plane as close to these pins as possible. AVDD must have the same value as DVDD. plane as close to this pin as possible. filter is connected to VTUNE to drive the internal VCO. 8 CP GND Charge Pump Ground. This output is the ground return pin for CP OUT. 9 A GND Analog Ground. This pin is the ground return pin for AVDD. possible. VRF must have the same value as AVDD. 13, 15 A GNDRF RF Output Stage Ground. This pin is the ground return pin for the RF output stage. 14 RF OUTB Auxiliary VCO Output. The 2× VCO output is available at this pin. analog ground plane as close to this pin as possible. 18, 21 A GNDVCO VCO Ground. This pin is the gr ound return path for the VCO. 19 V REGVCO VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible. Connect VREGVCO directly to VVCO.

1. NIC = NO INTERNAL CONNECTION. FOR EXISTING DESIGNS THAT CURRENTLY USE THE ADF5355,

TO UPGRADE TO THE ADF5356, THE RSET RESISTOR CAN BE LEFT CONNECTED TO THIS PIN.

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. DVDD

Rev. 0 | Page 9 of 38 Pin No. Mnemonic Description 20 V TUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT output voltage. The capacitance at this pin (VTUNE input capacitance) is 9 pF. 22 NIC No Internal Connection. For existing designs that currently use the ADF5355, to upgrade to the ADF5356, the RSET resistor can be left connected to this pin. 23 V REF Internal Compensation Node. This pin is dc biased at half the tuning range. Connect decoupling capacitors to the ground plane as close to this pin as possible. 24 V BIAS Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible. 25, 32 C REG1, CREG2 Outputs from the LDO Regulator. CREG1 and CREG2 are the supply voltages to the digital circuits. These pins have a nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins. 26 PDB RF RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable. Do not leave this pin floating. 27 DV DD Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground plane as close to this pin as possible. 28 REF INB Complementary Reference Input. If unused, ac couple this pin to AGND. 29 REF INA Reference Input. 30 MUXOUT Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the scaled reference frequency to be externally accessible. 31 SD GND Digital Σ-Δ Modulator Ground. SD GND is the ground return path for the Σ-Δ modulator. EP Exposed Pad. The exposed pad must be connected to A GND.

Register 6 enables this function. only by using the RF Output B enable bit (Bit DB10) in Register 6. Table 7. Total IDD1 (RF Output A Enabled)2

5 V Supply (IVCO and ICP) 74 74 74 74 74

3.3 V Supply (AIDD, DIDD, and

1 IDD is the total current of IVCO, ICP, AIDD, DIDD, and IRFOUTx±. 2 RFOUTA± refers to RFOUTA+/RFOUTA−.

Figure 36. Register Summary (Register 0 to Register 6) 1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0. 2DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.

Figure 37. Register Summary (Register 7 to Register 13) 1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

Figure 38. Register 0 Details Bits[DB31:DB22] are reserved and must be set to 0. calibration, and to choose the appropriate VCO and VCO subband. calibration, which is the recommended mode of operation. Toggling AUTOCAL is also required when changing frequency. See the Frequency Update Sequence section for more information. (Bit DB20) in Register 0 sets the prescaler value. MIN is 23, and if P is 8/9, NMIN is 75.

Figure 41. Register 3 Bit DB31 is reserved and must be set to 0. Σ-Δ reset by writing a 1 to the SD1 bit (Bit DB30). must be set to 1. If unused, the bit can be programmed to 0. adjustments to phase are made continually in an application. Σ-Δ load reset by setting the SD1 bit (Bit DB30) in Register 3 to 1. 1DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY A WRITE TO REGISTER 0.

Figure 42. Register 4 Details Bits[DB31:DB30] are reserved and must be set to 0. Bits[DB29:DB27]. For additional details, see Figure 42. signal directly to the 10-bit R counter, disabling the doubler. active edges at the PFD input. provides a 50% duty cycle signal at the PFD input. Program Modes section explains how double buffering works. 0.90 mA setting is recommended.

1 ENABLED

1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

differential setting for reference frequencies above 250 MHz. logic, and set it to 1 to select 3.3 V logic. tic is used, set this bit to 0 (negative). The U3 bit (Bit DB6) sets the programmable power-down mode.  The charge pump is forced into three-state mode.  The digital lock detect circuitry resets. three-state mode. Set DB5 to 0 for normal operation. synthesizer N counter, R counter, and VCO band select are reset. For normal operation, set DB4 to 0. described in Figure 43, using a hexadecimal word of 0x00800025. Figure 43. Register 5 Details (0x00800025)

Figure 44. Register 6 Details BP1 (Bit DB31) sets the polarity of the charge pump bleed current. and to disable negative bleed, write 0 to BL9. values greater than 100 MHz. Bits[DB28:DB25] are reserved and must be set to 1010. reserved and must be set to 0. signals is required to increase the power.

0 MUTE DISABLED

1 MUTE ENABLED

1BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT, BIT DB14 OF REGISTER 4, IS ENABLED.

Rev. 0 | Page 27 of 38 Charge Pump Bleed Current BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed current added to the charge pump output. This current optimizes the phase noise and spurious levels from the device. Calculate the optimal bleed setting using the following equation: Bleed Value = floor(24 × (f PFD/61.44 MHz) × (ICP/0.9 mA)) where: Bleed Value is the value programmed to Bits[DB20:DB13]. floor() is a function to round down to the nearest integer value. fPFD is the PFD frequency. ICP is the value of charge pump current setting, Bits[DB13:DB10] of Register 4. If fPFD > 100 MHz, disable the bleed current using Bit DB29. Mute Till Lock Detect When D5 (Bit DB11) is set to 1, the supply current to the RF output stage is shut down until the device achieves lock, as determined by the digital lock detect circuitry. RF Output B Enable D4 (Bit DB10) enables or disables RF Output B (RFOUTB). If DB10 is set to 0, RF Output B is enabled. If DB10 is set to 1, RF Output B is disabled. RF Output A Enable D3 (Bit DB6) enables or disables RF Output A (RFOUTA+/RFOUTA−). If DB3 is set to 0, RF Output A is disabled. If DB6 is set to 1, RF Output A is enabled. RF Output A Power D2 and D1 (Bits[DB5:DB4]) set the value of the RF Output A (RFOUTA+/RFOUTA−) power level (see Figure 44).

Figure 45. Register 7 Details synchronization (Bit DB25) must be set to 1. internally with the rising edge of reference input frequency. reference frequency, which can lead to longer lock times. detect high (see Figure 45 for details). enable this functionality, set Bit DB7 to 1.

0 FRACTIONAL-N

0 DISABLED

1 LE SYNCED TO REF IN

Figure 48. Register 10 Details 11, and all other bits in this range must be set to 0. (or the PFD frequency) divided by ADC_CLK_DIV. power-up cases, it defaults to R = 1. so that the ADC clock frequency is 99.417 kHz. If ADC_CLK_DIV is greater than 255, set it to 255.

Figure 51. Register 13 Details compatibility with the ADF5355.

1. Ensure that >16 ADC clock cycles elapse between the write

section for more information.

1. Register 13 (for halved fPFD).
2. Register 6 (bleed current setting using the desired fPFD).
3. Register 4 (with the R divider doubled to halve fPFD).
4. Register 2 (for halved fPFD).
5. Register 1 (for halved fPFD).
6. Ensure that >16 ADC clock cycles elapse between the write

section for more information.

1. Register 0 (for halved f

PFD; autocalibration enabled).

1. Register 13 (for the desired fPFD).
2. Register 4 (with the R divider set for the desired fPFD).
3. Register 2 (for the desired fPFD).
4. Register 1 (for the desired fPFD).
5. Register 0 (for the desired fPFD; autocalibration disabled).

1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

(FRAC1) in Register 1, and the integer value (INT) in Register 0.

75 MHz, the sequence must be as follows:

1. Ensure that >16 ADC clock cycles elapse between the write

section for more information.

1. Register 13 (for halved fPFD).
2. Register 4 (with the R divider doubled to halve fPFD).
3. Register 2 (for halved fPFD).
4. Register 1 (for halved fPFD).
5. Ensure that >16 ADC clock cycles elapse between the write

section for more information.

1. Register 0 (for halved fPFD; autocalibration enabled).
2. Register 13 (for the desired fPFD).
3. Register 4 (with the R divider doubled to halve fPFD)
4. Register 2 (for the desired fPFD).
5. Register 1 (for the desired fPFD).
6. Register 0 (for desired fPFD; autocalibration disabled).

The frequency change occurs on the write to Register 0. RFOUT is the RF output frequency. INT is the integer division factor. MOD1 is the fixed 24-bit modulus. fREFIN is the reference input frequency. D is the reference doubler bit. R is the fREFIN reference division factor. T is the reference divide by 2 bit (0 or 1). Figure 52. Loop Closed Before Output Divider where int() is a function indicating the integer result.

Rev. 0 | Page 34 of 38 REFERENCE DOUBLER AND REFERENCE DIVIDER The on-chip reference doubler allows the input reference signal to be doubled. The doubler is useful for increasing the PFD comparison frequency. To improve the noise performance of the system, increase the PFD frequency. Doubling the PFD frequency typically improves noise performance by 3 dB. The reference divide by 2 divides the reference signal by 2, resulting in a 50% duty cycle PFD frequency. SPURIOUS OPTIMIZATION AND FAST LOCK Narrow loop bandwidths can filter unwanted spurious signals; however, these bandwidths typically have a long lock time. A wider loop bandwidth achieves faster lock times but may lead to increased spurious signals inside the loop bandwidth. OPTIMIZING JITTER For the lowest jitter applications, use the highest possible PFD frequency to minimize the contribution of in-band noise from the PLL. Set the PLL filter bandwidth such that the in-band noise of the PLL intersects with the open-loop noise of the VCO, minimizing the contribution of both to the overall noise. Use the ADIsimPLL design tool for this task. SPUR MECHANISMS This section describes the two different spur mechanisms that arise with a fractional-N synthesizer and methods to minimize them in the ADF5356. Integer Boundary Spurs One mechanism for fractional spur creation is the interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (the purpose of a fractional-N synthesizer), spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or the difference in frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth (thus the name, integer boundary spurs). Reference Spurs Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. Feedthrough of low levels of on-chip reference switching noise, through the prescaler back to the VCO, can result in reference spur levels as high as −85 dBc. PLL LOCK TIME The PLL lock time divides into a number of settings. All of these settings are modeled in the ADIsimPLL design tool. Much faster lock times than those detailed in this data sheet are possible; contact Analog Devices, Inc., for more information. Lock Time—A Worked Example Assume that fPFD = 61.44 MHz, VCO Band Div = ceiling(fPFD/1,600,000) = 39 By combining ALC Wait > (50 μs × fPFD)/Timeout Synthesizer Lock Timeout > (20 μs × fPFD)/Timeout It is found that ALC Wait = 2.5 × Synthesizer Lock Timeout The ALC wait and synthesizer lock timeout values must be set to fulfill this equation. Both values are five bits wide; therefore, the maximum value for either is 31. There are several suitable values. The following values meet the criteria: ALC Wait = 30 Synthesizer Lock Timeout = 12 Finally, rearrange as follows: ALC wait > (50 μs × f PFD)/Timeout Timeout = ceiling((fPFD × 50 μs)/ALC Wait) Timeout = ceiling((61.44 MHz × 50 μs)/30) = 103 Synthesizer Lock Timeout The synthesizer lock timeout ensures that the VCO calibration digital-to-analog (DAC), which forces VTUNE, settles to a steady value for the band select circuitry. The timeout and synthesizer lock timeout variables programmed in Register 9 select the length of time the DAC is allowed to settle to the final voltage, before the VCO calibration process continues to the next phase, which is VCO band selection. The PFD frequency is the clock for this logic, and the duration is set by PFDf TimeoutLock r SynthesizeTimeout  The calculated time must be equal to or greater than 20 μs. VCO Band Selection Use the PFD frequency again as the clock for the band selection process. Calculate this value by fPFD/(VCO Band Selection × 16) < 100 kHz The band selection takes 11 cycles of the previously calculated value. Calculate the duration by 11 × (VCO Band Selection × 16)/fPFD Automatic Level Calibration Timeout Use the automatic level calibration (ALC) function to choose the correct bias current in the ADF5356 VCO core. Calculate the time taken by 30 × ALC Wait × Timeout/fPFD

Rev. 0 | Page 35 of 38 PLL Low-Pass Filter Settling Time The time taken for the loop to settle is inversely proportional to the low-pass filter bandwidth. The settling time is also modeled in the ADIsimPLL design tool. The total lock time for changing frequencies is the sum of the four separate times (synthesizer lock, VCO band selection, ALC timeout, and PLL settling time) and is modeled in the ADIsimPLL design tool.

vital to connect a low noise regulator, such as the ADM7150. Connect the same regulator to the VVCO, VREGVCO, and VP pins. shows the recommended connections. maximize the solder joint size. be plated with 1 oz. of copper to plug the via. Figure 53. Power Supplies

use a pull-up inductor to increase the output power level. Figure 54. Optimum Output Stage unused output or combine it with both outputs using a balun. next appropriate circuit stage. no additional matching components.

Rev. 0 | Page 38 of 38 OUTLINE DIMENSIONS Fig ure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADF5356BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 ADF5356BCPZ-RL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 EV-ADF5356SD1Z Evaluation Board 1 Z = RoHS Compliant Part. 0.50 0.40 0.30 01-26-2016-B 0.50 BSC BOT TOM VIEWTOP VIEW PIN 1 INDICATOR 916 EXPOSED PAD PIN 1 INDICATOR SEATING PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.08 0.30 0.25 0.18 5.10 5.00 SQ 4.90 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

0.25 MIN

3.75 3.60 SQ 3.55 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5. PKG-004570 ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15360-0-8/17(0)