ADF4112BCP

ADF4110 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADF4110/ADF4111/ADF4112/ADF4113 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 RF PLL Frequency Synthesizers

FEATURES

ADF4110: 550 MHz ADF4111: 1.2 GHz ADF4112: 3.0 GHz ADF4113: 4.0 GHz 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (V P) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Antibacklash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Mode

APPLICATIONS

Base Stations for Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment GENERAL DESCRIPTION The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and down- conversion sections of wireless receivers and transmitters. They consist of a low-noise digital PFD (Phase Frequency D etector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be imple- mented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM REFERENCE N = BP + A FUNCTION LATCH PRESCALER P/P +1 13-BIT B COUNTER 6-BIT A COUNTER 14-BIT R COUNTER 24-BIT INPUT REGISTER R COUNTER LATCH A, B COUNTER LATCH PHASE FREQUENCY DETECTOR CHARGE PUMP M3 M2 M1 HIGH Z MUX MUXOUT CP AVDD SDOUT SDOUT FROM FUNCTION LATCH DGNDAGNDCE RFINB RFINA LE DATA CLK REFIN CPGNDVPDVDDAVDD LOCK DETECT ADF4110/ADF4111 ADF4112/ADF4113 RSET CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 1 LOAD LOAD

REV. 0–2– ADF4110/ADF4111/ADF4112/ADF4113–SPECIFICATIONS1 (AVDD = DVDD = 3 V /H11550 10%, 5 V /H11550 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k/H9024; TA = TMIN to TMAX unless otherwise noted) Parameter B Version B Chips 2 Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 25 for Input Circuit. RF Input Frequency Use a square wave for lower frequencies. ADF4110 45/550 45/550 MHz min/max ADF4110 25/550 25/550 MHz min/max Input Level = –10 dBm ADF4111 0.045/1.2 0.045/1.2 GHz min/max ADF4112 0.2/3.0 0.2/3.0 GHz min/max ADF4112 0.1/3.0 0.1/3.0 GHz min/max Input Level = –10 dBm ADF4113 0.2/3.7 0.2/3.7 GHz min/max Input Level = –10 dBm RF Input Sensitivity –15/0 –15/0 dBm min/max Maximum Allowable Prescaler Output Frequency 3 165 165 MHz max RF CHARACTERISTICS (5 V) RF Input Frequency Use a square wave for lower frequencies. ADF4110 25/550 25/550 MHz min/max ADF4111 0.025/1.4 0.025/1.4 GHz min/max ADF4112 0.1/3.0 0.1/3.0 GHz min/max ADF4113 0.2/3.7 0.2/3.7 GHz min/max ADF4113 0.2/4.0 0.2/4.0 GHz min/max Input Level = –5 dBm RF Input Sensitivity –10/0 –10/0 dBm min/max Maximum Allowable Prescaler Output Frequency3 200 200 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 0/100 0/100 MHz min/max Reference Input Sensitivity 4 –5/0 –5/0 dBm min/max AC-Coupled. When DC-Coupled: 0 to VDD max (CMOS-Compatible) REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR Phase Detector Frequency 5 55 55 MHz max CHARGE PUMP ICP Sink/Source Programmable: See Table V High Value 5 5 mA typ With R SET = 4.7 kΩ Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With R SET = 4.7 kΩ RSET Range 2.7/10 2.7/10 k Ω typ See Table V ICP 3-State Leakage Current 1 1 nA typ Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5 ICP vs. Temperature 2 2 % typ V CP = VP/2 LOGIC INPUTS VINH, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min VINL, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max IINH/IINL, Input Current ±1 ±1 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage DV DD – 0.4 DV DD – 0.4 V min I OH = 500 µA VOL, Output Low Voltage 0.4 0.4 V max I OL = 500 µA POWER SUPPLIES AVDD 2.7/5.5 2.7/5.5 V min/V max DVDD AVDD AVDD VP AVDD/6.0 AV DD/6.0 V min/V max AV DD ≤ VP ≤ 6.0 V IDD 6 (AIDD + DIDD ) See Figures 22 and 23 ADF4110 5.5 4.5 mA max 4.5 mA Typical ADF4111 5.5 4.5 mA max 4.5 mA Typical ADF4112 7.5 6.5 mA max 6.5 mA Typical ADF4113 11 8.5 mA max 8.5 mA Typical I P 0.5 0.5 mA max T A = 25°C Low Power Sleep Mode 1 1 µA typ

REV. 0 –3– ADF4110/ADF4111/ADF4112/ADF4113 Parameter B Version B Chips 2 Unit Test Conditions/Comments NOISE CHARACTERISTICS ADF4113 Phase Noise Floor 7 –171 –171 dBc/Hz typ @ 25 kHz PFD Frequency –164 –164 dBc/Hz typ @ 200 kHz PFD Frequency Phase Noise Performance 8 @ VCO Output ADF4110: 540 MHz Output 9 –91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4111: 900 MHz Output 10 –87 –87 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4112: 900 MHz Output 10 –90 –90 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4113: 900 MHz Output 10 –91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4111: 836 MHz Output 11 –78 –78 dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency ADF4112: 1750 MHz Output 12 –86 –86 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4112: 1750 MHz Output 13 –66 –66 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency ADF4112: 1960 MHz Output 14 –84 –84 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4113: 1960 MHz Output 14 –85 –85 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4113: 3100 MHz Output 15 –86 –86 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency Spurious Signals ADF4110: 540 MHz Output 9 –97/–106 –97/–106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4111: 900 MHz Output 10 –98/–110 –98/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4112: 900 MHz Output 10 –91/–100 –91/–100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4113: 900 MHz Output 10 –100/–110 –100/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4111: 836 MHz Output 11 –81/–84 –81/–84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD Frequency ADF4112: 1750 MHz Output 12 –88/–90 –88/–90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4112: 1750 MHz Output 13 –65/–73 –65/–73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency ADF4112: 1960 MHz Output 14 –80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4113: 1960 MHz Output 14 –80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4113: 3100 MHz Output 15 –80/–82 –82/–82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency NOTES 1Operating temperature range is as follows: B Version: –40 °C to +85°C. 2The B Chip specifications are given as typical values. 3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency which is less than this value. 4AVDD = DVDD = 3 V; For AV DD = DVDD = 5 V, use CMOS-compatible levels. 5Guaranteed by design. 6TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RF IN for ADF4110 = 540 MHz; RF IN for ADF4111, ADF4112, ADF4113 = 900 MHz. 7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 8The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III). 9fREFIN = 10 MHz; f PFD = 200 kHz; Offset frequency = 1 kHz; f RF = 540 MHz; N = 2700; Loop B/W = 20 kHz. 10fREFIN = 10 MHz; f PFD = 200 kHz; Offset frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 11fREFIN = 10 MHz; f PFD = 30 kHz; Offset frequency = 300 Hz; f RF = 836 MHz; N = 27867; Loop B/W = 3 kHz. 12fREFIN = 10 MHz; f PFD = 200 kHz; Offset frequency = 1 kHz; f RF = 1750 MHz; N = 8750; Loop B/W = 20 kHz. 13fREFIN = 10 MHz; f PFD = 10 kHz; Offset frequency = 200 Hz; f RF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. 14fREFIN = 10 MHz; f PFD = 200 kHz; Offset frequency = 1 kHz; f RF = 1960 MHz; N = 9800; Loop B/W = 20 kHz. 15fREFIN = 10 MHz; f PFD = 1 MHz; Offset frequency = 1 kHz; f RF = 3100 MHz; N = 3100; Loop B/W = 20 kHz. Specifications subject to change without notice. TIMING CHARACTERISTICS1 Limit at TMIN to TMAX Parameter (B Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLOCK Setup Time t2 10 ns min DATA to CLOCK Hold Time t3 25 ns min CLOCK High Duration t4 25 ns min CLOCK Low Duration t5 10 ns min CLOCK to LE Setup Time t6 20 ns min LE Pulsewidth NOTES 1Guaranteed by design but not production tested. Specifications subject to change without notice. (AVDD = DVDD = 3 V /H11550 10%, 5 V /H11550 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k/H9024; TA = TMIN to TMAX unless otherwise noted)

precautions are recommended to avoid performance degradation or loss of functionality. conditions for extended periods may affect device reliability. 6425 (CMOS) and 303 (Bipolar). *Contact the factory for chip availability. Figure 1. Timing Diagram

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1R SET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the R SET pin is 0.56 V. The relationship between I CP and RSET is I R CP SET max .= 23 5 So, with RSET = 4.7 kΩ, ICPmax = 5 mA. 2 CP Charge Pump Output. When enabled this provides ±ICP to the external loop filter, which in turn drives the external VCO. 3 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 AGND Analog Ground. This is the ground return path of the prescaler. 5R F INB Compleme ntary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 25. 6R F INA Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO. 7A V DD Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AV DD must be the same value as DV DD. 8 REF IN Reference Input. This is a CMOS input with a nominal threshold of V DD/2 and an equivalent input resis- tance of 100 k Ω. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-c oupled. 9 DGND Digital Ground. 10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three- state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2. 11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. 13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be accessed externally. 15 DV DD Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DV DD must be the same value as AV DD. 16 V P Charge Pump Power Supply. This should be greater than or equal to V DD. In systems where V DD is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. PIN CONFIGURATIONS TSSOP TOP VIEW (Not to Scale) RSET VP ADF4110 ADF4111 ADF4112 ADF4113 CP DVDD CPGND MUXOUT AGND LE RFINB DATA RFINA CLK AVDD CE REFIN DGND CHIP SCALE PACKAGE TOP VIEW (Not to Scale) CPGND AGND AGND RFINB RFINA MUXOUT LE DATA CLK CE ADF4110 ADF4111 ADF4112 ADF4113 CP RSET VP DVDD DVDD AVDD AVDD REFIN DGND DGND

Figure 14. ADF4113 Integrated Phase Noise (3100 MHz,

1 MHz, 100 kHz)

Figure 15. ADF4113 Reference Spurs (3100 MHz, 1 MHz, Figure 16. ADF4113 Phase Noise (Referred to CP Output) Figure 17. ADF4113 Phase Noise vs. Temperature Figure 18. ADF4113 Reference Spurs vs. Temperature Figure 19. ADF4113 Reference Spurs (200 kHz) vs.

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –12– Table II. ADF4110 Family Latch Summary N COUNTER LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 B13 B12 B11 B8 B7 B6 B5 B4 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) B3 13-BIT B COUNTER CONTROL BITSRESERVED DB2 DB1 DB0 G1 B10 B9 6-BIT A COUNTER CP GAIN FUNCTION LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)F5 TIMER COUNTER CONTROL CONTROL BITS PRESCALER VALUE DB2 DB1 DB0 PD2 CPI3 CPI2 POWER- DOWN 2 MUXOUT CONTROL CURRENT SETTING CURRENT SETTING FASTLOCK MODE FASTLOCK ENABLE CP THREE- STATE PD POLARITY POWER- DOWN 1 COUNTER RESET P1P2 INITIALIZATION LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)F5 TIMER COUNTER CONTROL CONTROL BITS PRESCALER VALUE DB2 DB1 DB0 PD2 CPI3 CPI2 POWER- DOWN 2 MUXOUT CONTROL CURRENT SETTING CURRENT SETTING FASTLOCK MODE FASTLOCK ENABLE CP THREE- STATE PD POLARITY POWER- DOWN 1 COUNTER RESET P1P2 TEST MODE BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 LDP T2 T1 R14 R13 R12 R11 R10 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R9 14-BIT REFERENCE COUNTER, R CONTROL BITS RESERVED DB2 DB1 DB0 SYNCDLY ABP2 ABP1 ANTI- BACKLASH WIDTHSYNCDLY LOCK DETECT PRECISION REFERENCE COUNTER LATCH X XX X = DON'T CARE X = DON'T CARE

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –13– Table III. Reference Counter Latch Map OPERATIONLDP THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION R14 R13 R12 DIVIDE RATIO 16380 16381 16382 16383 TEST MODE BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 LDP T2 T1 R14 R13 R12 R11 R10 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R9 14-BIT REFERENCE COUNTER CONTROL BITS RESERVED DB2 DB1 DB0 SYNCDLY ABP2 ABP1 ANTI- BACKLASH WIDTHSYNCDLY LOCK DETECT PRECISION ABP1ABP2 3.0ns 1.5ns 6.0ns 3.0ns ANTIBACKLASH PULSEWIDTH SYNCDLY NORMAL OPERATION OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH NONDELAYED VERSION OF RF INPUT NORMAL OPERATION OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH DELAYED VERSION OF RF INPUT OPERATION X X = DON'T CARE

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –14– Table IV. AB Counter Latch Map THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS A COUNTER DIVIDE RATIO B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 8188 8189 8190 8191 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 B13 B12 B11 B8 B7 B6 B5 B4 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) B3 6-BIT A COUNTER CONTROL BITSRESERVED DB2 DB1 DB0 G1 B10 B9 CP GAIN *SEE TABLE 5 F4 (FUNCTION LATCH) FASTLOCK ENABLE* CP GAIN OPERATION CHARGE PUMP CURRENT SETTTING 1 IS PERMANENTLY USED CHARGE PUMP CURRENT SETTING

2 IS PERMANENTLY USED

CHARGE PUMP CURRENT SETTING

1 IS USED

CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT UPON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N X FREF), AT THE OUTPUT, NMIN IS (P2-P). X X = DON'T CARE X

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –15– Table V. Function Latch Map OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DV DD R DIVIDER OUTPUT ANALOG LOCK DETECT (N-CHANNEL OPEN-DRAIN) SERIAL DATA OUTPUT DGND COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET PD POLARITY NEGATIVE POSITIVE CHARGE PUMP OUTPUT NORMAL THREE-STATE CE PIN PD2 PD1 MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN X X X X FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE2 PRESCALER VALUE CPI6 CPI3 CPI5 CPI2 CPI4 CPI1 I CP (mA) 2.7k/H90244.7k/H902410k/H9024 1.09 2.18 3.26 4.35 5.44 6.53 7.62 8.70 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35 CURRENT SETTTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)F5 CONTROL BITS PRESCALER VALUE DB2 DB1 DB0 PD2P1 CPI3 CPI2 POWER- DOWN 2 CURRENT SETTTING TIMER COUNTER CONTROL FASTLOCK MODE FASTLOCK ENABLE CP THREE- STATE PD POLARITY MUXOUT CONTROL POWER- DOWN 1 COUNTER RESET TC4 TC3 TC2 TC1 TIMEOUT (PFD CYCLES) SEE PAGE 17

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –16– Table VI. Initialization Latch Map OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DV DD R DIVIDER OUTPUT ANALOG LOCK DETECT (N-CHANNEL OPEN-DRAIN) SERIAL DATA OUTPUT DGND TC4 TC3 TC2 TC1 TIMEOUT (PFD CYCLES) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET PD POLARITY NEGATIVE POSITIVE CHARGE PUMP OUTPUT NORMAL THREE-STATE CE PIN PD2 PD1 MODE ASYNCHRONOUS POWER- DOWN NORMAL OPERATION ASYNCHRONOUS POWER- DOWN SYNCHRONOUS POWER-DOWN X X X X FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE2 PRESCALER VALUE CPI6 CPI3 CPI5 CPI2 CPI4 CPI1 I CP (mA) 2.7k/H90244.7k/H902410k/H9024 1.09 2.18 3.27 4.35 5.44 6.53 7.62 8.70 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35 CURRENT SETTTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3DB13 CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)F5 CONTROL BITS PRESCALER VALUE DB2 DB1 DB0 PD2P1 CPI3 CPI2 POWER- DOWN 2 CURRENT SETTTING TIMER COUNTER CONTROL FASTLOCK MODE FASTLOCK ENABLE CP THREE- STATE PD POLARITY MUXOUT CONTROL POWER- DOWN 1 COUNTER RESET SEE PAGE 17

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –17– THE FUNCTION LATCH With C2, C1 set to 1, 0, the on-chip function latch will be pro- grammed. Table V shows the input data format for programming the Function Latch. Counter Reset DB2 (F1) is the counter reset bit. When this is “1,” the R counter and the A, B counters are reset. For normal operation this bit should be “0.” Upon powering up, the F1 bit needs to be disabled, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down DB3 (PD1) and DB21 (PD2) on the ADF4110 family, provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asynchronous power-down, the device pow- ers down immediately after latching a “1” into bit PD1, with the condition that PD2 has been loaded with a “0.” In the programmed synchronous power-down, the device power- down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a “1” into bit PD1 (on condition that a “1” has also been loaded to PD2), the device will go into power-down on the occurrence of the next charge pump event. When a power-down is activated (either synchronous or asynchro- nous mode including CE-pin-activated power-down), the following events occur: All active dc current paths are removed. The R, N, and timeout counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital clock detect circuitry is reset. The RF IN input is debiased. The reference input buffer circuitry is disabled. The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, M1 on the ADF4110 family. Table V shows the truth table. Fastlock Enable Bit DB9 of the Function Latch is the Fastlock Enable Bit. Only when this is “1” is Fastlock enabled. Fastlock Mode Bit DB10 of the Function Latch is the Fastlock Enable bit. When Fastlock is enabled, this bit determines which Fastlock Mode is used. If the Fastlock Mode bit is “0” then Fastlock Mode 1 is selected and if the Fastlock Mode bit is “1,” then Fastlock Mode 2 is selected. Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters Fastlock by having a “1” written to the CP Gain bit in the AB counter latch. The device exits Fastlock by having a “0” written to the CP Gain bit in the AB counter latch. Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. The device enters Fastlock by having a “1” written to the CP Gain bit in the AB counter latch. The device exits Fastlock under the control of the Timer Counter. After the timeout period deter- mined by the value in TC4 –TC1, the CP Gain bit in the AB counter latch is automatically reset to “0” and the device reverts to normal mode instead of Fastlock. See Table V for the time- out periods. Timer Counter Control The user has the option of programming two charge pump cur- rents. The intent is that the Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). The normal sequence of events is as follows: The user initially decides what the preferred charge pump cur- rents are going to be. For example, they may choose 2.5 mA as Current Setting 1 and 5 mA as the Current Setting 2. At the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. This is controlled by the Timer Counter Control Bits DB14 to DB11 (TC4–TC1) in the Function Latch. The truth table is given in Table V. When the user wishes to program a new output frequency, he can simply program the AB counter latch with new values for A and B. At the same time, he can set the CP Gain bit to a “1,” which sets the charge pump with the value in CPI6 –CPI4 for a period of time determined by TC4 –TC1. When this time is up, the charge pump current reverts to the value set by CPI3– CPI1. At the same time the CP Gain bit in the A, B Counter latch is reset to 0 and is now ready for the next time the user wishes to change the frequency again. Note that there is an enable feature on the Timer Counter. It is enabled when Fastlock Mode 2 is chosen by setting the Fastlock Mode bit (DB10) in the Function Latch to “1.” Charge Pump Currents CPI3, CPI2, CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table V. Prescaler Value P2 and P1 in the Function Latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 200 MHz. Thus, with an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not. PD Polarity This bit sets the PD Polarity Bit. See Table V. CP Three-State This bit the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.

REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 –18– THE INITIALIZATION LATCH When C2, C1 = 1, 1, the Initialization Latch is programmed. This is essentially the same as the Function Latch (programmed when C2, C1 = 1, 0). However, when the Initialization Latch is programmed an addi- tional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment. If the Latch is programmed for synchronous power-down (CE pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained w hen counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. DEVICE PROGRAMMING AFTER INITIAL POWER-UP After initially powering up the device, there are three ways to program the device. Initialization Latch Method Apply V DD. Program the Initialization Latch ( “11” in 2 LSBs of input word). Make sure that F1 bit is programmed to “0.” Then do an R load (“00” in 2 LSBs). Then do an AB load (“01” in 2 LSBs). When the Initialization Latch is loaded, the following occurs: 1. The function latch contents are loaded. 2. An internal pulse resets the R, A, B, and timeout counters to load state conditions and also three-states the charge pump. Note that the prescaler bandgap reference and the oscillator input buffer are unaffected by the internal reset pulse, allow- ing close phase alignment when counting resumes. 3. Latching the first AB counter data after the initialization word will activate the same internal reset pulse. Successive AB loads will not trigger the internal reset pulse unless there is another initialization. The CE Pin Method Apply VDD. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. Program the Function Latch (10). Program the R Counter Latch (00). Program the AB Counter Latch (01). Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment. Note that after CE goes high, a duration of 1 µs may be required for the prescaler bandgap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after V DD was initially applied. The Counter Reset Method Apply VDD. Do a Function Latch Load (“10” in 2 LSBs). As part of this, load “1” to the F1 bit. This enables the counter reset. Do an R Counter Load (“00” in 2 LSBs) Do an AB Counter Load (“01” in 2 LSBs). Do a Function Latch Load ( “10” in 2 LSBs). As part of this, load “0” to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initial- ization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three- states the charge pump, but does not trigger synchronous power- down. The counter reset method requires an extra function latch load compared to the initialization latch method. RESYNCHRONIZING THE PRESCALER OUTPUT Table III (the Reference Counter Latch Map) shows two bits, DB22 and DB21 that are labelled DLY and SYNC respectively. These bits affect the operation of the prescaler. With SYNC = “1,” the prescaler output is resynchronized with the RF input. This has the effect of reducing jitter due to the prescaler and can lead to an overall improvement in synthesizer phase noise performance. Typically, a 1 dB to 2 dB improve- ment is seen in the ADF4113. The lower bandwidth devices can show an even greater improvement. For example, the ADF4110 phase noise is typically improved by 3 dB when SYNC is enabled. With DLY = “1,” the prescaler output is resynchronized with a delayed version of the RF input. If the SYNC feature is used on the synthesizer, some care must be taken. At some point, (at cer tain temperatures and output frequencies), the delay through the prescaler will coincide with the active edge on RF input and this will cause the SYNC fea- ture to break down. So, it is important when using the SYNC feature to be aware of this. Adding a delay to the RF signal, by programming DLY = “1,” will extend the operating frequency and temperature somewhat. Using the SYNC feature will also increase the value of the AI DD for the device. With a 900 MHz output, the ADF4113 AI DD increases by about 1.3 mA when SYNC is enabled and a further 0.3 mA if DLY is enabled. All the typical performance plots on the data sheet except for Figure 5 apply for DLY and SYNC = “0,” i.e., no resynchroniza- tion or delay enabled.

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 29. Local Oscillator for GSM Base Station the loop filter components values shown in Figure 29. IN terminal of the synthesizer. grammed to monitor various internal signals in the synthesizer. One of these is the LD or lock-detect signal.

8 REFIN

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 31. Local Oscillator Shutdown Circuit Figure 32. Wideband Phase Locked Loop

CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY. Figure 33. Direct Conversion Transmitter Solution available from ADI to implement this solution. temperature) from this portion of the signal chain. The Local Oscillator (LO) is implemented using the ADF4113. channel spacing and an output center frequency of 1960 MHz. The target application is a WCDMA base station transmitter. The LO port of the AD8346 is driven in single-ended fashion. required. The circuit of Figure 33 gives a typical level of –8 dBm. power will be around –10 dBm.

REV. 0–24– C3766 –5–4/00 (rev. 0) PRINTED IN U.S.A. ADF4110/ADF4111/ADF4112/ADF4113 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Chip Scale (CP-20) 610 BOTTOM VIEW (ROTATED 180/H11543) 0.016 (0.40) 0.014 (0.35) 0.079 (2.0) REF 0.079 (2.0) REF DETAIL E 0.020 (0.5) REF LEAD PITCH 0.0079 (0.20) REF 0.0083 (0.211) 0.0079 (0.200) 0.0077 (0.195) SEATING PLANE 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) CONTROLLING DIMENSIONS ARE IN MILLIMETERS 0.0059 (0.15) REF 0.011 (0.275) 0.010 (0.250) 0.009 (0.225) 0.0059 (0.15) REF 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) LEAD OPTION DETAIL E 0.159 (4.05) 0.157 (4.00) 0.156 (3.95) TOP VIEW 0.159 (4.05) 0.157 (4.00) 0.156 (3.95) Thin Shrink Small Outline (RU-16) 16 9 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 0.201 (5.10) 0.193 (4.90) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543